pinctrl_stm32.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017-2020 STMicroelectronics - All Rights Reserved
  4. */
  5. #define LOG_CATEGORY UCLASS_PINCTRL
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <hwspinlock.h>
  9. #include <log.h>
  10. #include <malloc.h>
  11. #include <asm/arch/gpio.h>
  12. #include <asm/gpio.h>
  13. #include <asm/io.h>
  14. #include <dm/device_compat.h>
  15. #include <dm/lists.h>
  16. #include <dm/pinctrl.h>
  17. #include <linux/bitops.h>
  18. #include <linux/err.h>
  19. #include <linux/libfdt.h>
  20. #define MAX_PINS_ONE_IP 70
  21. #define MODE_BITS_MASK 3
  22. #define OSPEED_MASK 3
  23. #define PUPD_MASK 3
  24. #define OTYPE_MSK 1
  25. #define AFR_MASK 0xF
  26. struct stm32_pinctrl_priv {
  27. struct hwspinlock hws;
  28. int pinctrl_ngpios;
  29. struct list_head gpio_dev;
  30. };
  31. struct stm32_gpio_bank {
  32. struct udevice *gpio_dev;
  33. struct list_head list;
  34. };
  35. #ifndef CONFIG_SPL_BUILD
  36. static char pin_name[PINNAME_SIZE];
  37. #define PINMUX_MODE_COUNT 5
  38. static const char * const pinmux_mode[PINMUX_MODE_COUNT] = {
  39. "gpio input",
  40. "gpio output",
  41. "analog",
  42. "unknown",
  43. "alt function",
  44. };
  45. static const char * const pinmux_bias[] = {
  46. [STM32_GPIO_PUPD_NO] = "",
  47. [STM32_GPIO_PUPD_UP] = "pull-up",
  48. [STM32_GPIO_PUPD_DOWN] = "pull-down",
  49. };
  50. static const char * const pinmux_otype[] = {
  51. [STM32_GPIO_OTYPE_PP] = "push-pull",
  52. [STM32_GPIO_OTYPE_OD] = "open-drain",
  53. };
  54. static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
  55. {
  56. struct stm32_gpio_priv *priv = dev_get_priv(dev);
  57. struct stm32_gpio_regs *regs = priv->regs;
  58. u32 af;
  59. u32 alt_shift = (offset % 8) * 4;
  60. u32 alt_index = offset / 8;
  61. af = (readl(&regs->afr[alt_index]) &
  62. GENMASK(alt_shift + 3, alt_shift)) >> alt_shift;
  63. return af;
  64. }
  65. static int stm32_populate_gpio_dev_list(struct udevice *dev)
  66. {
  67. struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
  68. struct udevice *gpio_dev;
  69. struct udevice *child;
  70. struct stm32_gpio_bank *gpio_bank;
  71. int ret;
  72. /*
  73. * parse pin-controller sub-nodes (ie gpio bank nodes) and fill
  74. * a list with all gpio device reference which belongs to the
  75. * current pin-controller. This list is used to find pin_name and
  76. * pin muxing
  77. */
  78. list_for_each_entry(child, &dev->child_head, sibling_node) {
  79. ret = uclass_get_device_by_name(UCLASS_GPIO, child->name,
  80. &gpio_dev);
  81. if (ret < 0)
  82. continue;
  83. gpio_bank = malloc(sizeof(*gpio_bank));
  84. if (!gpio_bank) {
  85. dev_err(dev, "Not enough memory\n");
  86. return -ENOMEM;
  87. }
  88. gpio_bank->gpio_dev = gpio_dev;
  89. list_add_tail(&gpio_bank->list, &priv->gpio_dev);
  90. }
  91. return 0;
  92. }
  93. static int stm32_pinctrl_get_pins_count(struct udevice *dev)
  94. {
  95. struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
  96. struct gpio_dev_priv *uc_priv;
  97. struct stm32_gpio_bank *gpio_bank;
  98. /*
  99. * if get_pins_count has already been executed once on this
  100. * pin-controller, no need to run it again
  101. */
  102. if (priv->pinctrl_ngpios)
  103. return priv->pinctrl_ngpios;
  104. if (list_empty(&priv->gpio_dev))
  105. stm32_populate_gpio_dev_list(dev);
  106. /*
  107. * walk through all banks to retrieve the pin-controller
  108. * pins number
  109. */
  110. list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
  111. uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
  112. priv->pinctrl_ngpios += uc_priv->gpio_count;
  113. }
  114. return priv->pinctrl_ngpios;
  115. }
  116. static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
  117. unsigned int selector,
  118. unsigned int *idx)
  119. {
  120. struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
  121. struct stm32_gpio_bank *gpio_bank;
  122. struct gpio_dev_priv *uc_priv;
  123. int pin_count = 0;
  124. if (list_empty(&priv->gpio_dev))
  125. stm32_populate_gpio_dev_list(dev);
  126. /* look up for the bank which owns the requested pin */
  127. list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
  128. uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
  129. if (selector < (pin_count + uc_priv->gpio_count)) {
  130. /*
  131. * we found the bank, convert pin selector to
  132. * gpio bank index
  133. */
  134. *idx = stm32_offset_to_index(gpio_bank->gpio_dev,
  135. selector - pin_count);
  136. if (IS_ERR_VALUE(*idx))
  137. return NULL;
  138. return gpio_bank->gpio_dev;
  139. }
  140. pin_count += uc_priv->gpio_count;
  141. }
  142. return NULL;
  143. }
  144. static const char *stm32_pinctrl_get_pin_name(struct udevice *dev,
  145. unsigned int selector)
  146. {
  147. struct gpio_dev_priv *uc_priv;
  148. struct udevice *gpio_dev;
  149. unsigned int gpio_idx;
  150. /* look up for the bank which owns the requested pin */
  151. gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
  152. if (!gpio_dev) {
  153. snprintf(pin_name, PINNAME_SIZE, "Error");
  154. } else {
  155. uc_priv = dev_get_uclass_priv(gpio_dev);
  156. snprintf(pin_name, PINNAME_SIZE, "%s%d",
  157. uc_priv->bank_name,
  158. gpio_idx);
  159. }
  160. return pin_name;
  161. }
  162. static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
  163. unsigned int selector,
  164. char *buf,
  165. int size)
  166. {
  167. struct udevice *gpio_dev;
  168. struct stm32_gpio_priv *priv;
  169. const char *label;
  170. int mode;
  171. int af_num;
  172. unsigned int gpio_idx;
  173. u32 pupd, otype;
  174. /* look up for the bank which owns the requested pin */
  175. gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
  176. if (!gpio_dev)
  177. return -ENODEV;
  178. mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label);
  179. dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n",
  180. selector, gpio_idx, mode);
  181. priv = dev_get_priv(gpio_dev);
  182. pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) & PUPD_MASK;
  183. otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK;
  184. switch (mode) {
  185. case GPIOF_UNKNOWN:
  186. /* should never happen */
  187. return -EINVAL;
  188. case GPIOF_UNUSED:
  189. snprintf(buf, size, "%s", pinmux_mode[mode]);
  190. break;
  191. case GPIOF_FUNC:
  192. af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
  193. snprintf(buf, size, "%s %d %s %s", pinmux_mode[mode], af_num,
  194. pinmux_otype[otype], pinmux_bias[pupd]);
  195. break;
  196. case GPIOF_OUTPUT:
  197. snprintf(buf, size, "%s %s %s %s",
  198. pinmux_mode[mode], pinmux_otype[otype],
  199. pinmux_bias[pupd], label ? label : "");
  200. break;
  201. case GPIOF_INPUT:
  202. snprintf(buf, size, "%s %s %s", pinmux_mode[mode],
  203. pinmux_bias[pupd], label ? label : "");
  204. break;
  205. }
  206. return 0;
  207. }
  208. #endif
  209. static int stm32_pinctrl_probe(struct udevice *dev)
  210. {
  211. struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
  212. int ret;
  213. INIT_LIST_HEAD(&priv->gpio_dev);
  214. /* hwspinlock property is optional, just log the error */
  215. ret = hwspinlock_get_by_index(dev, 0, &priv->hws);
  216. if (ret)
  217. dev_dbg(dev, "hwspinlock_get_by_index may have failed (%d)\n",
  218. ret);
  219. return 0;
  220. }
  221. static int stm32_gpio_config(struct gpio_desc *desc,
  222. const struct stm32_gpio_ctl *ctl)
  223. {
  224. struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
  225. struct stm32_gpio_regs *regs = priv->regs;
  226. struct stm32_pinctrl_priv *ctrl_priv;
  227. int ret;
  228. u32 index;
  229. if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
  230. ctl->pupd > 2 || ctl->speed > 3)
  231. return -EINVAL;
  232. ctrl_priv = dev_get_priv(dev_get_parent(desc->dev));
  233. ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10);
  234. if (ret == -ETIME) {
  235. dev_err(desc->dev, "HWSpinlock timeout\n");
  236. return ret;
  237. }
  238. index = (desc->offset & 0x07) * 4;
  239. clrsetbits_le32(&regs->afr[desc->offset >> 3], AFR_MASK << index,
  240. ctl->af << index);
  241. index = desc->offset * 2;
  242. clrsetbits_le32(&regs->moder, MODE_BITS_MASK << index,
  243. ctl->mode << index);
  244. clrsetbits_le32(&regs->ospeedr, OSPEED_MASK << index,
  245. ctl->speed << index);
  246. clrsetbits_le32(&regs->pupdr, PUPD_MASK << index, ctl->pupd << index);
  247. index = desc->offset;
  248. clrsetbits_le32(&regs->otyper, OTYPE_MSK << index, ctl->otype << index);
  249. hwspinlock_unlock(&ctrl_priv->hws);
  250. return 0;
  251. }
  252. static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
  253. {
  254. gpio_dsc->port = (port_pin & 0x1F000) >> 12;
  255. gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
  256. log_debug("GPIO:port= %d, pin= %d\n", gpio_dsc->port, gpio_dsc->pin);
  257. return 0;
  258. }
  259. static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn,
  260. ofnode node)
  261. {
  262. gpio_fn &= 0x00FF;
  263. gpio_ctl->af = 0;
  264. switch (gpio_fn) {
  265. case 0:
  266. gpio_ctl->mode = STM32_GPIO_MODE_IN;
  267. break;
  268. case 1 ... 16:
  269. gpio_ctl->mode = STM32_GPIO_MODE_AF;
  270. gpio_ctl->af = gpio_fn - 1;
  271. break;
  272. case 17:
  273. gpio_ctl->mode = STM32_GPIO_MODE_AN;
  274. break;
  275. default:
  276. gpio_ctl->mode = STM32_GPIO_MODE_OUT;
  277. break;
  278. }
  279. gpio_ctl->speed = ofnode_read_u32_default(node, "slew-rate", 0);
  280. if (ofnode_read_bool(node, "drive-open-drain"))
  281. gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
  282. else
  283. gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
  284. if (ofnode_read_bool(node, "bias-pull-up"))
  285. gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
  286. else if (ofnode_read_bool(node, "bias-pull-down"))
  287. gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
  288. else
  289. gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
  290. log_debug("gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
  291. gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
  292. gpio_ctl->pupd);
  293. return 0;
  294. }
  295. static int stm32_pinctrl_config(ofnode node)
  296. {
  297. u32 pin_mux[MAX_PINS_ONE_IP];
  298. int rv, len;
  299. ofnode subnode;
  300. /*
  301. * check for "pinmux" property in each subnode (e.g. pins1 and pins2 for
  302. * usart1) of pin controller phandle "pinctrl-0"
  303. * */
  304. ofnode_for_each_subnode(subnode, node) {
  305. struct stm32_gpio_dsc gpio_dsc;
  306. struct stm32_gpio_ctl gpio_ctl;
  307. int i;
  308. rv = ofnode_read_size(subnode, "pinmux");
  309. if (rv < 0)
  310. return rv;
  311. len = rv / sizeof(pin_mux[0]);
  312. log_debug("No of pinmux entries= %d\n", len);
  313. if (len > MAX_PINS_ONE_IP)
  314. return -EINVAL;
  315. rv = ofnode_read_u32_array(subnode, "pinmux", pin_mux, len);
  316. if (rv < 0)
  317. return rv;
  318. for (i = 0; i < len; i++) {
  319. struct gpio_desc desc;
  320. log_debug("pinmux = %x\n", *(pin_mux + i));
  321. prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
  322. prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), subnode);
  323. rv = uclass_get_device_by_seq(UCLASS_GPIO,
  324. gpio_dsc.port,
  325. &desc.dev);
  326. if (rv)
  327. return rv;
  328. desc.offset = gpio_dsc.pin;
  329. rv = stm32_gpio_config(&desc, &gpio_ctl);
  330. log_debug("rv = %d\n\n", rv);
  331. if (rv)
  332. return rv;
  333. }
  334. }
  335. return 0;
  336. }
  337. static int stm32_pinctrl_bind(struct udevice *dev)
  338. {
  339. ofnode node;
  340. const char *name;
  341. int ret;
  342. dev_for_each_subnode(node, dev) {
  343. dev_dbg(dev, "bind %s\n", ofnode_get_name(node));
  344. if (!ofnode_is_enabled(node))
  345. continue;
  346. ofnode_get_property(node, "gpio-controller", &ret);
  347. if (ret < 0)
  348. continue;
  349. /* Get the name of each gpio node */
  350. name = ofnode_get_name(node);
  351. if (!name)
  352. return -EINVAL;
  353. /* Bind each gpio node */
  354. ret = device_bind_driver_to_node(dev, "gpio_stm32",
  355. name, node, NULL);
  356. if (ret)
  357. return ret;
  358. dev_dbg(dev, "bind %s\n", name);
  359. }
  360. return 0;
  361. }
  362. #if CONFIG_IS_ENABLED(PINCTRL_FULL)
  363. static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
  364. {
  365. return stm32_pinctrl_config(dev_ofnode(config));
  366. }
  367. #else /* PINCTRL_FULL */
  368. static int stm32_pinctrl_set_state_simple(struct udevice *dev,
  369. struct udevice *periph)
  370. {
  371. const fdt32_t *list;
  372. uint32_t phandle;
  373. ofnode config_node;
  374. int size, i, ret;
  375. list = ofnode_get_property(dev_ofnode(periph), "pinctrl-0", &size);
  376. if (!list)
  377. return -EINVAL;
  378. dev_dbg(dev, "periph->name = %s\n", periph->name);
  379. size /= sizeof(*list);
  380. for (i = 0; i < size; i++) {
  381. phandle = fdt32_to_cpu(*list++);
  382. config_node = ofnode_get_by_phandle(phandle);
  383. if (!ofnode_valid(config_node)) {
  384. dev_err(periph,
  385. "prop pinctrl-0 index %d invalid phandle\n", i);
  386. return -EINVAL;
  387. }
  388. ret = stm32_pinctrl_config(config_node);
  389. if (ret)
  390. return ret;
  391. }
  392. return 0;
  393. }
  394. #endif /* PINCTRL_FULL */
  395. static struct pinctrl_ops stm32_pinctrl_ops = {
  396. #if CONFIG_IS_ENABLED(PINCTRL_FULL)
  397. .set_state = stm32_pinctrl_set_state,
  398. #else /* PINCTRL_FULL */
  399. .set_state_simple = stm32_pinctrl_set_state_simple,
  400. #endif /* PINCTRL_FULL */
  401. #ifndef CONFIG_SPL_BUILD
  402. .get_pin_name = stm32_pinctrl_get_pin_name,
  403. .get_pins_count = stm32_pinctrl_get_pins_count,
  404. .get_pin_muxing = stm32_pinctrl_get_pin_muxing,
  405. #endif
  406. };
  407. static const struct udevice_id stm32_pinctrl_ids[] = {
  408. { .compatible = "st,stm32f429-pinctrl" },
  409. { .compatible = "st,stm32f469-pinctrl" },
  410. { .compatible = "st,stm32f746-pinctrl" },
  411. { .compatible = "st,stm32f769-pinctrl" },
  412. { .compatible = "st,stm32h743-pinctrl" },
  413. { .compatible = "st,stm32mp157-pinctrl" },
  414. { .compatible = "st,stm32mp157-z-pinctrl" },
  415. { }
  416. };
  417. U_BOOT_DRIVER(pinctrl_stm32) = {
  418. .name = "pinctrl_stm32",
  419. .id = UCLASS_PINCTRL,
  420. .of_match = stm32_pinctrl_ids,
  421. .ops = &stm32_pinctrl_ops,
  422. .bind = stm32_pinctrl_bind,
  423. .probe = stm32_pinctrl_probe,
  424. .priv_auto = sizeof(struct stm32_pinctrl_priv),
  425. };