starfive-otp.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
  4. * Author: yanhong <yanhong.wang@starfivetech.com>
  5. *
  6. */
  7. #include <common.h>
  8. #include <clk.h>
  9. #include <dm/device.h>
  10. #include <dm/read.h>
  11. #include <linux/delay.h>
  12. #include <asm/io.h>
  13. #include <misc.h>
  14. /*otp param*/
  15. #define OTP_MEM_START 0x800
  16. #define OTP_MEM_SIZE 0x800
  17. #define OTP_DIV_1US 1000000
  18. /* program pulse time select. default value is 11*/
  19. #define OTP_TPW_TIME 11
  20. /* Read Data Access Time. max 50ns*/
  21. #define OTP_TCD_TIME 20
  22. #define OTP_PAOGRAM_DELAY 100
  23. #define OTP_TURN_ON_DELAY 200
  24. /*timing Register*/
  25. #define OTP_CFGR_DIV_1US_MASK 0xff
  26. #define OTP_CFGR_DIV_1US_SHIFT 8
  27. #define OTP_CFGR_RD_CYC_MASK 0x0f
  28. #define OTP_CFGR_RD_CYC_SHIFT 16
  29. /*status Register*/
  30. #define OTPC_SRR_BUSY (1<<31)
  31. /*otp operation mode select*/
  32. #define OTP_OPRR_OPR_MASK 0x7
  33. #define OTP_OPR_STANDBY 0x0 /* set otp to standby*/
  34. #define OTP_OPR_READ 0x1 /* set otp to read*/
  35. #define OTPC_TIMEOUT_CNT 10000
  36. #define BYTES_PER_INT 4
  37. struct starfive_otp_regs {
  38. u32 otp_cfg; /*timing Register*/
  39. u32 otpc_ie; /*interrupt Enable Register*/
  40. u32 otpc_sr; /*status Register*/
  41. u32 otp_opr; /*operation mode select Register*/
  42. u32 otpc_ctl; /*otp control port*/
  43. u32 otpc_addr; /*otp pa port*/
  44. u32 otpc_din; /*otp pdin port*/
  45. u32 otpc_dout; /*otp pdout*/
  46. };
  47. struct starfive_otp_platdata {
  48. struct starfive_otp_regs __iomem *regs;
  49. struct clk clk;
  50. u32 pclk_hz;
  51. };
  52. static int starfive_otp_regstatus(struct starfive_otp_regs *regs,
  53. u32 mask)
  54. {
  55. int delay = OTPC_TIMEOUT_CNT;
  56. while (readl(&regs->otpc_sr) & mask) {
  57. udelay(OTP_PAOGRAM_DELAY);
  58. delay--;
  59. if (delay <= 0) {
  60. printf("%s: check otp status timeout\n", __func__);
  61. return -ETIMEDOUT;
  62. }
  63. }
  64. return 0;
  65. }
  66. static int starfive_otp_setmode(struct starfive_otp_regs *regs,
  67. u32 mode)
  68. {
  69. writel(mode & OTP_OPRR_OPR_MASK, &regs->otp_opr);
  70. starfive_otp_regstatus(regs, OTPC_SRR_BUSY);
  71. return 0;
  72. }
  73. static int starfive_otp_config(struct udevice *dev)
  74. {
  75. struct starfive_otp_platdata *plat = dev_get_plat(dev);
  76. struct starfive_otp_regs *regs = (struct starfive_otp_regs *)plat->regs;
  77. u32 div_1us;
  78. u32 rd_cyc;
  79. u32 val;
  80. div_1us = plat->pclk_hz / OTP_DIV_1US;
  81. rd_cyc = div_1us / OTP_TCD_TIME + 2;
  82. val = OTP_TPW_TIME;
  83. val |= (rd_cyc & OTP_CFGR_RD_CYC_MASK) << OTP_CFGR_RD_CYC_SHIFT;
  84. val |= (div_1us & OTP_CFGR_DIV_1US_MASK) << OTP_CFGR_DIV_1US_SHIFT;
  85. writel(val, &regs->otp_cfg);
  86. return 0;
  87. }
  88. static int starfive_otp_read(struct udevice *dev, int offset,
  89. void *buf, int size)
  90. {
  91. struct starfive_otp_platdata *plat = dev_get_plat(dev);
  92. void *base = (void *)plat->regs;
  93. u32 *databuf = (u32 *)buf;
  94. u32 data;
  95. int bytescnt;
  96. int i;
  97. if ((size % BYTES_PER_INT) || (offset % BYTES_PER_INT)) {
  98. printf("%s: size and offset must be multiple of 4.\n", __func__);
  99. return -EINVAL;
  100. }
  101. /* check bounds */
  102. if (!buf)
  103. return -EINVAL;
  104. if (offset >= OTP_MEM_SIZE)
  105. return -EINVAL;
  106. if ((offset + size) > OTP_MEM_SIZE)
  107. return -EINVAL;
  108. bytescnt = size / BYTES_PER_INT;
  109. for (i = 0; i < bytescnt; i++) {
  110. starfive_otp_setmode(plat->regs, OTP_OPR_READ);
  111. /* read the value */
  112. data = readl(base + OTP_MEM_START + offset);
  113. starfive_otp_regstatus(plat->regs, OTPC_SRR_BUSY);
  114. starfive_otp_setmode(plat->regs, OTP_OPR_STANDBY);
  115. databuf[i] = data;
  116. offset += 4;
  117. }
  118. return size;
  119. }
  120. static int starfive_otp_probe(struct udevice *dev)
  121. {
  122. starfive_otp_config(dev);
  123. udelay(OTP_TURN_ON_DELAY);
  124. return 0;
  125. }
  126. static int starfive_otp_ofdata_to_platdata(struct udevice *dev)
  127. {
  128. struct starfive_otp_platdata *plat = dev_get_plat(dev);
  129. int ret;
  130. plat->regs = dev_read_addr_ptr(dev);
  131. if (!plat->regs)
  132. goto err;
  133. ret = dev_read_u32(dev, "clock-frequency", &plat->pclk_hz);
  134. if (ret < 0)
  135. goto err;
  136. ret = clk_get_by_name(dev, "apb", &plat->clk);
  137. if (ret)
  138. goto err;
  139. ret = clk_enable(&plat->clk);
  140. if (ret < 0)
  141. goto err;
  142. return 0;
  143. err:
  144. printf("%s init fail.\n", __func__);
  145. return ret;
  146. }
  147. static const struct misc_ops starfive_otp_ops = {
  148. .read = starfive_otp_read,
  149. };
  150. static const struct udevice_id starfive_otp_ids[] = {
  151. { .compatible = "starfive,jh7110-otp" },
  152. {}
  153. };
  154. U_BOOT_DRIVER(starfive_otp) = {
  155. .name = "starfive_otp",
  156. .id = UCLASS_MISC,
  157. .of_match = starfive_otp_ids,
  158. .probe = starfive_otp_probe,
  159. .of_to_plat = starfive_otp_ofdata_to_platdata,
  160. .plat_auto = sizeof(struct starfive_otp_platdata),
  161. .ops = &starfive_otp_ops,
  162. };