qfw_mmio.c 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * MMIO interface for QFW
  4. *
  5. * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
  6. * (C) Copyright 2021 Asherah Connor <ashe@kivikakk.ee>
  7. */
  8. #define LOG_CATEGORY UCLASS_QFW
  9. #include <asm/types.h>
  10. #include <asm/io.h>
  11. #include <dm.h>
  12. #include <dm/device.h>
  13. #include <qfw.h>
  14. struct qfw_mmio {
  15. /*
  16. * Each access to the 64-bit data register can be 8/16/32/64 bits wide.
  17. */
  18. union {
  19. u8 data8;
  20. u16 data16;
  21. u32 data32;
  22. u64 data64;
  23. };
  24. u16 selector;
  25. u8 padding[6];
  26. u64 dma;
  27. };
  28. struct qfw_mmio_plat {
  29. volatile struct qfw_mmio *mmio;
  30. };
  31. static void qfw_mmio_read_entry_io(struct udevice *dev, u16 entry, u32 size,
  32. void *address)
  33. {
  34. struct qfw_mmio_plat *plat = dev_get_plat(dev);
  35. /*
  36. * writing FW_CFG_INVALID will cause read operation to resume at last
  37. * offset, otherwise read will start at offset 0
  38. *
  39. * Note: on platform where the control register is MMIO, the register
  40. * is big endian.
  41. */
  42. if (entry != FW_CFG_INVALID)
  43. plat->mmio->selector = cpu_to_be16(entry);
  44. /* the endianness of data register is string-preserving */
  45. while (size >= 8) {
  46. *(u64 *)address = plat->mmio->data64;
  47. address += 8;
  48. size -= 8;
  49. }
  50. while (size >= 4) {
  51. *(u32 *)address = plat->mmio->data32;
  52. address += 4;
  53. size -= 4;
  54. }
  55. while (size >= 2) {
  56. *(u16 *)address = plat->mmio->data16;
  57. address += 2;
  58. size -= 2;
  59. }
  60. while (size >= 1) {
  61. *(u8 *)address = plat->mmio->data8;
  62. address += 1;
  63. size -= 1;
  64. }
  65. }
  66. /* Read configuration item using fw_cfg DMA interface */
  67. static void qfw_mmio_read_entry_dma(struct udevice *dev, struct qfw_dma *dma)
  68. {
  69. struct qfw_mmio_plat *plat = dev_get_plat(dev);
  70. /* the DMA address register is big-endian */
  71. plat->mmio->dma = cpu_to_be64((uintptr_t)dma);
  72. while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR);
  73. }
  74. static int qfw_mmio_of_to_plat(struct udevice *dev)
  75. {
  76. struct qfw_mmio_plat *plat = dev_get_plat(dev);
  77. plat->mmio = map_physmem(dev_read_addr(dev),
  78. sizeof(struct qfw_mmio),
  79. MAP_NOCACHE);
  80. return 0;
  81. }
  82. static int qfw_mmio_probe(struct udevice *dev)
  83. {
  84. return qfw_register(dev);
  85. }
  86. static struct dm_qfw_ops qfw_mmio_ops = {
  87. .read_entry_io = qfw_mmio_read_entry_io,
  88. .read_entry_dma = qfw_mmio_read_entry_dma,
  89. };
  90. static const struct udevice_id qfw_mmio_ids[] = {
  91. { .compatible = "qemu,fw-cfg-mmio" },
  92. {}
  93. };
  94. U_BOOT_DRIVER(qfw_mmio) = {
  95. .name = "qfw_mmio",
  96. .id = UCLASS_QFW,
  97. .of_match = qfw_mmio_ids,
  98. .plat_auto = sizeof(struct qfw_mmio_plat),
  99. .of_to_plat = qfw_mmio_of_to_plat,
  100. .probe = qfw_mmio_probe,
  101. .ops = &qfw_mmio_ops,
  102. };