p2sb_emul.c 5.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * PCI emulation device for an x86 Primary-to-Sideband bus
  4. *
  5. * Copyright 2019 Google LLC
  6. * Written by Simon Glass <sjg@chromium.org>
  7. */
  8. #define LOG_CATEGORY UCLASS_MISC
  9. #include <common.h>
  10. #include <axi.h>
  11. #include <dm.h>
  12. #include <log.h>
  13. #include <pci.h>
  14. #include <asm/test.h>
  15. #include <p2sb.h>
  16. /**
  17. * struct p2sb_emul_plat - platform data for this device
  18. *
  19. * @command: Current PCI command value
  20. * @bar: Current base address values
  21. */
  22. struct p2sb_emul_plat {
  23. u16 command;
  24. u32 bar[6];
  25. };
  26. enum {
  27. /* This emulator supports 16 different devices */
  28. MEMMAP_SIZE = 16 << PCR_PORTID_SHIFT,
  29. };
  30. static struct pci_bar {
  31. int type;
  32. u32 size;
  33. } barinfo[] = {
  34. { PCI_BASE_ADDRESS_MEM_TYPE_32, MEMMAP_SIZE },
  35. { 0, 0 },
  36. { 0, 0 },
  37. { 0, 0 },
  38. { 0, 0 },
  39. { 0, 0 },
  40. };
  41. struct p2sb_emul_priv {
  42. u8 regs[16];
  43. };
  44. static int sandbox_p2sb_emul_read_config(const struct udevice *emul,
  45. uint offset, ulong *valuep,
  46. enum pci_size_t size)
  47. {
  48. struct p2sb_emul_plat *plat = dev_get_plat(emul);
  49. switch (offset) {
  50. case PCI_COMMAND:
  51. *valuep = plat->command;
  52. break;
  53. case PCI_HEADER_TYPE:
  54. *valuep = PCI_HEADER_TYPE_NORMAL;
  55. break;
  56. case PCI_VENDOR_ID:
  57. *valuep = SANDBOX_PCI_VENDOR_ID;
  58. break;
  59. case PCI_DEVICE_ID:
  60. *valuep = SANDBOX_PCI_P2SB_EMUL_ID;
  61. break;
  62. case PCI_CLASS_DEVICE:
  63. if (size == PCI_SIZE_8) {
  64. *valuep = SANDBOX_PCI_CLASS_SUB_CODE;
  65. } else {
  66. *valuep = (SANDBOX_PCI_CLASS_CODE << 8) |
  67. SANDBOX_PCI_CLASS_SUB_CODE;
  68. }
  69. break;
  70. case PCI_CLASS_CODE:
  71. *valuep = SANDBOX_PCI_CLASS_CODE;
  72. break;
  73. case PCI_BASE_ADDRESS_0:
  74. case PCI_BASE_ADDRESS_1:
  75. case PCI_BASE_ADDRESS_2:
  76. case PCI_BASE_ADDRESS_3:
  77. case PCI_BASE_ADDRESS_4:
  78. case PCI_BASE_ADDRESS_5: {
  79. int barnum;
  80. u32 *bar;
  81. barnum = pci_offset_to_barnum(offset);
  82. bar = &plat->bar[barnum];
  83. *valuep = sandbox_pci_read_bar(*bar, barinfo[barnum].type,
  84. barinfo[barnum].size);
  85. break;
  86. }
  87. case PCI_CAPABILITY_LIST:
  88. *valuep = PCI_CAP_ID_PM_OFFSET;
  89. break;
  90. }
  91. return 0;
  92. }
  93. static int sandbox_p2sb_emul_write_config(struct udevice *emul, uint offset,
  94. ulong value, enum pci_size_t size)
  95. {
  96. struct p2sb_emul_plat *plat = dev_get_plat(emul);
  97. switch (offset) {
  98. case PCI_COMMAND:
  99. plat->command = value;
  100. break;
  101. case PCI_BASE_ADDRESS_0:
  102. case PCI_BASE_ADDRESS_1: {
  103. int barnum;
  104. u32 *bar;
  105. barnum = pci_offset_to_barnum(offset);
  106. bar = &plat->bar[barnum];
  107. log_debug("w bar %d=%lx\n", barnum, value);
  108. *bar = value;
  109. /* space indicator (bit#0) is read-only */
  110. *bar |= barinfo[barnum].type;
  111. break;
  112. }
  113. }
  114. return 0;
  115. }
  116. static int sandbox_p2sb_emul_find_bar(struct udevice *emul, unsigned int addr,
  117. int *barnump, unsigned int *offsetp)
  118. {
  119. struct p2sb_emul_plat *plat = dev_get_plat(emul);
  120. int barnum;
  121. for (barnum = 0; barnum < ARRAY_SIZE(barinfo); barnum++) {
  122. unsigned int size = barinfo[barnum].size;
  123. u32 base = plat->bar[barnum] & ~PCI_BASE_ADDRESS_SPACE;
  124. if (addr >= base && addr < base + size) {
  125. *barnump = barnum;
  126. *offsetp = addr - base;
  127. return 0;
  128. }
  129. }
  130. *barnump = -1;
  131. return -ENOENT;
  132. }
  133. static int sandbox_p2sb_emul_read_io(struct udevice *dev, unsigned int addr,
  134. ulong *valuep, enum pci_size_t size)
  135. {
  136. unsigned int offset;
  137. int barnum;
  138. int ret;
  139. ret = sandbox_p2sb_emul_find_bar(dev, addr, &barnum, &offset);
  140. if (ret)
  141. return ret;
  142. if (barnum == 4)
  143. *valuep = offset;
  144. else if (barnum == 0)
  145. *valuep = offset;
  146. return 0;
  147. }
  148. static int sandbox_p2sb_emul_write_io(struct udevice *dev, unsigned int addr,
  149. ulong value, enum pci_size_t size)
  150. {
  151. unsigned int offset;
  152. int barnum;
  153. int ret;
  154. ret = sandbox_p2sb_emul_find_bar(dev, addr, &barnum, &offset);
  155. if (ret)
  156. return ret;
  157. return 0;
  158. }
  159. static int find_p2sb_channel(struct udevice *emul, uint offset,
  160. struct udevice **devp)
  161. {
  162. uint pid = offset >> PCR_PORTID_SHIFT;
  163. struct udevice *p2sb, *dev;
  164. int ret;
  165. ret = sandbox_pci_get_client(emul, &p2sb);
  166. if (ret)
  167. return log_msg_ret("No client", ret);
  168. device_foreach_child(dev, p2sb) {
  169. struct p2sb_child_plat *pplat =
  170. dev_get_parent_plat(dev);
  171. log_debug(" - child %s, pid %d, want %d\n", dev->name,
  172. pplat->pid, pid);
  173. if (pid == pplat->pid) {
  174. *devp = dev;
  175. return 0;
  176. }
  177. }
  178. return -ENOENT;
  179. }
  180. static int sandbox_p2sb_emul_map_physmem(struct udevice *dev,
  181. phys_addr_t addr, unsigned long *lenp,
  182. void **ptrp)
  183. {
  184. struct p2sb_emul_priv *priv = dev_get_priv(dev);
  185. struct udevice *child = NULL; /* Silence compiler warning */
  186. unsigned int offset;
  187. int barnum;
  188. int ret;
  189. log_debug("map %x: ", (uint)addr);
  190. ret = sandbox_p2sb_emul_find_bar(dev, addr, &barnum, &offset);
  191. if (ret)
  192. return log_msg_ret("Cannot find bar", ret);
  193. log_debug("bar %d, offset %x\n", barnum, offset);
  194. if (barnum != 0)
  195. return log_msg_ret("Unknown BAR", -EINVAL);
  196. ret = find_p2sb_channel(dev, offset, &child);
  197. if (ret)
  198. return log_msg_ret("Cannot find channel", ret);
  199. offset &= ((1 << PCR_PORTID_SHIFT) - 1);
  200. ret = axi_read(child, offset, priv->regs, AXI_SIZE_32);
  201. if (ret)
  202. return log_msg_ret("Child read failed", ret);
  203. *ptrp = priv->regs + (offset & 3);
  204. *lenp = 4;
  205. return 0;
  206. }
  207. static struct dm_pci_emul_ops sandbox_p2sb_emul_emul_ops = {
  208. .read_config = sandbox_p2sb_emul_read_config,
  209. .write_config = sandbox_p2sb_emul_write_config,
  210. .read_io = sandbox_p2sb_emul_read_io,
  211. .write_io = sandbox_p2sb_emul_write_io,
  212. .map_physmem = sandbox_p2sb_emul_map_physmem,
  213. };
  214. static const struct udevice_id sandbox_p2sb_emul_ids[] = {
  215. { .compatible = "sandbox,p2sb-emul" },
  216. { }
  217. };
  218. U_BOOT_DRIVER(sandbox_p2sb_emul_emul) = {
  219. .name = "sandbox_p2sb_emul_emul",
  220. .id = UCLASS_PCI_EMUL,
  221. .of_match = sandbox_p2sb_emul_ids,
  222. .ops = &sandbox_p2sb_emul_emul_ops,
  223. .priv_auto = sizeof(struct p2sb_emul_priv),
  224. .plat_auto = sizeof(struct p2sb_emul_plat),
  225. };
  226. static struct pci_device_id sandbox_p2sb_emul_supported[] = {
  227. { PCI_VDEVICE(SANDBOX, SANDBOX_PCI_PMC_EMUL_ID) },
  228. {},
  229. };
  230. U_BOOT_PCI_DEVICE(sandbox_p2sb_emul_emul, sandbox_p2sb_emul_supported);