intel_broadwell_gpio.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2012 The Chromium OS Authors.
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <errno.h>
  8. #include <fdtdec.h>
  9. #include <log.h>
  10. #include <pch.h>
  11. #include <pci.h>
  12. #include <syscon.h>
  13. #include <asm/cpu.h>
  14. #include <asm/global_data.h>
  15. #include <asm/gpio.h>
  16. #include <asm/io.h>
  17. #include <asm/pci.h>
  18. #include <asm/arch/gpio.h>
  19. #include <dt-bindings/gpio/x86-gpio.h>
  20. DECLARE_GLOBAL_DATA_PTR;
  21. /**
  22. * struct broadwell_bank_priv - Private driver data
  23. *
  24. * @regs: Pointer to GPIO registers
  25. * @bank: Bank number for this bank (0, 1 or 2)
  26. * @offset: GPIO offset for this bank (0, 32 or 64)
  27. */
  28. struct broadwell_bank_priv {
  29. struct pch_lp_gpio_regs *regs;
  30. int bank;
  31. int offset;
  32. };
  33. static int broadwell_gpio_request(struct udevice *dev, unsigned offset,
  34. const char *label)
  35. {
  36. struct broadwell_bank_priv *priv = dev_get_priv(dev);
  37. struct pch_lp_gpio_regs *regs = priv->regs;
  38. u32 val;
  39. /*
  40. * Make sure that the GPIO pin we want isn't already in use for some
  41. * built-in hardware function. We have to check this for every
  42. * requested pin.
  43. */
  44. debug("%s: request bank %d offset %d: ", __func__, priv->bank, offset);
  45. val = inl(&regs->own[priv->bank]);
  46. if (!(val & (1UL << offset))) {
  47. debug("gpio is reserved for internal use\n");
  48. return -EPERM;
  49. }
  50. debug("ok\n");
  51. return 0;
  52. }
  53. static int broadwell_gpio_direction_input(struct udevice *dev, unsigned offset)
  54. {
  55. struct broadwell_bank_priv *priv = dev_get_priv(dev);
  56. struct pch_lp_gpio_regs *regs = priv->regs;
  57. setio_32(&regs->config[priv->offset + offset], CONFA_DIR_INPUT);
  58. return 0;
  59. }
  60. static int broadwell_gpio_get_value(struct udevice *dev, unsigned offset)
  61. {
  62. struct broadwell_bank_priv *priv = dev_get_priv(dev);
  63. struct pch_lp_gpio_regs *regs = priv->regs;
  64. return inl(&regs->config[priv->offset + offset]) & CONFA_LEVEL_HIGH ?
  65. 1 : 0;
  66. }
  67. static int broadwell_gpio_set_value(struct udevice *dev, unsigned offset,
  68. int value)
  69. {
  70. struct broadwell_bank_priv *priv = dev_get_priv(dev);
  71. struct pch_lp_gpio_regs *regs = priv->regs;
  72. debug("%s: dev=%s, offset=%d, value=%d\n", __func__, dev->name, offset,
  73. value);
  74. clrsetio_32(&regs->config[priv->offset + offset], CONFA_OUTPUT_HIGH,
  75. value ? CONFA_OUTPUT_HIGH : 0);
  76. return 0;
  77. }
  78. static int broadwell_gpio_direction_output(struct udevice *dev, unsigned offset,
  79. int value)
  80. {
  81. struct broadwell_bank_priv *priv = dev_get_priv(dev);
  82. struct pch_lp_gpio_regs *regs = priv->regs;
  83. broadwell_gpio_set_value(dev, offset, value);
  84. clrio_32(&regs->config[priv->offset + offset], CONFA_DIR_INPUT);
  85. return 0;
  86. }
  87. static int broadwell_gpio_get_function(struct udevice *dev, unsigned offset)
  88. {
  89. struct broadwell_bank_priv *priv = dev_get_priv(dev);
  90. struct pch_lp_gpio_regs *regs = priv->regs;
  91. u32 mask = 1UL << offset;
  92. if (!(inl(&regs->own[priv->bank]) & mask))
  93. return GPIOF_FUNC;
  94. if (inl(&regs->config[priv->offset + offset]) & CONFA_DIR_INPUT)
  95. return GPIOF_INPUT;
  96. else
  97. return GPIOF_OUTPUT;
  98. }
  99. static int broadwell_gpio_probe(struct udevice *dev)
  100. {
  101. struct broadwell_bank_plat *plat = dev_get_plat(dev);
  102. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  103. struct broadwell_bank_priv *priv = dev_get_priv(dev);
  104. struct udevice *pinctrl;
  105. int ret;
  106. /* Set up pin control if available */
  107. ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl);
  108. debug("%s, pinctrl=%p, ret=%d\n", __func__, pinctrl, ret);
  109. uc_priv->gpio_count = GPIO_PER_BANK;
  110. uc_priv->bank_name = plat->bank_name;
  111. priv->regs = (struct pch_lp_gpio_regs *)(uintptr_t)plat->base_addr;
  112. priv->bank = plat->bank;
  113. priv->offset = priv->bank * 32;
  114. debug("%s: probe done, regs %p, bank %d\n", __func__, priv->regs,
  115. priv->bank);
  116. return 0;
  117. }
  118. static int broadwell_gpio_of_to_plat(struct udevice *dev)
  119. {
  120. struct broadwell_bank_plat *plat = dev_get_plat(dev);
  121. u32 gpiobase;
  122. int bank;
  123. int ret;
  124. ret = pch_get_gpio_base(dev->parent, &gpiobase);
  125. if (ret)
  126. return ret;
  127. bank = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1);
  128. if (bank == -1) {
  129. debug("%s: Invalid bank number %d\n", __func__, bank);
  130. return -EINVAL;
  131. }
  132. plat->bank = bank;
  133. plat->base_addr = gpiobase;
  134. plat->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
  135. "bank-name", NULL);
  136. return 0;
  137. }
  138. static const struct dm_gpio_ops gpio_broadwell_ops = {
  139. .request = broadwell_gpio_request,
  140. .direction_input = broadwell_gpio_direction_input,
  141. .direction_output = broadwell_gpio_direction_output,
  142. .get_value = broadwell_gpio_get_value,
  143. .set_value = broadwell_gpio_set_value,
  144. .get_function = broadwell_gpio_get_function,
  145. };
  146. static const struct udevice_id intel_broadwell_gpio_ids[] = {
  147. { .compatible = "intel,broadwell-gpio" },
  148. { }
  149. };
  150. U_BOOT_DRIVER(gpio_broadwell) = {
  151. .name = "gpio_broadwell",
  152. .id = UCLASS_GPIO,
  153. .of_match = intel_broadwell_gpio_ids,
  154. .ops = &gpio_broadwell_ops,
  155. .of_to_plat = broadwell_gpio_of_to_plat,
  156. .probe = broadwell_gpio_probe,
  157. .priv_auto = sizeof(struct broadwell_bank_priv),
  158. .plat_auto = sizeof(struct broadwell_bank_plat),
  159. };