clk-jh7110.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
  4. * Author: yanhong <yanhong.wang@starfivetech.com>
  5. *
  6. */
  7. #include <common.h>
  8. #include <asm/arch/clk.h>
  9. #include <clk-uclass.h>
  10. #include <clk.h>
  11. #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
  12. #include <dm/device.h>
  13. #include <dm/devres.h>
  14. #include <dm.h>
  15. #include <malloc.h>
  16. #include <log.h>
  17. #include <linux/clk-provider.h>
  18. #include <linux/io.h>
  19. #define STARFIVE_CLK_ENABLE_SHIFT 31 /*[31]*/
  20. #define STARFIVE_CLK_INVERT_SHIFT 30 /*[30]*/
  21. #define STARFIVE_CLK_MUX_SHIFT 24 /*[29:24]*/
  22. #define STARFIVE_CLK_DIV_SHIFT 0 /*[23:0]*/
  23. #define SYS_OFFSET(id) ((id) * 4)
  24. #define STG_OFFSET(id) (((id) - JH7110_CLK_SYS_REG_END) * 4)
  25. #define AON_OFFSET(id) (((id) - JH7110_CLK_STG_REG_END) * 4)
  26. #define VOUT_OFFSET(id) (((id) - JH7110_CLK_VOUT_START) * 4)
  27. struct jh7110_clk_priv {
  28. void __iomem *sys;
  29. void __iomem *stg;
  30. void __iomem *aon;
  31. void __iomem *vout;
  32. };
  33. static const char *cpu_root_sels[2] = {
  34. [0] = "osc",
  35. [1] = "pll0_out",
  36. };
  37. static const char *perh_root_sels[2] = {
  38. [0] = "pll0_out",
  39. [1] = "pll2_out",
  40. };
  41. static const char *bus_root_sels[2] = {
  42. [0] = "osc",
  43. [1] = "pll2_out",
  44. };
  45. static const char *qspi_ref_sels[2] = {
  46. [0] = "osc",
  47. [1] = "u0_cdns_qspi_ref_src",
  48. };
  49. static const char *gmac5_tx_sels[2] = {
  50. [0] = "gmac1_gtxclk",
  51. [1] = "gmac1_rmii_rtx",
  52. };
  53. static const char *u0_dw_gmac5_axi64_clk_tx_sels[2] = {
  54. [0] = "gmac0_gtxclk",
  55. [1] = "gmac0_rmii_rtx",
  56. };
  57. static const char *mclk_sels[2] = {
  58. [0] = "mclk_inner",
  59. [1] = "mclk_ext",
  60. };
  61. static const char *u0_i2stx_4ch_bclk_sels[2] = {
  62. [0] = "i2stx_4ch0_bclk_mst",
  63. [1] = "i2stx_bclk_ext",
  64. };
  65. static const char *u0_dc8200_clk_pix_sels[2] = {
  66. [0] = "dc8200_pix0",
  67. [1] = "hdmitx0_pixelclk",
  68. };
  69. static const char *dom_vout_top_lcd_clk_sels[2] = {
  70. [0] = "u0_dc8200_clk_pix0_out",
  71. [1] = "u0_dc8200_clk_pix1_out",
  72. };
  73. static const char *u0_cdns_dsitx_clk_sels[2] = {
  74. [0] = "dc8200_pix0",
  75. [1] = "hdmitx0_pixelclk",
  76. };
  77. static ulong starfive_clk_get_rate(struct clk *clk)
  78. {
  79. struct clk *c;
  80. int ret;
  81. debug("%s(#%lu)\n", __func__, clk->id);
  82. ret = clk_get_by_id(clk->id, &c);
  83. if (ret)
  84. return ret;
  85. return clk_get_rate(c);
  86. }
  87. static ulong starfive_clk_set_rate(struct clk *clk, unsigned long rate)
  88. {
  89. struct clk *c;
  90. int ret;
  91. debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
  92. ret = clk_get_by_id(clk->id, &c);
  93. if (ret)
  94. return ret;
  95. return clk_set_rate(c, rate);
  96. }
  97. static int __starfive_clk_enable(struct clk *clk, bool enable)
  98. {
  99. struct clk *c;
  100. int ret;
  101. debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
  102. ret = clk_get_by_id(clk->id, &c);
  103. if (ret)
  104. return ret;
  105. if (enable)
  106. ret = clk_enable(c);
  107. else
  108. ret = clk_disable(c);
  109. return ret;
  110. }
  111. static int starfive_clk_disable(struct clk *clk)
  112. {
  113. return __starfive_clk_enable(clk, 0);
  114. }
  115. static int starfive_clk_enable(struct clk *clk)
  116. {
  117. return __starfive_clk_enable(clk, 1);
  118. }
  119. static int starfive_clk_set_parent(struct clk *clk, struct clk *parent)
  120. {
  121. struct clk *c, *cp;
  122. int ret;
  123. debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
  124. ret = clk_get_by_id(clk->id, &c);
  125. if (ret)
  126. return ret;
  127. ret = clk_get_by_id(parent->id, &cp);
  128. if (ret)
  129. return ret;
  130. ret = clk_set_parent(c, cp);
  131. c->dev->parent = cp->dev;
  132. return ret;
  133. }
  134. static const struct clk_ops starfive_clk_ops = {
  135. .set_rate = starfive_clk_set_rate,
  136. .get_rate = starfive_clk_get_rate,
  137. .enable = starfive_clk_enable,
  138. .disable = starfive_clk_disable,
  139. .set_parent = starfive_clk_set_parent,
  140. };
  141. static struct clk *starfive_clk_mux(void __iomem *reg,
  142. const char *name,
  143. unsigned int offset,
  144. u8 width,
  145. const char * const *parent_names,
  146. u8 num_parents)
  147. {
  148. return clk_register_mux(NULL, name, parent_names, num_parents, 0,
  149. reg + offset, STARFIVE_CLK_MUX_SHIFT, width, 0);
  150. }
  151. static struct clk *starfive_clk_gate(void __iomem *reg,
  152. const char *name,
  153. const char *parent_name,
  154. unsigned int offset)
  155. {
  156. return clk_register_gate(NULL, name, parent_name, 0, reg+offset,
  157. STARFIVE_CLK_ENABLE_SHIFT, 0, NULL);
  158. }
  159. static struct clk *starfive_clk_fix_factor(void __iomem *reg,
  160. const char *name,
  161. const char *parent_name,
  162. unsigned int mult,
  163. unsigned int div)
  164. {
  165. return clk_register_fixed_factor(NULL, name, parent_name,
  166. 0, mult, div);
  167. }
  168. static struct clk *starfive_clk_divider(void __iomem *reg,
  169. const char *name,
  170. const char *parent_name,
  171. unsigned int offset,
  172. u8 width)
  173. {
  174. return clk_register_divider(NULL, name, parent_name, 0, reg+offset, 0,
  175. width, CLK_DIVIDER_ONE_BASED);
  176. }
  177. static struct clk *starfive_clk_composite(void __iomem *reg,
  178. const char *name,
  179. const char * const *parent_names,
  180. unsigned int num_parents,
  181. unsigned int offset,
  182. unsigned int mux_width,
  183. unsigned int gate_width,
  184. unsigned int div_width)
  185. {
  186. struct clk *clk = ERR_PTR(-ENOMEM);
  187. struct clk_divider *div = NULL;
  188. struct clk_gate *gate = NULL;
  189. struct clk_mux *mux = NULL;
  190. int mask_arry[4] = {0x1, 0x3, 0x7, 0xF};
  191. int mask;
  192. if (mux_width) {
  193. if (mux_width > 4)
  194. goto fail;
  195. else
  196. mask = mask_arry[mux_width-1];
  197. mux = kzalloc(sizeof(*mux), GFP_KERNEL);
  198. if (!mux)
  199. goto fail;
  200. mux->reg = reg + offset;
  201. mux->mask = mask;
  202. mux->shift = STARFIVE_CLK_MUX_SHIFT;
  203. mux->num_parents = num_parents;
  204. mux->flags = 0;
  205. mux->parent_names = parent_names;
  206. }
  207. if (gate_width) {
  208. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  209. if (!gate)
  210. goto fail;
  211. gate->reg = reg + offset;
  212. gate->bit_idx = STARFIVE_CLK_ENABLE_SHIFT;
  213. gate->flags = 0;
  214. }
  215. if (div_width) {
  216. div = kzalloc(sizeof(*div), GFP_KERNEL);
  217. if (!div)
  218. goto fail;
  219. div->reg = reg + offset;
  220. if ((offset == SYS_OFFSET(JH7110_UART3_CLK_CORE)) ||
  221. (offset == SYS_OFFSET(JH7110_UART4_CLK_CORE)) ||
  222. (offset == SYS_OFFSET(JH7110_UART5_CLK_CORE))) {
  223. div->shift = 8;
  224. div->width = 8;
  225. } else {
  226. div->shift = STARFIVE_CLK_DIV_SHIFT;
  227. div->width = div_width;
  228. }
  229. div->flags = CLK_DIVIDER_ONE_BASED;
  230. div->table = NULL;
  231. }
  232. clk = clk_register_composite(NULL, name,
  233. parent_names, num_parents,
  234. &mux->clk, &clk_mux_ops,
  235. &div->clk, &clk_divider_ops,
  236. &gate->clk, &clk_gate_ops, 0);
  237. if (IS_ERR(clk))
  238. goto fail;
  239. return clk;
  240. fail:
  241. kfree(gate);
  242. kfree(div);
  243. kfree(mux);
  244. return ERR_CAST(clk);
  245. }
  246. static struct clk *starfive_clk_fix_parent_composite(void __iomem *reg,
  247. const char *name,
  248. const char *parent_names,
  249. unsigned int offset,
  250. unsigned int mux_width,
  251. unsigned int gate_width,
  252. unsigned int div_width)
  253. {
  254. const char * const *parents;
  255. parents = &parent_names;
  256. return starfive_clk_composite(reg, name, parents, 1, offset,
  257. mux_width, gate_width, div_width);
  258. }
  259. static struct clk *starfive_clk_gate_divider(void __iomem *reg,
  260. const char *name,
  261. const char *parent,
  262. unsigned int offset,
  263. unsigned int width)
  264. {
  265. const char * const *parent_names;
  266. parent_names = &parent;
  267. return starfive_clk_composite(reg, name, parent_names, 1,
  268. offset, 0, 1, width);
  269. }
  270. static int jh7110_clk_init(struct udevice *dev)
  271. {
  272. struct jh7110_clk_priv *priv = dev_get_priv(dev);
  273. struct starfive_pll_freq conf;
  274. u64 pll;
  275. pll = starfive_jh7110_pll_get_rate(PLL0, &conf);
  276. clk_dm(JH7110_PLL0_OUT,
  277. starfive_clk_fix_factor(priv->sys,
  278. "pll0_out", "osc", conf.fbdiv,
  279. conf.prediv * conf.postdiv1));
  280. pll = starfive_jh7110_pll_get_rate(PLL1, &conf);
  281. clk_dm(JH7110_PLL1_OUT,
  282. starfive_clk_fix_factor(priv->sys,
  283. "pll1_out", "osc", conf.fbdiv,
  284. conf.prediv * conf.postdiv1));
  285. pll = starfive_jh7110_pll_get_rate(PLL2, &conf);
  286. clk_dm(JH7110_PLL2_OUT,
  287. starfive_clk_fix_factor(priv->sys,
  288. "pll2_out", "osc", conf.fbdiv,
  289. conf.prediv * conf.postdiv1));
  290. /*root*/
  291. clk_dm(JH7110_CPU_ROOT,
  292. starfive_clk_mux(priv->sys, "cpu_root",
  293. SYS_OFFSET(JH7110_CPU_ROOT), 1,
  294. cpu_root_sels, ARRAY_SIZE(cpu_root_sels)));
  295. clk_dm(JH7110_CPU_CORE,
  296. starfive_clk_divider(priv->sys,
  297. "cpu_core", "cpu_root",
  298. SYS_OFFSET(JH7110_CPU_CORE), 3));
  299. clk_dm(JH7110_CPU_BUS,
  300. starfive_clk_divider(priv->sys,
  301. "cpu_bus", "cpu_core",
  302. SYS_OFFSET(JH7110_CPU_BUS), 2));
  303. clk_dm(JH7110_DDR_ROOT,
  304. starfive_clk_fix_factor(priv->sys,
  305. "ddr_root", "pll1_out", 1, 1));
  306. clk_dm(JH7110_GMACUSB_ROOT,
  307. starfive_clk_fix_factor(priv->sys,
  308. "gmacusb_root", "pll0_out", 1, 1));
  309. clk_dm(JH7110_PERH_ROOT,
  310. starfive_clk_composite(priv->sys,
  311. "perh_root",
  312. perh_root_sels, ARRAY_SIZE(perh_root_sels),
  313. SYS_OFFSET(JH7110_PERH_ROOT), 1, 0, 2));
  314. clk_dm(JH7110_BUS_ROOT,
  315. starfive_clk_mux(priv->sys, "bus_root",
  316. SYS_OFFSET(JH7110_BUS_ROOT), 1,
  317. bus_root_sels, ARRAY_SIZE(bus_root_sels)));
  318. clk_dm(JH7110_AXI_CFG0,
  319. starfive_clk_divider(priv->sys,
  320. "axi_cfg0", "bus_root",
  321. SYS_OFFSET(JH7110_AXI_CFG0), 2));
  322. clk_dm(JH7110_STG_AXIAHB,
  323. starfive_clk_divider(priv->sys,
  324. "stg_axiahb", "axi_cfg0",
  325. SYS_OFFSET(JH7110_STG_AXIAHB), 2));
  326. clk_dm(JH7110_AHB0,
  327. starfive_clk_gate(priv->sys,
  328. "ahb0", "stg_axiahb",
  329. SYS_OFFSET(JH7110_AHB0)));
  330. clk_dm(JH7110_AHB1,
  331. starfive_clk_gate(priv->sys,
  332. "ahb1", "stg_axiahb",
  333. SYS_OFFSET(JH7110_AHB1)));
  334. clk_dm(JH7110_APB_BUS_FUNC,
  335. starfive_clk_divider(priv->sys,
  336. "apb_bus_func", "stg_axiahb",
  337. SYS_OFFSET(JH7110_APB_BUS_FUNC), 4));
  338. clk_dm(JH7110_PCLK2_MUX_FUNC_PCLK,
  339. starfive_clk_fix_factor(priv->sys,
  340. "u2_pclk_mux_func_pclk", "apb_bus_func", 1, 1));
  341. clk_dm(JH7110_U2_PCLK_MUX_PCLK,
  342. starfive_clk_fix_factor(priv->sys,
  343. "u2_pclk_mux_pclk", "u2_pclk_mux_func_pclk", 1, 1));
  344. clk_dm(JH7110_APB_BUS,
  345. starfive_clk_fix_factor(priv->sys,
  346. "apb_bus", "u2_pclk_mux_pclk", 1, 1));
  347. clk_dm(JH7110_APB0,
  348. starfive_clk_gate(priv->sys,
  349. "apb0", "apb_bus",
  350. SYS_OFFSET(JH7110_APB0)));
  351. clk_dm(JH7110_APB12,
  352. starfive_clk_fix_factor(priv->sys,
  353. "apb12", "apb_bus", 1, 1));
  354. clk_dm(JH7110_AON_APB,
  355. starfive_clk_fix_factor(priv->sys,
  356. "aon_apb", "apb_bus_func", 1, 1));
  357. clk_dm(JH7110_NOCSTG_BUS,
  358. starfive_clk_divider(priv->sys,
  359. "nocstg_bus", "bus_root",
  360. SYS_OFFSET(JH7110_NOCSTG_BUS), 3));
  361. /*QSPI*/
  362. clk_dm(JH7110_QSPI_CLK_AHB,
  363. starfive_clk_gate(priv->sys,
  364. "u0_cdns_qspi_clk_ahb", "ahb1",
  365. SYS_OFFSET(JH7110_QSPI_CLK_AHB)));
  366. clk_dm(JH7110_QSPI_CLK_APB,
  367. starfive_clk_gate(priv->sys,
  368. "u0_cdns_qspi_clk_apb", "apb12",
  369. SYS_OFFSET(JH7110_QSPI_CLK_APB)));
  370. clk_dm(JH7110_QSPI_REF_SRC,
  371. starfive_clk_divider(priv->sys,
  372. "u0_cdns_qspi_ref_src", "gmacusb_root",
  373. SYS_OFFSET(JH7110_QSPI_REF_SRC), 5));
  374. clk_dm(JH7110_QSPI_CLK_REF,
  375. starfive_clk_composite(priv->sys,
  376. "u0_cdns_qspi_clk_ref",
  377. qspi_ref_sels, ARRAY_SIZE(qspi_ref_sels),
  378. SYS_OFFSET(JH7110_QSPI_CLK_REF), 1, 1, 0));
  379. /*SDIO*/
  380. clk_dm(JH7110_SDIO0_CLK_AHB,
  381. starfive_clk_gate(priv->sys,
  382. "u0_dw_sdio_clk_ahb", "ahb0",
  383. SYS_OFFSET(JH7110_SDIO0_CLK_AHB)));
  384. clk_dm(JH7110_SDIO1_CLK_AHB,
  385. starfive_clk_gate(priv->sys,
  386. "u1_dw_sdio_clk_ahb", "ahb0",
  387. SYS_OFFSET(JH7110_SDIO1_CLK_AHB)));
  388. clk_dm(JH7110_SDIO0_CLK_SDCARD,
  389. starfive_clk_fix_parent_composite(priv->sys,
  390. "u0_dw_sdio_clk_sdcard", "axi_cfg0",
  391. SYS_OFFSET(JH7110_SDIO0_CLK_SDCARD), 0, 1, 4));
  392. clk_dm(JH7110_SDIO1_CLK_SDCARD,
  393. starfive_clk_fix_parent_composite(priv->sys,
  394. "u1_dw_sdio_clk_sdcard", "axi_cfg0",
  395. SYS_OFFSET(JH7110_SDIO1_CLK_SDCARD), 0, 1, 4));
  396. /*STG*/
  397. clk_dm(JH7110_USB_125M,
  398. starfive_clk_divider(priv->sys,
  399. "usb_125m", "gmacusb_root",
  400. SYS_OFFSET(JH7110_USB_125M), 4));
  401. clk_dm(JH7110_NOC_BUS_CLK_STG_AXI,
  402. starfive_clk_gate(priv->sys,
  403. "u0_sft7110_noc_bus_clk_stg_axi",
  404. "nocstg_bus",
  405. SYS_OFFSET(JH7110_NOC_BUS_CLK_STG_AXI)));
  406. /*GMAC1*/
  407. clk_dm(JH7110_GMAC5_CLK_AHB,
  408. starfive_clk_gate(priv->sys,
  409. "u1_dw_gmac5_axi64_clk_ahb", "ahb0",
  410. SYS_OFFSET(JH7110_GMAC5_CLK_AHB)));
  411. clk_dm(JH7110_GMAC5_CLK_AXI,
  412. starfive_clk_gate(priv->sys,
  413. "u1_dw_gmac5_axi64_clk_axi", "stg_axiahb",
  414. SYS_OFFSET(JH7110_GMAC5_CLK_AXI)));
  415. clk_dm(JH7110_GMAC_SRC,
  416. starfive_clk_divider(priv->sys,
  417. "gmac_src", "gmacusb_root",
  418. SYS_OFFSET(JH7110_GMAC_SRC), 3));
  419. clk_dm(JH7110_GMAC1_GTXCLK,
  420. starfive_clk_divider(priv->sys,
  421. "gmac1_gtxclk", "gmacusb_root",
  422. SYS_OFFSET(JH7110_GMAC1_GTXCLK), 4));
  423. clk_dm(JH7110_GMAC1_GTXC,
  424. starfive_clk_gate(priv->sys,
  425. "gmac1_gtxc", "gmac1_gtxclk",
  426. SYS_OFFSET(JH7110_GMAC1_GTXC)));
  427. clk_dm(JH7110_GMAC1_RMII_RTX,
  428. starfive_clk_divider(priv->sys,
  429. "gmac1_rmii_rtx", "gmac1_rmii_refin",
  430. SYS_OFFSET(JH7110_GMAC1_RMII_RTX), 5));
  431. clk_dm(JH7110_GMAC5_CLK_PTP,
  432. starfive_clk_gate_divider(priv->sys,
  433. "u1_dw_gmac5_axi64_clk_ptp", "gmac_src",
  434. SYS_OFFSET(JH7110_GMAC5_CLK_PTP), 5));
  435. clk_dm(JH7110_GMAC5_CLK_TX,
  436. starfive_clk_composite(priv->sys,
  437. "u1_dw_gmac5_axi64_clk_tx",
  438. gmac5_tx_sels, ARRAY_SIZE(gmac5_tx_sels),
  439. SYS_OFFSET(JH7110_GMAC5_CLK_TX), 1, 1, 0));
  440. /*GMAC0*/
  441. clk_dm(JH7110_AON_AHB,
  442. starfive_clk_fix_factor(priv->sys, "aon_ahb",
  443. "stg_axiahb", 1, 1));
  444. clk_dm(JH7110_GMAC0_GTXCLK,
  445. starfive_clk_gate_divider(priv->sys, "gmac0_gtxclk",
  446. "gmacusb_root", SYS_OFFSET(JH7110_GMAC0_GTXCLK), 4));
  447. clk_dm(JH7110_GMAC0_PTP,
  448. starfive_clk_gate_divider(priv->sys, "gmac0_ptp",
  449. "gmac_src", SYS_OFFSET(JH7110_GMAC0_PTP), 5));
  450. clk_dm(JH7110_GMAC0_GTXC,
  451. starfive_clk_gate(priv->sys,
  452. "gmac0_gtxc", "gmac0_gtxclk",
  453. SYS_OFFSET(JH7110_GMAC0_GTXC)));
  454. /*UART0*/
  455. clk_dm(JH7110_UART0_CLK_APB,
  456. starfive_clk_gate(priv->sys,
  457. "u0_dw_uart_clk_apb", "apb0",
  458. SYS_OFFSET(JH7110_UART0_CLK_APB)));
  459. clk_dm(JH7110_UART0_CLK_CORE,
  460. starfive_clk_gate(priv->sys,
  461. "u0_dw_uart_clk_core", "osc",
  462. SYS_OFFSET(JH7110_UART0_CLK_CORE)));
  463. /*UART1*/
  464. clk_dm(JH7110_UART1_CLK_APB,
  465. starfive_clk_gate(priv->sys,
  466. "u1_dw_uart_clk_apb", "apb0",
  467. SYS_OFFSET(JH7110_UART1_CLK_APB)));
  468. clk_dm(JH7110_UART1_CLK_CORE,
  469. starfive_clk_gate(priv->sys,
  470. "u1_dw_uart_clk_core", "osc",
  471. SYS_OFFSET(JH7110_UART1_CLK_CORE)));
  472. /*UART2*/
  473. clk_dm(JH7110_UART2_CLK_APB,
  474. starfive_clk_gate(priv->sys,
  475. "u2_dw_uart_clk_apb", "apb0",
  476. SYS_OFFSET(JH7110_UART2_CLK_APB)));
  477. clk_dm(JH7110_UART2_CLK_CORE,
  478. starfive_clk_gate(priv->sys,
  479. "u2_dw_uart_clk_core", "osc",
  480. SYS_OFFSET(JH7110_UART2_CLK_CORE)));
  481. /*UART3*/
  482. clk_dm(JH7110_UART3_CLK_APB,
  483. starfive_clk_gate(priv->sys,
  484. "u3_dw_uart_clk_apb", "apb0",
  485. SYS_OFFSET(JH7110_UART3_CLK_APB)));
  486. clk_dm(JH7110_UART3_CLK_CORE,
  487. starfive_clk_gate_divider(priv->sys,
  488. "u3_dw_uart_clk_core", "perh_root",
  489. SYS_OFFSET(JH7110_UART3_CLK_CORE), 8));
  490. /*UART4*/
  491. clk_dm(JH7110_UART4_CLK_APB,
  492. starfive_clk_gate(priv->sys,
  493. "u4_dw_uart_clk_apb", "apb0",
  494. SYS_OFFSET(JH7110_UART4_CLK_APB)));
  495. clk_dm(JH7110_UART4_CLK_CORE,
  496. starfive_clk_gate_divider(priv->sys,
  497. "u4_dw_uart_clk_core", "perh_root",
  498. SYS_OFFSET(JH7110_UART4_CLK_CORE), 8));
  499. /*UART5*/
  500. clk_dm(JH7110_UART5_CLK_APB,
  501. starfive_clk_gate(priv->sys,
  502. "u5_dw_uart_clk_apb", "apb0",
  503. SYS_OFFSET(JH7110_UART5_CLK_APB)));
  504. clk_dm(JH7110_UART5_CLK_CORE,
  505. starfive_clk_gate_divider(priv->sys,
  506. "u5_dw_uart_clk_core", "perh_root",
  507. SYS_OFFSET(JH7110_UART5_CLK_CORE), 8));
  508. clk_dm(JH7110_STG_APB,
  509. starfive_clk_fix_factor(priv->stg,
  510. "stg_apb", "apb_bus", 1, 1));
  511. /*USB*/
  512. clk_dm(JH7110_USB0_CLK_USB_APB,
  513. starfive_clk_gate(priv->stg,
  514. "u0_cdn_usb_clk_usb_apb", "stg_apb",
  515. STG_OFFSET(JH7110_USB0_CLK_USB_APB)));
  516. clk_dm(JH7110_USB0_CLK_UTMI_APB,
  517. starfive_clk_gate(priv->stg,
  518. "u0_cdn_usb_clk_utmi_apb", "stg_apb",
  519. STG_OFFSET(JH7110_USB0_CLK_UTMI_APB)));
  520. clk_dm(JH7110_USB0_CLK_AXI,
  521. starfive_clk_gate(priv->stg,
  522. "u0_cdn_usb_clk_axi", "stg_axiahb",
  523. STG_OFFSET(JH7110_USB0_CLK_AXI)));
  524. clk_dm(JH7110_USB0_CLK_LPM,
  525. starfive_clk_gate_divider(priv->stg,
  526. "u0_cdn_usb_clk_lpm", "osc",
  527. STG_OFFSET(JH7110_USB0_CLK_LPM), 2));
  528. clk_dm(JH7110_USB0_CLK_STB,
  529. starfive_clk_gate_divider(priv->stg,
  530. "u0_cdn_usb_clk_stb", "osc",
  531. STG_OFFSET(JH7110_USB0_CLK_STB), 3));
  532. clk_dm(JH7110_USB0_CLK_APP_125,
  533. starfive_clk_gate(priv->stg,
  534. "u0_cdn_usb_clk_app_125", "usb_125m",
  535. STG_OFFSET(JH7110_USB0_CLK_APP_125)));
  536. clk_dm(JH7110_USB0_REFCLK,
  537. starfive_clk_divider(priv->stg,
  538. "u0_cdn_usb_refclk", "osc",
  539. STG_OFFSET(JH7110_USB0_REFCLK), 2));
  540. /*GMAC1*/
  541. clk_dm(JH7110_U0_GMAC5_CLK_AHB,
  542. starfive_clk_gate(priv->aon,
  543. "u0_dw_gmac5_axi64_clk_ahb", "aon_ahb",
  544. AON_OFFSET(JH7110_U0_GMAC5_CLK_AHB)));
  545. clk_dm(JH7110_U0_GMAC5_CLK_AXI,
  546. starfive_clk_gate(priv->aon,
  547. "u0_dw_gmac5_axi64_clk_axi", "aon_ahb",
  548. AON_OFFSET(JH7110_U0_GMAC5_CLK_AXI)));
  549. clk_dm(JH7110_GMAC0_RMII_RTX,
  550. starfive_clk_divider(priv->aon,
  551. "gmac0_rmii_rtx", "gmac0_rmii_refin",
  552. AON_OFFSET(JH7110_GMAC0_RMII_RTX), 5));
  553. clk_dm(JH7110_U0_GMAC5_CLK_PTP,
  554. starfive_clk_fix_factor(priv->aon,
  555. "u0_dw_gmac5_axi64_clk_ptp",
  556. "gmac0_ptp", 1, 1));
  557. clk_dm(JH7110_U0_GMAC5_CLK_TX,
  558. starfive_clk_composite(priv->aon,
  559. "u0_dw_gmac5_axi64_clk_tx",
  560. u0_dw_gmac5_axi64_clk_tx_sels,
  561. ARRAY_SIZE(u0_dw_gmac5_axi64_clk_tx_sels),
  562. AON_OFFSET(JH7110_U0_GMAC5_CLK_TX), 1, 1, 0));
  563. /*otp*/
  564. clk_dm(JH7110_OTPC_CLK_APB,
  565. starfive_clk_gate(priv->aon,
  566. "u0_otpc_clk_apb", "aon_apb",
  567. AON_OFFSET(JH7110_OTPC_CLK_APB)));
  568. /*vout*/
  569. clk_dm(JH7110_VOUT_ROOT,
  570. starfive_clk_fix_factor(priv->sys,
  571. "vout_root", "pll2_out", 1, 1));
  572. clk_dm(JH7110_AUDIO_ROOT,
  573. starfive_clk_divider(priv->sys,
  574. "audio_root", "pll2_out",
  575. SYS_OFFSET(JH7110_AUDIO_ROOT), 5));
  576. clk_dm(JH7110_VOUT_SRC,
  577. starfive_clk_gate(priv->sys,
  578. "u0_dom_vout_top_clk_vout_src", "vout_root",
  579. SYS_OFFSET(JH7110_VOUT_SRC)));
  580. clk_dm(JH7110_VOUT_AXI,
  581. starfive_clk_divider(priv->sys,
  582. "vout_axi", "vout_root",
  583. SYS_OFFSET(JH7110_VOUT_AXI), 3));
  584. clk_dm(JH7110_VOUT_TOP_CLK_VOUT_AXI,
  585. starfive_clk_gate(priv->sys,
  586. "u0_dom_vout_top_vout_axi", "vout_axi",
  587. SYS_OFFSET(JH7110_VOUT_TOP_CLK_VOUT_AXI)));
  588. clk_dm(JH7110_NOC_BUS_CLK_DISP_AXI,
  589. starfive_clk_gate(priv->sys,
  590. "u0_sft7110_noc_bus_clk_disp_axi", "vout_axi",
  591. SYS_OFFSET(JH7110_NOC_BUS_CLK_DISP_AXI)));
  592. clk_dm(JH7110_VOUT_TOP_CLK_VOUT_AHB,
  593. starfive_clk_gate(priv->sys,
  594. "u0_dom_vout_top_clk_vout_ahb", "ahb1",
  595. SYS_OFFSET(JH7110_VOUT_TOP_CLK_VOUT_AHB)));
  596. clk_dm(JH7110_MCLK_INNER,
  597. starfive_clk_divider(priv->sys,
  598. "mclk_inner", "audio_root",
  599. SYS_OFFSET(JH7110_MCLK_INNER), 5));
  600. clk_dm(JH7110_MCLK,
  601. starfive_clk_mux(priv->sys, "mclk",
  602. SYS_OFFSET(JH7110_MCLK), 1,
  603. mclk_sels, ARRAY_SIZE(mclk_sels)));
  604. clk_dm(JH7110_I2STX_4CH0_BCLK_MST,
  605. starfive_clk_gate_divider(priv->sys,
  606. "i2stx_4ch0_bclk_mst", "mclk",
  607. SYS_OFFSET(JH7110_I2STX_4CH0_BCLK_MST), 5));
  608. clk_dm(JH7110_I2STX0_4CHBCLK,
  609. starfive_clk_mux(priv->sys, "u0_i2stx_4ch_bclk",
  610. SYS_OFFSET(JH7110_I2STX0_4CHBCLK), 1,
  611. u0_i2stx_4ch_bclk_sels, ARRAY_SIZE(u0_i2stx_4ch_bclk_sels)));
  612. clk_dm(JH7110_VOUT_TOP_CLK_HDMITX0_BCLK,
  613. starfive_clk_fix_factor(priv->sys,
  614. "u0_dom_vout_top_clk_hdmitx0_bclk",
  615. "u0_i2stx_4ch_bclk", 1, 1));
  616. clk_dm(JH7110_VOUT_TOP_CLK_HDMITX0_MCLK,
  617. starfive_clk_gate(priv->sys,
  618. "u0_dom_vout_top_clk_hdmitx0_mclk", "mclk",
  619. SYS_OFFSET(JH7110_VOUT_TOP_CLK_HDMITX0_MCLK)));
  620. clk_dm(JH7110_VOUT_TOP_CLK_MIPIPHY_REF,
  621. starfive_clk_divider(priv->sys,
  622. "u0_dom_vout_top_clk_mipiphy_ref", "osc",
  623. SYS_OFFSET(JH7110_MCLK_INNER), 2));
  624. /*i2c5*/
  625. clk_dm(JH7110_I2C5_CLK_APB,
  626. starfive_clk_gate(priv->sys,
  627. "u5_dw_i2c_clk_apb", "apb0",
  628. SYS_OFFSET(JH7110_I2C5_CLK_APB)));
  629. clk_dm(JH7110_I2C5_CLK_CORE,
  630. starfive_clk_gate(priv->sys,
  631. "u5_dw_i2c_clk_core", "osc",
  632. SYS_OFFSET(JH7110_I2C5_CLK_CORE)));
  633. /*i2c2*/
  634. clk_dm(JH7110_I2C2_CLK_APB,
  635. starfive_clk_gate(priv->sys,
  636. "u2_dw_i2c_clk_apb", "apb0",
  637. SYS_OFFSET(JH7110_I2C2_CLK_APB)));
  638. clk_dm(JH7110_I2C2_CLK_CORE,
  639. starfive_clk_fix_factor(priv->sys,
  640. "u2_dw_i2c_clk_core", "u2_dw_i2c_clk_apb", 1, 1));
  641. /*pcie0*/
  642. clk_dm(JH7110_PCIE0_CLK_TL,
  643. starfive_clk_gate(priv->stg,
  644. "u0_plda_pcie_clk_tl",
  645. "stg_axiahb",
  646. STG_OFFSET(JH7110_PCIE0_CLK_TL)));
  647. clk_dm(JH7110_PCIE0_CLK_AXI_MST0,
  648. starfive_clk_gate(priv->stg,
  649. "u0_plda_pcie_clk_axi_mst0",
  650. "stg_axiahb",
  651. STG_OFFSET(JH7110_PCIE0_CLK_AXI_MST0)));
  652. clk_dm(JH7110_PCIE0_CLK_APB,
  653. starfive_clk_gate(priv->stg,
  654. "u0_plda_pcie_clk_apb",
  655. "stg_apb",
  656. STG_OFFSET(JH7110_PCIE0_CLK_APB)));
  657. /*pcie1*/
  658. clk_dm(JH7110_PCIE1_CLK_TL,
  659. starfive_clk_gate(priv->stg,
  660. "u1_plda_pcie_clk_tl",
  661. "stg_axiahb",
  662. STG_OFFSET(JH7110_PCIE1_CLK_TL)));
  663. clk_dm(JH7110_PCIE1_CLK_AXI_MST0,
  664. starfive_clk_gate(priv->stg,
  665. "u1_plda_pcie_clk_axi_mst0",
  666. "stg_axiahb",
  667. STG_OFFSET(JH7110_PCIE1_CLK_AXI_MST0)));
  668. clk_dm(JH7110_PCIE1_CLK_APB,
  669. starfive_clk_gate(priv->stg,
  670. "u1_plda_pcie_clk_apb",
  671. "stg_apb",
  672. STG_OFFSET(JH7110_PCIE1_CLK_APB)));
  673. return 0;
  674. }
  675. static int jh7110_clk_vout_init(struct udevice *dev)
  676. {
  677. struct jh7110_clk_priv *priv = dev_get_priv(dev);
  678. clk_dm(JH7110_DISP_ROOT,
  679. starfive_clk_fix_factor(priv->vout,
  680. "disp_root", "u0_dom_vout_top_clk_vout_src",
  681. 1, 1));
  682. clk_dm(JH7110_DISP_AXI,
  683. starfive_clk_fix_factor(priv->vout,
  684. "disp_axi", "u0_dom_vout_top_vout_axi",
  685. 1, 1));
  686. clk_dm(JH7110_DISP_AHB,
  687. starfive_clk_fix_factor(priv->vout,
  688. "disp_ahb", "u0_dom_vout_top_clk_vout_ahb",
  689. 1, 1));
  690. clk_dm(JH7110_HDMITX0_MCLK,
  691. starfive_clk_fix_factor(priv->vout,
  692. "hdmitx0_mclk", "u0_dom_vout_top_clk_hdmitx0_mclk",
  693. 1, 1));
  694. clk_dm(JH7110_HDMITX0_SCK,
  695. starfive_clk_fix_factor(priv->vout,
  696. "hdmitx0_sck", "u0_dom_vout_top_clk_hdmitx0_bclk",
  697. 1, 1));
  698. clk_dm(JH7110_APB,
  699. starfive_clk_divider(priv->vout,
  700. "apb", "disp_ahb",
  701. VOUT_OFFSET(JH7110_APB), 5));
  702. clk_dm(JH7110_U0_PCLK_MUX_FUNC_PCLK,
  703. starfive_clk_fix_factor(priv->vout,
  704. "u0_pclk_mux_func_pclk", "apb",
  705. 1, 1));
  706. clk_dm(JH7110_DISP_APB,
  707. starfive_clk_fix_factor(priv->vout,
  708. "disp_apb", "u0_pclk_mux_func_pclk",
  709. 1, 1));
  710. clk_dm(JH7110_TX_ESC,
  711. starfive_clk_divider(priv->vout,
  712. "tx_esc", "disp_ahb",
  713. VOUT_OFFSET(JH7110_TX_ESC), 5));
  714. clk_dm(JH7110_DC8200_PIX0,
  715. starfive_clk_divider(priv->vout,
  716. "dc8200_pix0", "disp_root",
  717. VOUT_OFFSET(JH7110_DC8200_PIX0), 6));
  718. clk_dm(JH7110_DSI_SYS,
  719. starfive_clk_divider(priv->vout,
  720. "dsi_sys", "disp_root",
  721. VOUT_OFFSET(JH7110_DSI_SYS), 5));
  722. clk_dm(JH7110_U0_DC8200_CLK_PIX0,
  723. starfive_clk_composite(priv->vout,
  724. "u0_dc8200_clk_pix0",
  725. u0_dc8200_clk_pix_sels,
  726. ARRAY_SIZE(u0_dc8200_clk_pix_sels),
  727. VOUT_OFFSET(JH7110_U0_DC8200_CLK_PIX0), 1, 1, 0));
  728. clk_dm(JH7110_U0_DC8200_CLK_PIX1,
  729. starfive_clk_composite(priv->vout,
  730. "u0_dc8200_clk_pix1",
  731. u0_dc8200_clk_pix_sels,
  732. ARRAY_SIZE(u0_dc8200_clk_pix_sels),
  733. VOUT_OFFSET(JH7110_U0_DC8200_CLK_PIX1), 1, 1, 0));
  734. clk_dm(JH7110_U0_DC8200_CLK_AXI,
  735. starfive_clk_gate(priv->vout,
  736. "u0_dc8200_clk_axi", "disp_axi",
  737. VOUT_OFFSET(JH7110_U0_DC8200_CLK_AXI)));
  738. clk_dm(JH7110_U0_DC8200_CLK_CORE,
  739. starfive_clk_gate(priv->vout,
  740. "u0_dc8200_clk_core", "disp_axi",
  741. VOUT_OFFSET(JH7110_U0_DC8200_CLK_CORE)));
  742. clk_dm(JH7110_U0_DC8200_CLK_AHB,
  743. starfive_clk_gate(priv->vout,
  744. "u0_dc8200_clk_ahb", "disp_ahb",
  745. VOUT_OFFSET(JH7110_U0_DC8200_CLK_AHB)));
  746. clk_dm(JH7110_U0_DC8200_CLK_PIX0_OUT,
  747. starfive_clk_fix_factor(priv->vout,
  748. "u0_dc8200_clk_pix0_out", "u0_dc8200_clk_pix0",
  749. 1, 1));
  750. clk_dm(JH7110_U0_DC8200_CLK_PIX1_OUT,
  751. starfive_clk_fix_factor(priv->sys,
  752. "u0_dc8200_clk_pix1_out", "u0_dc8200_clk_pix1",
  753. 1, 1));
  754. clk_dm(JH7110_DOM_VOUT_TOP_LCD_CLK,
  755. starfive_clk_composite(priv->vout,
  756. "dom_vout_top_lcd_clk",
  757. dom_vout_top_lcd_clk_sels,
  758. ARRAY_SIZE(dom_vout_top_lcd_clk_sels),
  759. VOUT_OFFSET(JH7110_DOM_VOUT_TOP_LCD_CLK), 1, 1, 0));
  760. clk_dm(JH7110_U0_MIPITX_DPHY_CLK_TXESC,
  761. starfive_clk_gate(priv->vout,
  762. "u0_mipitx_dphy_clk_txesc", "tx_esc",
  763. VOUT_OFFSET(JH7110_U0_MIPITX_DPHY_CLK_TXESC)));
  764. clk_dm(JH7110_U0_CDNS_DSITX_CLK_SYS,
  765. starfive_clk_gate(priv->vout,
  766. "u0_cdns_dsiTx_clk_sys", "dsi_sys",
  767. VOUT_OFFSET(JH7110_U0_CDNS_DSITX_CLK_SYS)));
  768. clk_dm(JH7110_U0_CDNS_DSITX_CLK_APB,
  769. starfive_clk_gate(priv->vout,
  770. "u0_cdns_dsiTx_clk_apb", "dsi_sys",
  771. VOUT_OFFSET(JH7110_U0_CDNS_DSITX_CLK_APB)));
  772. clk_dm(JH7110_U0_CDNS_DSITX_CLK_TXESC,
  773. starfive_clk_gate(priv->vout,
  774. "u0_cdns_dsiTx_clk_txesc", "tx_esc",
  775. VOUT_OFFSET(JH7110_U0_CDNS_DSITX_CLK_TXESC)));
  776. clk_dm(JH7110_U0_CDNS_DSITX_CLK_DPI,
  777. starfive_clk_composite(priv->vout,
  778. "u0_cdns_dsitx_clk_api",
  779. u0_cdns_dsitx_clk_sels,
  780. ARRAY_SIZE(u0_cdns_dsitx_clk_sels),
  781. VOUT_OFFSET(JH7110_U0_CDNS_DSITX_CLK_DPI), 1, 1, 0));
  782. clk_dm(JH7110_U0_HDMI_TX_CLK_SYS,
  783. starfive_clk_gate(priv->vout,
  784. "u0_hdmi_tx_clk_sys", "disp_apb",
  785. VOUT_OFFSET(JH7110_U0_HDMI_TX_CLK_SYS)));
  786. clk_dm(JH7110_U0_HDMI_TX_CLK_MCLK,
  787. starfive_clk_gate(priv->vout,
  788. "u0_hdmi_tx_clk_mclk", "hdmitx0_mclk",
  789. VOUT_OFFSET(JH7110_U0_HDMI_TX_CLK_MCLK)));
  790. clk_dm(JH7110_U0_HDMI_TX_CLK_BCLK,
  791. starfive_clk_gate(priv->vout,
  792. "u0_hdmi_tx_clk_bclk", "hdmitx0_sck",
  793. VOUT_OFFSET(JH7110_U0_HDMI_TX_CLK_BCLK)));
  794. return 0;
  795. }
  796. static int jh7110_clk_vout_probe(struct udevice *dev)
  797. {
  798. struct jh7110_clk_priv *priv = dev_get_priv(dev);
  799. priv->vout = (void __iomem *)dev_read_addr(dev);
  800. if (!priv->vout)
  801. return -EINVAL;
  802. return jh7110_clk_vout_init(dev);
  803. }
  804. static int jh7110_clk_probe(struct udevice *dev)
  805. {
  806. struct jh7110_clk_priv *priv = dev_get_priv(dev);
  807. priv->aon = dev_remap_addr_name(dev, "aon");
  808. if (!priv->aon)
  809. return -EINVAL;
  810. priv->sys = dev_remap_addr_name(dev, "sys");
  811. if (!priv->sys)
  812. return -EINVAL;
  813. priv->stg = dev_remap_addr_name(dev, "stg");
  814. if (!priv->stg)
  815. return -EINVAL;
  816. return jh7110_clk_init(dev);
  817. }
  818. static const struct udevice_id jh7110_clk_of_match[] = {
  819. { .compatible = "starfive,jh7110-clkgen" },
  820. { }
  821. };
  822. U_BOOT_DRIVER(jh7110_clk) = {
  823. .name = "jh7110_clk",
  824. .id = UCLASS_CLK,
  825. .of_match = jh7110_clk_of_match,
  826. .probe = jh7110_clk_probe,
  827. .ops = &starfive_clk_ops,
  828. .priv_auto = sizeof(struct jh7110_clk_priv),
  829. };
  830. static const struct udevice_id jh7110_clk_vout_of_match[] = {
  831. { .compatible = "starfive,jh7110-clk-vout" },
  832. { }
  833. };
  834. U_BOOT_DRIVER(jh7110_clk_vout) = {
  835. .name = "jh7110_clk_vout",
  836. .id = UCLASS_CLK,
  837. .of_match = jh7110_clk_vout_of_match,
  838. .probe = jh7110_clk_vout_probe,
  839. .ops = &starfive_clk_ops,
  840. .priv_auto = sizeof(struct jh7110_clk_priv),
  841. };