clk_octeon.c 1.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2020 Stefan Roese <sr@denx.de>
  4. */
  5. #include <clk-uclass.h>
  6. #include <dm.h>
  7. #include <asm/global_data.h>
  8. #include <dt-bindings/clock/octeon-clock.h>
  9. DECLARE_GLOBAL_DATA_PTR;
  10. struct octeon_clk_priv {
  11. u64 core_clk;
  12. u64 io_clk;
  13. };
  14. static int octeon_clk_enable(struct clk *clk)
  15. {
  16. /* Nothing to do on Octeon */
  17. return 0;
  18. }
  19. static ulong octeon_clk_get_rate(struct clk *clk)
  20. {
  21. struct octeon_clk_priv *priv = dev_get_priv(clk->dev);
  22. switch (clk->id) {
  23. case OCTEON_CLK_CORE:
  24. return priv->core_clk;
  25. case OCTEON_CLK_IO:
  26. return priv->io_clk;
  27. default:
  28. return 0;
  29. }
  30. return 0;
  31. }
  32. static struct clk_ops octeon_clk_ops = {
  33. .enable = octeon_clk_enable,
  34. .get_rate = octeon_clk_get_rate,
  35. };
  36. static const struct udevice_id octeon_clk_ids[] = {
  37. { .compatible = "mrvl,octeon-clk" },
  38. { /* sentinel */ }
  39. };
  40. static int octeon_clk_probe(struct udevice *dev)
  41. {
  42. struct octeon_clk_priv *priv = dev_get_priv(dev);
  43. /*
  44. * The clock values are already read into GD, lets just store them
  45. * in priv data
  46. */
  47. priv->core_clk = gd->cpu_clk;
  48. priv->io_clk = gd->bus_clk;
  49. return 0;
  50. }
  51. U_BOOT_DRIVER(clk_octeon) = {
  52. .name = "clk_octeon",
  53. .id = UCLASS_CLK,
  54. .of_match = octeon_clk_ids,
  55. .ops = &octeon_clk_ops,
  56. .probe = octeon_clk_probe,
  57. .priv_auto = sizeof(struct octeon_clk_priv),
  58. };