starfive_evb.c 7.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
  4. * Author: yanhong <yanhong.wang@starfivetech.com>
  5. *
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/jh7110-regs.h>
  10. #include <cpu_func.h>
  11. #include <dm/uclass.h>
  12. #include <dm/device.h>
  13. #include <env.h>
  14. #include <inttypes.h>
  15. #include <misc.h>
  16. #include <linux/bitops.h>
  17. #include <asm/arch/gpio.h>
  18. #include <bmp_logo.h>
  19. #include <video.h>
  20. #include <splash.h>
  21. enum chip_type_t {
  22. CHIP_A = 0,
  23. CHIP_B,
  24. CHIP_MAX,
  25. };
  26. enum cpu_voltage_type_t {
  27. CPU_VOL_1020 = 0xef0,
  28. CPU_VOL_1040 = 0xfff,
  29. CPU_VOL_1060 = 0xff0,
  30. CPU_VOL_1080 = 0xfe0,
  31. CPU_VOL_1100 = 0xf80,
  32. CPU_VOL_1120 = 0xf00,
  33. };
  34. #define CPU_VOL_MASK 0xfff
  35. #define SYS_CLOCK_ENABLE(clk) \
  36. setbits_le32(SYS_CRG_BASE + clk, CLK_ENABLE_MASK)
  37. #define CPU_VOL_BINNING_OFFSET 0x7fc
  38. static void sys_reset_clear(ulong assert, ulong status, u32 rst)
  39. {
  40. u32 value;
  41. clrbits_le32(SYS_CRG_BASE + assert, BIT(rst));
  42. do {
  43. value = in_le32(SYS_CRG_BASE + status);
  44. } while ((value & BIT(rst)) != BIT(rst));
  45. }
  46. static void jh7110_timer_init(void)
  47. {
  48. SYS_CLOCK_ENABLE(TIMER_CLK_APB_SHIFT);
  49. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER0_SHIFT);
  50. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER1_SHIFT);
  51. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER2_SHIFT);
  52. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER3_SHIFT);
  53. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  54. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_APB_SHIFT);
  55. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  56. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER0_SHIFT);
  57. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  58. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER1_SHIFT);
  59. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  60. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER2_SHIFT);
  61. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  62. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER3_SHIFT);
  63. }
  64. static void jh7110_gmac_sel_tx_to_rgmii(int id)
  65. {
  66. switch (id) {
  67. case 0:
  68. clrsetbits_le32(AON_CRG_BASE + GMAC5_0_CLK_TX_SHIFT,
  69. GMAC5_0_CLK_TX_MASK,
  70. BIT(GMAC5_0_CLK_TX_BIT) & GMAC5_0_CLK_TX_MASK);
  71. break;
  72. case 1:
  73. clrsetbits_le32(SYS_CRG_BASE + GMAC5_1_CLK_TX_SHIFT,
  74. GMAC5_1_CLK_TX_MASK,
  75. BIT(GMAC5_1_CLK_TX_BIT) & GMAC5_1_CLK_TX_MASK);
  76. break;
  77. default:
  78. break;
  79. }
  80. }
  81. static void jh7110_gmac_io_pad(int id)
  82. {
  83. u32 cap = BIT(0); /* 2.5V */
  84. switch (id) {
  85. case 0:
  86. /* Improved GMAC0 TX I/O PAD capability */
  87. clrsetbits_le32(AON_IOMUX_BASE + 0x78, 0x3, cap & 0x3);
  88. clrsetbits_le32(AON_IOMUX_BASE + 0x7c, 0x3, cap & 0x3);
  89. clrsetbits_le32(AON_IOMUX_BASE + 0x80, 0x3, cap & 0x3);
  90. clrsetbits_le32(AON_IOMUX_BASE + 0x84, 0x3, cap & 0x3);
  91. clrsetbits_le32(AON_IOMUX_BASE + 0x88, 0x3, cap & 0x3);
  92. break;
  93. case 1:
  94. /* Improved GMAC1 TX I/O PAD capability */
  95. clrsetbits_le32(SYS_IOMUX_BASE + 0x26c, 0x3, cap & 0x3);
  96. clrsetbits_le32(SYS_IOMUX_BASE + 0x270, 0x3, cap & 0x3);
  97. clrsetbits_le32(SYS_IOMUX_BASE + 0x274, 0x3, cap & 0x3);
  98. clrsetbits_le32(SYS_IOMUX_BASE + 0x278, 0x3, cap & 0x3);
  99. clrsetbits_le32(SYS_IOMUX_BASE + 0x27c, 0x3, cap & 0x3);
  100. break;
  101. }
  102. }
  103. static void jh7110_gmac_init(int id, u32 chip)
  104. {
  105. switch (chip) {
  106. case CHIP_B:
  107. jh7110_gmac_sel_tx_to_rgmii(id);
  108. jh7110_gmac_io_pad(id);
  109. break;
  110. case CHIP_A:
  111. default:
  112. break;
  113. }
  114. }
  115. static void jh7110_usb_init(bool usb2_enable)
  116. {
  117. if (usb2_enable) {
  118. /*usb 2.0 utmi phy init*/
  119. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  120. USB_MODE_STRAP_MASK,
  121. (2<<USB_MODE_STRAP_SHIFT) &
  122. USB_MODE_STRAP_MASK);/*2:host mode, 4:device mode*/
  123. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  124. USB_OTG_SUSPENDM_BYPS_MASK,
  125. BIT(USB_OTG_SUSPENDM_BYPS_SHIFT)
  126. & USB_OTG_SUSPENDM_BYPS_MASK);
  127. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  128. USB_OTG_SUSPENDM_MASK,
  129. BIT(USB_OTG_SUSPENDM_SHIFT) &
  130. USB_OTG_SUSPENDM_MASK);/*HOST = 1. DEVICE = 0;*/
  131. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  132. USB_PLL_EN_MASK,
  133. BIT(USB_PLL_EN_SHIFT) & USB_PLL_EN_MASK);
  134. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  135. USB_REFCLK_MODE_MASK,
  136. BIT(USB_REFCLK_MODE_SHIFT) & USB_REFCLK_MODE_MASK);
  137. /* usb 2.0 phy mode,REPLACE USB3.0 PHY module = 1;else = 0*/
  138. clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24,
  139. PDRSTN_SPLIT_MASK,
  140. BIT(PDRSTN_SPLIT_SHIFT) &
  141. PDRSTN_SPLIT_MASK);
  142. } else {
  143. /*usb 3.0 pipe phy config*/
  144. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_196,
  145. PCIE_CKREF_SRC_MASK,
  146. (0<<PCIE_CKREF_SRC_SHIFT) & PCIE_CKREF_SRC_MASK);
  147. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_196,
  148. PCIE_CLK_SEL_MASK,
  149. (0<<PCIE_CLK_SEL_SHIFT) & PCIE_CLK_SEL_MASK);
  150. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_328,
  151. PCIE_PHY_MODE_MASK,
  152. BIT(PCIE_PHY_MODE_SHIFT) & PCIE_PHY_MODE_MASK);
  153. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_500,
  154. PCIE_USB3_BUS_WIDTH_MASK,
  155. (0 << PCIE_USB3_BUS_WIDTH_SHIFT) &
  156. PCIE_USB3_BUS_WIDTH_MASK);
  157. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_500,
  158. PCIE_USB3_RATE_MASK,
  159. (0 << PCIE_USB3_RATE_SHIFT) & PCIE_USB3_RATE_MASK);
  160. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_500,
  161. PCIE_USB3_RX_STANDBY_MASK,
  162. (0 << PCIE_USB3_RX_STANDBY_SHIFT)
  163. & PCIE_USB3_RX_STANDBY_MASK);
  164. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_500,
  165. PCIE_USB3_PHY_ENABLE_MASK,
  166. BIT(PCIE_USB3_PHY_ENABLE_SHIFT)
  167. & PCIE_USB3_PHY_ENABLE_MASK);
  168. /* usb 3.0 phy mode,REPLACE USB3.0 PHY module = 1;else = 0*/
  169. clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24,
  170. PDRSTN_SPLIT_MASK,
  171. (0 << PDRSTN_SPLIT_SHIFT) & PDRSTN_SPLIT_MASK);
  172. }
  173. }
  174. static u32 get_chip_type(void)
  175. {
  176. u32 value;
  177. value = in_le32(AON_IOMUX_BASE + AON_GPIO_DIN_REG);
  178. value = (value & BIT(3)) >> 3;
  179. switch (value) {
  180. case CHIP_B:
  181. env_set("chip_vision", "B");
  182. break;
  183. case CHIP_A:
  184. default:
  185. env_set("chip_vision", "A");
  186. break;
  187. }
  188. return value;
  189. }
  190. #if CONFIG_IS_ENABLED(STARFIVE_OTP)
  191. static void get_cpu_voltage_type(struct udevice *dev)
  192. {
  193. int ret;
  194. u32 buf = CPU_VOL_1040;
  195. ret = misc_read(dev, CPU_VOL_BINNING_OFFSET, &buf, sizeof(buf));
  196. if (ret != sizeof(buf))
  197. printf("%s: error reading CPU vol from OTP\n", __func__);
  198. else {
  199. switch ((buf & CPU_VOL_MASK)) {
  200. case CPU_VOL_1120:
  201. env_set("cpu_max_vol", "1120000");
  202. break;
  203. case CPU_VOL_1100:
  204. env_set("cpu_max_vol", "1100000");
  205. break;
  206. case CPU_VOL_1080:
  207. env_set("cpu_max_vol", "1080000");
  208. break;
  209. case CPU_VOL_1060:
  210. env_set("cpu_max_vol", "1060000");
  211. break;
  212. case CPU_VOL_1020:
  213. env_set("cpu_max_vol", "1020000");
  214. break;
  215. default:
  216. env_set("cpu_max_vol", "1040000");
  217. break;
  218. }
  219. }
  220. }
  221. #endif
  222. int board_init(void)
  223. {
  224. enable_caches();
  225. jh7110_timer_init();
  226. jh7110_usb_init(true);
  227. return 0;
  228. }
  229. #ifdef CONFIG_MISC_INIT_R
  230. int misc_init_r(void)
  231. {
  232. char mac0[6] = {0x66, 0x34, 0xb0, 0x6c, 0xde, 0xad};
  233. char mac1[6] = {0x66, 0x34, 0xb0, 0x7c, 0xae, 0x5d};
  234. u32 chip;
  235. #if CONFIG_IS_ENABLED(STARFIVE_OTP)
  236. struct udevice *dev;
  237. char buf[16];
  238. int ret;
  239. #define MACADDR_OFFSET 0x8
  240. ret = uclass_get_device_by_driver(UCLASS_MISC,
  241. DM_DRIVER_GET(starfive_otp), &dev);
  242. if (ret) {
  243. debug("%s: could not find otp device\n", __func__);
  244. goto err;
  245. }
  246. ret = misc_read(dev, MACADDR_OFFSET, buf, sizeof(buf));
  247. if (ret != sizeof(buf))
  248. printf("%s: error reading mac from OTP\n", __func__);
  249. else
  250. if (buf[0] != 0xff) {
  251. memcpy(mac0, buf, 6);
  252. memcpy(mac1, &buf[8], 6);
  253. }
  254. err:
  255. #endif
  256. eth_env_set_enetaddr("eth0addr", mac0);
  257. eth_env_set_enetaddr("eth1addr", mac1);
  258. chip = get_chip_type();
  259. #if CONFIG_IS_ENABLED(STARFIVE_OTP)
  260. get_cpu_voltage_type(dev);
  261. #endif
  262. jh7110_gmac_init(0, chip);
  263. jh7110_gmac_init(1, chip);
  264. return 0;
  265. }
  266. #endif
  267. int board_late_init(void)
  268. {
  269. struct udevice *dev;
  270. int ret;
  271. ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
  272. if (ret)
  273. return ret;
  274. ret = video_bmp_display(dev, (ulong)&bmp_logo_bitmap[0], BMP_ALIGN_CENTER, BMP_ALIGN_CENTER, true);
  275. if (ret)
  276. goto err;
  277. err:
  278. return 0;
  279. }