spl.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
  4. * Author: yanhong <yanhong.wang@starfivetech.com>
  5. *
  6. */
  7. #include <common.h>
  8. #include <init.h>
  9. #include <asm/arch/spl.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/gpio.h>
  12. #include <asm/arch/jh7110-regs.h>
  13. #include <asm/arch/clk.h>
  14. #include <image.h>
  15. #include <log.h>
  16. #include <spl.h>
  17. #define MODE_SELECT_REG 0x1702002c
  18. int spl_board_init_f(void)
  19. {
  20. int ret;
  21. ret = spl_soc_init();
  22. if (ret) {
  23. debug("JH7110 SPL init failed: %d\n", ret);
  24. return ret;
  25. }
  26. return 0;
  27. }
  28. u32 spl_boot_device(void)
  29. {
  30. int boot_mode = 0;
  31. boot_mode = readl((const volatile void *)MODE_SELECT_REG) & 0x3;
  32. switch (boot_mode) {
  33. case 0:
  34. return BOOT_DEVICE_SPI;
  35. case 1:
  36. return BOOT_DEVICE_MMC2;
  37. case 2:
  38. return BOOT_DEVICE_MMC1;
  39. case 3:
  40. return BOOT_DEVICE_UART;
  41. default:
  42. debug("Unsupported boot device 0x%x.\n",
  43. boot_mode);
  44. return BOOT_DEVICE_NONE;
  45. }
  46. }
  47. struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
  48. {
  49. return (struct image_header *)(STARFIVE_SPL_BOOT_LOAD_ADDR);
  50. }
  51. void board_init_f(ulong dummy)
  52. {
  53. int ret;
  54. /* Set pll0 cpufreq to 1000M */
  55. starfive_jh7110_pll_set_rate(PLL0, 1000000000);
  56. /*change pll2 to 1188MHz*/
  57. starfive_jh7110_pll_set_rate(PLL2, 1188000000);
  58. /*DDR control depend clk init*/
  59. clrsetbits_le32(SYS_CRG_BASE, CLK_CPU_ROOT_SW_MASK,
  60. BIT(CLK_CPU_ROOT_SW_SHIFT) & CLK_CPU_ROOT_SW_MASK);
  61. clrsetbits_le32(SYS_CRG_BASE + CLK_BUS_ROOT_OFFSET,
  62. CLK_BUS_ROOT_SW_MASK,
  63. BIT(CLK_BUS_ROOT_SW_SHIFT) & CLK_BUS_ROOT_SW_MASK);
  64. /*Set clk_perh_root clk default mux sel to pll2*/
  65. clrsetbits_le32(SYS_CRG_BASE + CLK_PERH_ROOT_OFFSET,
  66. CLK_PERH_ROOT_MASK,
  67. BIT(CLK_PERH_ROOT_SHIFT) & CLK_PERH_ROOT_MASK);
  68. clrsetbits_le32(SYS_CRG_BASE + CLK_NOC_BUS_STG_AXI_OFFSET,
  69. CLK_NOC_BUS_STG_AXI_EN_MASK,
  70. BIT(CLK_NOC_BUS_STG_AXI_EN_SHIFT)
  71. & CLK_NOC_BUS_STG_AXI_EN_MASK);
  72. clrsetbits_le32(AON_CRG_BASE + CLK_AON_APB_FUNC_OFFSET,
  73. CLK_AON_APB_FUNC_SW_MASK,
  74. BIT(CLK_AON_APB_FUNC_SW_SHIFT) & CLK_AON_APB_FUNC_SW_MASK);
  75. /* switch qspi clk to pll0 */
  76. clrsetbits_le32(SYS_CRG_BASE + CLK_QSPI_REF_OFFSET,
  77. CLK_QSPI_REF_SW_MASK,
  78. BIT(CLK_QSPI_REF_SW_SHIFT) & CLK_QSPI_REF_SW_MASK);
  79. /*set GPIO to 1.8v*/
  80. setbits_le32(SYS_SYSCON_BASE + 0xC, 0xf);
  81. /* reset emmc */
  82. SYS_IOMUX_DOEN(22, LOW);
  83. SYS_IOMUX_DOUT(22, 19);
  84. /* reset sdio */
  85. SYS_IOMUX_DOEN(24, LOW);
  86. SYS_IOMUX_DOUT(24, 66);
  87. ret = spl_early_init();
  88. if (ret)
  89. panic("spl_early_init() failed: %d\n", ret);
  90. arch_cpu_init_dm();
  91. preloader_console_init();
  92. ret = spl_board_init_f();
  93. if (ret) {
  94. debug("spl_board_init_f init failed: %d\n", ret);
  95. return;
  96. }
  97. }
  98. #ifdef CONFIG_SPL_LOAD_FIT
  99. int board_fit_config_name_match(const char *name)
  100. {
  101. /* boot using first FIT config */
  102. return 0;
  103. }
  104. #endif