jh7110-regs.h 3.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
  4. * Author: yanhong <yanhong.wang@starfivetech.com>
  5. *
  6. */
  7. #ifndef __STARFIVE_JH7110_REGS_H
  8. #define __STARFIVE_JH7110_REGS_H
  9. /*system control register*/
  10. #define STG_SYSCON_BASE 0x10240000
  11. #define SYS_SYSCON_BASE 0x13030000
  12. #define SYS_IOMUX_BASE 0x13040000
  13. #define AON_IOMUX_BASE 0x17020000
  14. #define AON_SYSCON_BASE 0x17010000
  15. #define SYS_CRG_BASE 0x13020000
  16. #define AON_CRG_BASE 0x17000000
  17. #define AON_IOMUX_BASE 0x17020000
  18. #define STG_CRG_BASE 0x10230000
  19. #define CLK_ENABLE_MASK 0x80000000U
  20. #define SYS_CRG_RESET_ASSERT3_SHIFT 0X304U
  21. #define SYS_CRG_RESET_STATUS3_SHIFT 0X314U
  22. /*gmac cfg*/
  23. #define AON_SYSCFG_12 0xCU
  24. #define SYS_SYSCON_144 0x90U
  25. #define GMAC5_0_SEL_I_SHIFT 0x12U
  26. #define GMAC5_0_SEL_I_MASK 0x1C0000U
  27. #define GMAC5_0_CLK_TX_SHIFT 0x14
  28. #define GMAC5_0_CLK_RX_SHIFT 0x1C
  29. #define GMAC5_0_CLK_TX_BIT 0x18
  30. #define GMAC5_0_CLK_TX_MASK 0x1000000U
  31. #define GMAC5_1_SEL_I_SHIFT 0x2U
  32. #define GMAC5_1_SEL_I_MASK 0x1CU
  33. #define GMAC5_1_CLK_TX_SHIFT 0x1A4
  34. #define GMAC5_1_CLK_RX_SHIFT 0x19C
  35. #define GMAC5_1_CLK_TX_BIT 0x18
  36. #define GMAC5_1_CLK_TX_MASK 0x1000000U
  37. /*usb cfg*/
  38. #define STG_SYSCON_4 0x4U
  39. #define STG_SYSCON_196 0xC4U
  40. #define STG_SYSCON_328 0x148U
  41. #define STG_SYSCON_500 0x1F4U
  42. #define SYS_SYSCON_24 0x18U
  43. #define SYS_SYSCON_28 0x1CU
  44. #define SYS_SYSCON_32 0x20U
  45. #define SYS_SYSCON_36 0x24U
  46. #define SYS_IOMUX_32 0x80U
  47. #define USB_MODE_STRAP_SHIFT 0x10U
  48. #define USB_MODE_STRAP_MASK 0x70000U
  49. #define USB_OTG_SUSPENDM_BYPS_SHIFT 0x14U
  50. #define USB_OTG_SUSPENDM_BYPS_MASK 0x100000U
  51. #define USB_OTG_SUSPENDM_SHIFT 0x13U
  52. #define USB_OTG_SUSPENDM_MASK 0x80000U
  53. #define USB_PLL_EN_SHIFT 0x16U
  54. #define USB_PLL_EN_MASK 0x400000U
  55. #define USB_REFCLK_MODE_SHIFT 0x17U
  56. #define USB_REFCLK_MODE_MASK 0x800000U
  57. #define PDRSTN_SPLIT_SHIFT 0x11U
  58. #define PDRSTN_SPLIT_MASK 0x20000U
  59. #define IOMUX_USB_SHIFT 0x10U
  60. #define IOMUX_USB_MASK 0x7F0000U
  61. #define PCIE_CKREF_SRC_SHIFT 0x12U
  62. #define PCIE_CKREF_SRC_MASK 0xC0000U
  63. #define PCIE_CLK_SEL_SHIFT 0x14U
  64. #define PCIE_CLK_SEL_MASK 0x300000U
  65. #define PCIE_PHY_MODE_SHIFT 0x14U
  66. #define PCIE_PHY_MODE_MASK 0x300000U
  67. #define PCIE_USB3_BUS_WIDTH_SHIFT 0x2U
  68. #define PCIE_USB3_BUS_WIDTH_MASK 0xCU
  69. #define PCIE_USB3_RATE_SHIFT 0x5U
  70. #define PCIE_USB3_RATE_MASK 0x60U
  71. #define PCIE_USB3_RX_STANDBY_SHIFT 0x7U
  72. #define PCIE_USB3_RX_STANDBY_MASK 0x80U
  73. #define PCIE_USB3_PHY_ENABLE_SHIFT 0x4U
  74. #define PCIE_USB3_PHY_ENABLE_MASK 0x10U
  75. #define AON_GPIO_DIN_REG 0x2c
  76. /*timer cfg*/
  77. #define TIMER_CLK_APB_SHIFT 0x1F0U
  78. #define TIMER_CLK_TIMER0_SHIFT 0x1F4U
  79. #define TIMER_CLK_TIMER1_SHIFT 0x1F8U
  80. #define TIMER_CLK_TIMER2_SHIFT 0x1FCU
  81. #define TIMER_CLK_TIMER3_SHIFT 0x200U
  82. #define TIMER_RSTN_APB_SHIFT 21
  83. #define TIMER_RSTN_TIMER0_SHIFT 22
  84. #define TIMER_RSTN_TIMER1_SHIFT 23
  85. #define TIMER_RSTN_TIMER2_SHIFT 24
  86. #define TIMER_RSTN_TIMER3_SHIFT 25
  87. #define CLK_CPU_ROOT_OFFSET 0x0
  88. #define CLK_CPU_ROOT_SW_SHIFT 24
  89. #define CLK_CPU_ROOT_SW_MASK 0x1000000U
  90. #define CLK_PERH_ROOT_OFFSET 0x10
  91. #define CLK_PERH_ROOT_SHIFT 24
  92. #define CLK_PERH_ROOT_MASK 0x1000000U
  93. #define CLK_BUS_ROOT_OFFSET 0x14
  94. #define CLK_BUS_ROOT_SW_SHIFT 24
  95. #define CLK_BUS_ROOT_SW_MASK 0x1000000U
  96. #define CLK_NOC_BUS_STG_AXI_OFFSET 0x180
  97. #define CLK_NOC_BUS_STG_AXI_EN_SHIFT 31
  98. #define CLK_NOC_BUS_STG_AXI_EN_MASK 0x80000000U
  99. #define CLK_AON_APB_FUNC_OFFSET 0x4
  100. #define CLK_AON_APB_FUNC_SW_SHIFT 24
  101. #define CLK_AON_APB_FUNC_SW_MASK 0x1000000U
  102. #define CLK_QSPI_REF_OFFSET 0x168
  103. #define CLK_QSPI_REF_SW_SHIFT 24
  104. #define CLK_QSPI_REF_SW_MASK 0x1000000U
  105. #endif /* __STARFIVE_JH7110_REGS_H */