clk.h 695 B

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
  4. * Author: yanhong <yanhong.wang@starfivetech.com>
  5. *
  6. */
  7. #ifndef __CLK_STARFIVE_H
  8. #define __CLK_STARFIVE_H
  9. enum starfive_pll_type {
  10. PLL0 = 0,
  11. PLL1,
  12. PLL2,
  13. PLL_MAX = PLL2
  14. };
  15. struct starfive_pll_freq {
  16. u64 freq;
  17. u32 prediv;
  18. u32 fbdiv;
  19. u32 frac;
  20. u32 postdiv1;
  21. u32 dacpd; /* Both daxpd and dsmpd set 1 while integer multiple mode */
  22. u32 dsmpd; /* Both daxpd and dsmpd set 0 while fraction multiple mode */
  23. };
  24. u64 starfive_jh7110_pll_get_rate(enum starfive_pll_type pll,
  25. struct starfive_pll_freq *conf);
  26. int starfive_jh7110_pll_set_rate(enum starfive_pll_type pll, u64 rate);
  27. #endif