spl.c 1.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
  4. * Author: yanhong <yanhong.wang@starfivetech.com>
  5. *
  6. */
  7. #include <dm.h>
  8. #include <log.h>
  9. #include <asm/csr.h>
  10. #include <init.h>
  11. #define CSR_U74_FEATURE_DISABLE 0x7c1
  12. int spl_soc_init(void)
  13. {
  14. int ret;
  15. struct udevice *dev;
  16. /* I2C init */
  17. ret = uclass_get_device(UCLASS_I2C, 0, &dev);
  18. if (ret) {
  19. debug("I2C init failed: %d\n", ret);
  20. return ret;
  21. }
  22. /*read memory size info from eeprom and
  23. *init gd->ram_size variable
  24. */
  25. dram_init();
  26. /* DDR init */
  27. ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  28. if (ret) {
  29. debug("DRAM init failed: %d\n", ret);
  30. return ret;
  31. }
  32. /*flash init*/
  33. ret = uclass_get_device(UCLASS_SPI_FLASH, 0, &dev);
  34. if (ret) {
  35. debug("SPI init failed: %d\n", ret);
  36. return ret;
  37. }
  38. return 0;
  39. }
  40. void harts_early_init(void)
  41. {
  42. /*
  43. * Feature Disable CSR
  44. *
  45. * Clear feature disable CSR to '0' to turn on all features for
  46. * each core. This operation must be in M-mode.
  47. */
  48. if (CONFIG_IS_ENABLED(RISCV_MMODE))
  49. csr_write(CSR_U74_FEATURE_DISABLE, 0);
  50. #ifdef CONFIG_SPL_BUILD
  51. /*clear L2 LIM memory
  52. * set __bss_end to 0x81e0000 region to zero
  53. */
  54. __asm__ __volatile__ (
  55. "la t1, __bss_end\n"
  56. "li t2, 0x81e0000\n"
  57. "spl_clear_l2im:\n"
  58. "addi t1, t1, 8\n"
  59. "sd zero, 0(t1)\n"
  60. "blt t1, t2, spl_clear_l2im\n");
  61. #endif
  62. }