mediatek,mt7620-rfb.dts 1.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2020 MediaTek Inc.
  4. *
  5. * Author: Weijie Gao <weijie.gao@mediatek.com>
  6. */
  7. /dts-v1/;
  8. #include <dt-bindings/gpio/gpio.h>
  9. #include "mt7620.dtsi"
  10. / {
  11. compatible = "mediatek,mt7620-rfb", "mediatek,mt7620-soc";
  12. model = "MediaTek MT7620 RFB (WS2120)";
  13. aliases {
  14. serial0 = &uartlite;
  15. spi0 = &spi0;
  16. };
  17. chosen {
  18. stdout-path = &uartlite;
  19. };
  20. };
  21. &uartlite {
  22. status = "okay";
  23. };
  24. &pinctrl {
  25. state_default: pin_state {
  26. pleds {
  27. groups = "ephy led", "wled";
  28. function = "led";
  29. };
  30. gpios {
  31. groups = "uartf";
  32. function = "gpio";
  33. };
  34. };
  35. gsw_pins: gsw_pins {
  36. mdio {
  37. groups = "mdio";
  38. function = "mdio";
  39. };
  40. rgmii1 {
  41. groups = "rgmii1";
  42. function = "rgmii1";
  43. };
  44. rgmii2 {
  45. groups = "rgmii2";
  46. function = "rgmii2";
  47. };
  48. };
  49. };
  50. &spi0 {
  51. status = "okay";
  52. num-cs = <2>;
  53. spi-flash@0 {
  54. #address-cells = <1>;
  55. #size-cells = <1>;
  56. compatible = "jedec,spi-nor";
  57. spi-max-frequency = <25000000>;
  58. reg = <0>;
  59. };
  60. };
  61. &eth {
  62. status = "okay";
  63. pinctrl-names = "default";
  64. pinctrl-0 = <&gsw_pins>;
  65. port4 {
  66. phy-mode = "rgmii";
  67. phy-addr = <4>;
  68. };
  69. port5 {
  70. phy-mode = "rgmii";
  71. phy-addr = <5>;
  72. };
  73. };
  74. &mmc {
  75. bus-width = <4>;
  76. cap-sd-highspeed;
  77. status = "okay";
  78. };