cache.h 784 B

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  1. /*
  2. * Copyright (c) 2011 The Chromium OS Authors.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #ifndef __AVR32_CACHE_H__
  7. #define __AVR32_CACHE_H__
  8. /*
  9. * Since the AVR32 architecture has a queryable cacheline size with a maximum
  10. * value of 256 we set the DMA buffer alignemnt requirement to this maximum
  11. * value. The board config can override this if it knows that the cacheline
  12. * size is a smaller value. AVR32 boards use the CONFIG_SYS_DCACHE_LINESZ
  13. * macro to specify cache line size, so if it is set we use it instead.
  14. */
  15. #ifdef CONFIG_SYS_CACHELINE_SIZE
  16. #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
  17. #elif defined(CONFIG_SYS_DCACHE_LINESZ)
  18. #define ARCH_DMA_MINALIGN CONFIG_SYS_DCACHE_LINESZ
  19. #else
  20. #define ARCH_DMA_MINALIGN 256
  21. #endif
  22. #endif /* __AVR32_CACHE_H__ */