hsdramc.c 2.6 KB

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  1. /*
  2. * Copyright (C) 2005-2006 Atmel Corporation
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #include <asm/sdram.h>
  9. #include <asm/arch/clk.h>
  10. #include <asm/arch/hardware.h>
  11. #include "hsdramc1.h"
  12. unsigned long sdram_init(void *sdram_base, const struct sdram_config *config)
  13. {
  14. unsigned long sdram_size;
  15. uint32_t cfgreg;
  16. unsigned int i;
  17. cfgreg = (HSDRAMC1_BF(NC, config->col_bits - 8)
  18. | HSDRAMC1_BF(NR, config->row_bits - 11)
  19. | HSDRAMC1_BF(NB, config->bank_bits - 1)
  20. | HSDRAMC1_BF(CAS, config->cas)
  21. | HSDRAMC1_BF(TWR, config->twr)
  22. | HSDRAMC1_BF(TRC, config->trc)
  23. | HSDRAMC1_BF(TRP, config->trp)
  24. | HSDRAMC1_BF(TRCD, config->trcd)
  25. | HSDRAMC1_BF(TRAS, config->tras)
  26. | HSDRAMC1_BF(TXSR, config->txsr));
  27. if (config->data_bits == SDRAM_DATA_16BIT)
  28. cfgreg |= HSDRAMC1_BIT(DBW);
  29. hsdramc1_writel(CR, cfgreg);
  30. /* Send a NOP to turn on the clock (necessary on some chips) */
  31. hsdramc1_writel(MR, HSDRAMC1_MODE_NOP);
  32. hsdramc1_readl(MR);
  33. writel(0, sdram_base);
  34. /*
  35. * Initialization sequence for SDRAM, from the data sheet:
  36. *
  37. * 1. A minimum pause of 200 us is provided to precede any
  38. * signal toggle.
  39. */
  40. udelay(200);
  41. /*
  42. * 2. A Precharge All command is issued to the SDRAM
  43. */
  44. hsdramc1_writel(MR, HSDRAMC1_MODE_BANKS_PRECHARGE);
  45. hsdramc1_readl(MR);
  46. writel(0, sdram_base);
  47. /*
  48. * 3. Eight auto-refresh (CBR) cycles are provided
  49. */
  50. hsdramc1_writel(MR, HSDRAMC1_MODE_AUTO_REFRESH);
  51. hsdramc1_readl(MR);
  52. for (i = 0; i < 8; i++)
  53. writel(0, sdram_base);
  54. /*
  55. * 4. A mode register set (MRS) cycle is issued to program
  56. * SDRAM parameters, in particular CAS latency and burst
  57. * length.
  58. *
  59. * The address will be chosen by the SDRAMC automatically; we
  60. * just have to make sure BA[1:0] are set to 0.
  61. */
  62. hsdramc1_writel(MR, HSDRAMC1_MODE_LOAD_MODE);
  63. hsdramc1_readl(MR);
  64. writel(0, sdram_base);
  65. /*
  66. * 5. The application must go into Normal Mode, setting Mode
  67. * to 0 in the Mode Register and performing a write access
  68. * at any location in the SDRAM.
  69. */
  70. hsdramc1_writel(MR, HSDRAMC1_MODE_NORMAL);
  71. hsdramc1_readl(MR);
  72. writel(0, sdram_base);
  73. /*
  74. * 6. Write refresh rate into SDRAMC refresh timer count
  75. * register (refresh rate = timing between refresh cycles).
  76. */
  77. hsdramc1_writel(TR, config->refresh_period);
  78. if (config->data_bits == SDRAM_DATA_16BIT)
  79. sdram_size = 1 << (config->row_bits + config->col_bits
  80. + config->bank_bits + 1);
  81. else
  82. sdram_size = 1 << (config->row_bits + config->col_bits
  83. + config->bank_bits + 2);
  84. return sdram_size;
  85. }