sm.h 5.2 KB

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  1. /*
  2. * Register definitions for System Manager
  3. */
  4. #ifndef __CPU_AT32AP_SM_H__
  5. #define __CPU_AT32AP_SM_H__
  6. /* SM register offsets */
  7. #define SM_PM_MCCTRL 0x0000
  8. #define SM_PM_CKSEL 0x0004
  9. #define SM_PM_CPU_MASK 0x0008
  10. #define SM_PM_HSB_MASK 0x000c
  11. #define SM_PM_PBA_MASK 0x0010
  12. #define SM_PM_PBB_MASK 0x0014
  13. #define SM_PM_PLL0 0x0020
  14. #define SM_PM_PLL1 0x0024
  15. #define SM_PM_VCTRL 0x0030
  16. #define SM_PM_VMREF 0x0034
  17. #define SM_PM_VMV 0x0038
  18. #define SM_PM_IER 0x0040
  19. #define SM_PM_IDR 0x0044
  20. #define SM_PM_IMR 0x0048
  21. #define SM_PM_ISR 0x004c
  22. #define SM_PM_ICR 0x0050
  23. #define SM_PM_GCCTRL(x) (0x0060 + 4 * x)
  24. #define SM_RTC_CTRL 0x0080
  25. #define SM_RTC_VAL 0x0084
  26. #define SM_RTC_TOP 0x0088
  27. #define SM_RTC_IER 0x0090
  28. #define SM_RTC_IDR 0x0094
  29. #define SM_RTC_IMR 0x0098
  30. #define SM_RTC_ISR 0x009c
  31. #define SM_RTC_ICR 0x00a0
  32. #define SM_WDT_CTRL 0x00b0
  33. #define SM_WDT_CLR 0x00b4
  34. #define SM_WDT_EXT 0x00b8
  35. #define SM_RC_RCAUSE 0x00c0
  36. #define SM_EIM_IER 0x0100
  37. #define SM_EIM_IDR 0x0104
  38. #define SM_EIM_IMR 0x0108
  39. #define SM_EIM_ISR 0x010c
  40. #define SM_EIM_ICR 0x0110
  41. #define SM_EIM_MODE 0x0114
  42. #define SM_EIM_EDGE 0x0118
  43. #define SM_EIM_LEVEL 0x011c
  44. #define SM_EIM_TEST 0x0120
  45. #define SM_EIM_NMIC 0x0124
  46. /* Bitfields in PM_CKSEL */
  47. #define SM_CPUSEL_OFFSET 0
  48. #define SM_CPUSEL_SIZE 3
  49. #define SM_CPUDIV_OFFSET 7
  50. #define SM_CPUDIV_SIZE 1
  51. #define SM_HSBSEL_OFFSET 8
  52. #define SM_HSBSEL_SIZE 3
  53. #define SM_HSBDIV_OFFSET 15
  54. #define SM_HSBDIV_SIZE 1
  55. #define SM_PBASEL_OFFSET 16
  56. #define SM_PBASEL_SIZE 3
  57. #define SM_PBADIV_OFFSET 23
  58. #define SM_PBADIV_SIZE 1
  59. #define SM_PBBSEL_OFFSET 24
  60. #define SM_PBBSEL_SIZE 3
  61. #define SM_PBBDIV_OFFSET 31
  62. #define SM_PBBDIV_SIZE 1
  63. /* Bitfields in PM_PLL0 */
  64. #define SM_PLLEN_OFFSET 0
  65. #define SM_PLLEN_SIZE 1
  66. #define SM_PLLOSC_OFFSET 1
  67. #define SM_PLLOSC_SIZE 1
  68. #define SM_PLLOPT_OFFSET 2
  69. #define SM_PLLOPT_SIZE 3
  70. #define SM_PLLDIV_OFFSET 8
  71. #define SM_PLLDIV_SIZE 8
  72. #define SM_PLLMUL_OFFSET 16
  73. #define SM_PLLMUL_SIZE 8
  74. #define SM_PLLCOUNT_OFFSET 24
  75. #define SM_PLLCOUNT_SIZE 6
  76. #define SM_PLLTEST_OFFSET 31
  77. #define SM_PLLTEST_SIZE 1
  78. /* Bitfields in PM_VCTRL */
  79. #define SM_VAUTO_OFFSET 0
  80. #define SM_VAUTO_SIZE 1
  81. #define SM_PM_VCTRL_VAL_OFFSET 8
  82. #define SM_PM_VCTRL_VAL_SIZE 7
  83. /* Bitfields in PM_VMREF */
  84. #define SM_REFSEL_OFFSET 0
  85. #define SM_REFSEL_SIZE 4
  86. /* Bitfields in PM_VMV */
  87. #define SM_PM_VMV_VAL_OFFSET 0
  88. #define SM_PM_VMV_VAL_SIZE 8
  89. /* Bitfields in PM_ICR */
  90. #define SM_LOCK0_OFFSET 0
  91. #define SM_LOCK0_SIZE 1
  92. #define SM_LOCK1_OFFSET 1
  93. #define SM_LOCK1_SIZE 1
  94. #define SM_WAKE_OFFSET 2
  95. #define SM_WAKE_SIZE 1
  96. #define SM_VOK_OFFSET 3
  97. #define SM_VOK_SIZE 1
  98. #define SM_VMRDY_OFFSET 4
  99. #define SM_VMRDY_SIZE 1
  100. #define SM_CKRDY_OFFSET 5
  101. #define SM_CKRDY_SIZE 1
  102. /* Bitfields in PM_GCCTRL */
  103. #define SM_OSCSEL_OFFSET 0
  104. #define SM_OSCSEL_SIZE 1
  105. #define SM_PLLSEL_OFFSET 1
  106. #define SM_PLLSEL_SIZE 1
  107. #define SM_CEN_OFFSET 2
  108. #define SM_CEN_SIZE 1
  109. #define SM_CPC_OFFSET 3
  110. #define SM_CPC_SIZE 1
  111. #define SM_DIVEN_OFFSET 4
  112. #define SM_DIVEN_SIZE 1
  113. #define SM_DIV_OFFSET 8
  114. #define SM_DIV_SIZE 8
  115. /* Bitfields in RTC_CTRL */
  116. #define SM_PCLR_OFFSET 1
  117. #define SM_PCLR_SIZE 1
  118. #define SM_TOPEN_OFFSET 2
  119. #define SM_TOPEN_SIZE 1
  120. #define SM_CLKEN_OFFSET 3
  121. #define SM_CLKEN_SIZE 1
  122. #define SM_PSEL_OFFSET 8
  123. #define SM_PSEL_SIZE 16
  124. /* Bitfields in RTC_VAL */
  125. #define SM_RTC_VAL_VAL_OFFSET 0
  126. #define SM_RTC_VAL_VAL_SIZE 31
  127. /* Bitfields in RTC_TOP */
  128. #define SM_RTC_TOP_VAL_OFFSET 0
  129. #define SM_RTC_TOP_VAL_SIZE 32
  130. /* Bitfields in RTC_ICR */
  131. #define SM_TOPI_OFFSET 0
  132. #define SM_TOPI_SIZE 1
  133. /* Bitfields in WDT_CTRL */
  134. #define SM_KEY_OFFSET 24
  135. #define SM_KEY_SIZE 8
  136. /* Bitfields in RC_RCAUSE */
  137. #define SM_POR_OFFSET 0
  138. #define SM_POR_SIZE 1
  139. #define SM_BOD_OFFSET 1
  140. #define SM_BOD_SIZE 1
  141. #define SM_EXT_OFFSET 2
  142. #define SM_EXT_SIZE 1
  143. #define SM_WDT_OFFSET 3
  144. #define SM_WDT_SIZE 1
  145. #define SM_NTAE_OFFSET 4
  146. #define SM_NTAE_SIZE 1
  147. #define SM_SERP_OFFSET 5
  148. #define SM_SERP_SIZE 1
  149. /* Bitfields in EIM_EDGE */
  150. #define SM_INT0_OFFSET 0
  151. #define SM_INT0_SIZE 1
  152. #define SM_INT1_OFFSET 1
  153. #define SM_INT1_SIZE 1
  154. #define SM_INT2_OFFSET 2
  155. #define SM_INT2_SIZE 1
  156. #define SM_INT3_OFFSET 3
  157. #define SM_INT3_SIZE 1
  158. /* Bitfields in EIM_LEVEL */
  159. /* Bitfields in EIM_TEST */
  160. #define SM_TESTEN_OFFSET 31
  161. #define SM_TESTEN_SIZE 1
  162. /* Bitfields in EIM_NMIC */
  163. #define SM_EN_OFFSET 0
  164. #define SM_EN_SIZE 1
  165. /* Bit manipulation macros */
  166. #define SM_BIT(name) \
  167. (1 << SM_##name##_OFFSET)
  168. #define SM_BF(name,value) \
  169. (((value) & ((1 << SM_##name##_SIZE) - 1)) \
  170. << SM_##name##_OFFSET)
  171. #define SM_BFEXT(name,value) \
  172. (((value) >> SM_##name##_OFFSET) \
  173. & ((1 << SM_##name##_SIZE) - 1))
  174. #define SM_BFINS(name,value,old) \
  175. (((old) & ~(((1 << SM_##name##_SIZE) - 1) \
  176. << SM_##name##_OFFSET)) \
  177. | SM_BF(name,value))
  178. /* Register access macros */
  179. #define sm_readl(reg) \
  180. readl((void *)ATMEL_BASE_SM + SM_##reg)
  181. #define sm_writel(reg,value) \
  182. writel((value), (void *)ATMEL_BASE_SM + SM_##reg)
  183. #endif /* __CPU_AT32AP_SM_H__ */