fsl_esdhc_imx.c 44 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
  4. * Copyright 2019, 2021 NXP
  5. * Andy Fleming
  6. * Yangbo Lu <yangbo.lu@nxp.com>
  7. *
  8. * Based vaguely on the pxa mmc code:
  9. * (C) Copyright 2003
  10. * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  11. */
  12. #include <config.h>
  13. #include <common.h>
  14. #include <command.h>
  15. #include <clk.h>
  16. #include <cpu_func.h>
  17. #include <errno.h>
  18. #include <hwconfig.h>
  19. #include <log.h>
  20. #include <mmc.h>
  21. #include <part.h>
  22. #include <asm/cache.h>
  23. #include <asm/global_data.h>
  24. #include <dm/device_compat.h>
  25. #include <linux/bitops.h>
  26. #include <linux/delay.h>
  27. #include <linux/err.h>
  28. #include <power/regulator.h>
  29. #include <malloc.h>
  30. #include <fsl_esdhc_imx.h>
  31. #include <fdt_support.h>
  32. #include <asm/io.h>
  33. #include <dm.h>
  34. #include <asm-generic/gpio.h>
  35. #include <dm/pinctrl.h>
  36. #include <dt-structs.h>
  37. #include <mapmem.h>
  38. #include <dm/ofnode.h>
  39. #include <linux/iopoll.h>
  40. #if !CONFIG_IS_ENABLED(BLK)
  41. #include "mmc_private.h"
  42. #endif
  43. #ifndef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
  44. #ifdef CONFIG_FSL_USDHC
  45. #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
  46. #endif
  47. #endif
  48. DECLARE_GLOBAL_DATA_PTR;
  49. #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
  50. IRQSTATEN_CINT | \
  51. IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
  52. IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
  53. IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
  54. IRQSTATEN_DINT)
  55. #define MAX_TUNING_LOOP 40
  56. #define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
  57. struct fsl_esdhc {
  58. uint dsaddr; /* SDMA system address register */
  59. uint blkattr; /* Block attributes register */
  60. uint cmdarg; /* Command argument register */
  61. uint xfertyp; /* Transfer type register */
  62. uint cmdrsp0; /* Command response 0 register */
  63. uint cmdrsp1; /* Command response 1 register */
  64. uint cmdrsp2; /* Command response 2 register */
  65. uint cmdrsp3; /* Command response 3 register */
  66. uint datport; /* Buffer data port register */
  67. uint prsstat; /* Present state register */
  68. uint proctl; /* Protocol control register */
  69. uint sysctl; /* System Control Register */
  70. uint irqstat; /* Interrupt status register */
  71. uint irqstaten; /* Interrupt status enable register */
  72. uint irqsigen; /* Interrupt signal enable register */
  73. uint autoc12err; /* Auto CMD error status register */
  74. uint hostcapblt; /* Host controller capabilities register */
  75. uint wml; /* Watermark level register */
  76. uint mixctrl; /* For USDHC */
  77. char reserved1[4]; /* reserved */
  78. uint fevt; /* Force event register */
  79. uint admaes; /* ADMA error status register */
  80. uint adsaddr; /* ADMA system address register */
  81. char reserved2[4];
  82. uint dllctrl;
  83. uint dllstat;
  84. uint clktunectrlstatus;
  85. char reserved3[4];
  86. uint strobe_dllctrl;
  87. uint strobe_dllstat;
  88. char reserved4[72];
  89. uint vendorspec;
  90. uint mmcboot;
  91. uint vendorspec2;
  92. uint tuning_ctrl; /* on i.MX6/7/8/RT */
  93. char reserved5[44];
  94. uint hostver; /* Host controller version register */
  95. char reserved6[4]; /* reserved */
  96. uint dmaerraddr; /* DMA error address register */
  97. char reserved7[4]; /* reserved */
  98. uint dmaerrattr; /* DMA error attribute register */
  99. char reserved8[4]; /* reserved */
  100. uint hostcapblt2; /* Host controller capabilities register 2 */
  101. char reserved9[8]; /* reserved */
  102. uint tcr; /* Tuning control register */
  103. char reserved10[28]; /* reserved */
  104. uint sddirctl; /* SD direction control register */
  105. char reserved11[712];/* reserved */
  106. uint scr; /* eSDHC control register */
  107. };
  108. struct fsl_esdhc_plat {
  109. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  110. /* Put this first since driver model will copy the data here */
  111. struct dtd_fsl_esdhc dtplat;
  112. #endif
  113. struct mmc_config cfg;
  114. struct mmc mmc;
  115. };
  116. struct esdhc_soc_data {
  117. u32 flags;
  118. };
  119. /**
  120. * struct fsl_esdhc_priv
  121. *
  122. * @esdhc_regs: registers of the sdhc controller
  123. * @sdhc_clk: Current clk of the sdhc controller
  124. * @bus_width: bus width, 1bit, 4bit or 8bit
  125. * @cfg: mmc config
  126. * @mmc: mmc
  127. * Following is used when Driver Model is enabled for MMC
  128. * @dev: pointer for the device
  129. * @non_removable: 0: removable; 1: non-removable
  130. * @broken_cd: 0: use GPIO for card detect; 1: Do not use GPIO for card detect
  131. * @wp_enable: 1: enable checking wp; 0: no check
  132. * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
  133. * @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
  134. * @caps: controller capabilities
  135. * @tuning_step: tuning step setting in tuning_ctrl register
  136. * @start_tuning_tap: the start point for tuning in tuning_ctrl register
  137. * @strobe_dll_delay_target: settings in strobe_dllctrl
  138. * @signal_voltage: indicating the current voltage
  139. * @signal_voltage_switch_extra_delay_ms: extra delay for IO voltage switch
  140. * @cd_gpio: gpio for card detection
  141. * @wp_gpio: gpio for write protection
  142. */
  143. struct fsl_esdhc_priv {
  144. struct fsl_esdhc *esdhc_regs;
  145. unsigned int sdhc_clk;
  146. struct clk per_clk;
  147. unsigned int clock;
  148. unsigned int mode;
  149. unsigned int bus_width;
  150. #if !CONFIG_IS_ENABLED(BLK)
  151. struct mmc *mmc;
  152. #endif
  153. struct udevice *dev;
  154. int non_removable;
  155. int broken_cd;
  156. int wp_enable;
  157. int vs18_enable;
  158. u32 flags;
  159. u32 caps;
  160. u32 tuning_step;
  161. u32 tuning_start_tap;
  162. u32 strobe_dll_delay_target;
  163. u32 signal_voltage;
  164. u32 signal_voltage_switch_extra_delay_ms;
  165. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  166. struct udevice *vqmmc_dev;
  167. struct udevice *vmmc_dev;
  168. #endif
  169. #if CONFIG_IS_ENABLED(DM_GPIO)
  170. struct gpio_desc cd_gpio;
  171. struct gpio_desc wp_gpio;
  172. #endif
  173. };
  174. /* Return the XFERTYP flags for a given command and data packet */
  175. static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
  176. {
  177. uint xfertyp = 0;
  178. if (data) {
  179. xfertyp |= XFERTYP_DPSEL;
  180. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  181. xfertyp |= XFERTYP_DMAEN;
  182. #endif
  183. if (data->blocks > 1) {
  184. xfertyp |= XFERTYP_MSBSEL;
  185. xfertyp |= XFERTYP_BCEN;
  186. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
  187. xfertyp |= XFERTYP_AC12EN;
  188. #endif
  189. }
  190. if (data->flags & MMC_DATA_READ)
  191. xfertyp |= XFERTYP_DTDSEL;
  192. }
  193. if (cmd->resp_type & MMC_RSP_CRC)
  194. xfertyp |= XFERTYP_CCCEN;
  195. if (cmd->resp_type & MMC_RSP_OPCODE)
  196. xfertyp |= XFERTYP_CICEN;
  197. if (cmd->resp_type & MMC_RSP_136)
  198. xfertyp |= XFERTYP_RSPTYP_136;
  199. else if (cmd->resp_type & MMC_RSP_BUSY)
  200. xfertyp |= XFERTYP_RSPTYP_48_BUSY;
  201. else if (cmd->resp_type & MMC_RSP_PRESENT)
  202. xfertyp |= XFERTYP_RSPTYP_48;
  203. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  204. xfertyp |= XFERTYP_CMDTYP_ABORT;
  205. return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
  206. }
  207. #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
  208. /*
  209. * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
  210. */
  211. static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
  212. struct mmc_data *data)
  213. {
  214. struct fsl_esdhc *regs = priv->esdhc_regs;
  215. uint blocks;
  216. char *buffer;
  217. uint databuf;
  218. uint size;
  219. uint irqstat;
  220. ulong start;
  221. if (data->flags & MMC_DATA_READ) {
  222. blocks = data->blocks;
  223. buffer = data->dest;
  224. while (blocks) {
  225. start = get_timer(0);
  226. size = data->blocksize;
  227. irqstat = esdhc_read32(&regs->irqstat);
  228. while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)) {
  229. if (get_timer(start) > PIO_TIMEOUT) {
  230. printf("\nData Read Failed in PIO Mode.");
  231. return;
  232. }
  233. }
  234. while (size && (!(irqstat & IRQSTAT_TC))) {
  235. udelay(100); /* Wait before last byte transfer complete */
  236. irqstat = esdhc_read32(&regs->irqstat);
  237. databuf = in_le32(&regs->datport);
  238. *((uint *)buffer) = databuf;
  239. buffer += 4;
  240. size -= 4;
  241. }
  242. blocks--;
  243. }
  244. } else {
  245. blocks = data->blocks;
  246. buffer = (char *)data->src;
  247. while (blocks) {
  248. start = get_timer(0);
  249. size = data->blocksize;
  250. irqstat = esdhc_read32(&regs->irqstat);
  251. while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)) {
  252. if (get_timer(start) > PIO_TIMEOUT) {
  253. printf("\nData Write Failed in PIO Mode.");
  254. return;
  255. }
  256. }
  257. while (size && (!(irqstat & IRQSTAT_TC))) {
  258. udelay(100); /* Wait before last byte transfer complete */
  259. databuf = *((uint *)buffer);
  260. buffer += 4;
  261. size -= 4;
  262. irqstat = esdhc_read32(&regs->irqstat);
  263. out_le32(&regs->datport, databuf);
  264. }
  265. blocks--;
  266. }
  267. }
  268. }
  269. #endif
  270. static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
  271. struct mmc_data *data)
  272. {
  273. int timeout;
  274. struct fsl_esdhc *regs = priv->esdhc_regs;
  275. #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) || \
  276. defined(CONFIG_IMX8ULP)
  277. dma_addr_t addr;
  278. #endif
  279. uint wml_value;
  280. wml_value = data->blocksize/4;
  281. if (data->flags & MMC_DATA_READ) {
  282. if (wml_value > WML_RD_WML_MAX)
  283. wml_value = WML_RD_WML_MAX_VAL;
  284. esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
  285. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  286. #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) || \
  287. defined(CONFIG_IMX8ULP)
  288. addr = virt_to_phys((void *)(data->dest));
  289. if (upper_32_bits(addr))
  290. printf("Error found for upper 32 bits\n");
  291. else
  292. esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
  293. #else
  294. esdhc_write32(&regs->dsaddr, (u32)data->dest);
  295. #endif
  296. #endif
  297. } else {
  298. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  299. flush_dcache_range((ulong)data->src,
  300. (ulong)data->src+data->blocks
  301. *data->blocksize);
  302. #endif
  303. if (wml_value > WML_WR_WML_MAX)
  304. wml_value = WML_WR_WML_MAX_VAL;
  305. if (priv->wp_enable) {
  306. if ((esdhc_read32(&regs->prsstat) &
  307. PRSSTAT_WPSPL) == 0) {
  308. printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
  309. return -ETIMEDOUT;
  310. }
  311. } else {
  312. #if CONFIG_IS_ENABLED(DM_GPIO)
  313. if (dm_gpio_is_valid(&priv->wp_gpio) &&
  314. dm_gpio_get_value(&priv->wp_gpio)) {
  315. printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
  316. return -ETIMEDOUT;
  317. }
  318. #endif
  319. }
  320. esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
  321. wml_value << 16);
  322. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  323. #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) || \
  324. defined(CONFIG_IMX8ULP)
  325. addr = virt_to_phys((void *)(data->src));
  326. if (upper_32_bits(addr))
  327. printf("Error found for upper 32 bits\n");
  328. else
  329. esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
  330. #else
  331. esdhc_write32(&regs->dsaddr, (u32)data->src);
  332. #endif
  333. #endif
  334. }
  335. esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
  336. /* Calculate the timeout period for data transactions */
  337. /*
  338. * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
  339. * 2)Timeout period should be minimum 0.250sec as per SD Card spec
  340. * So, Number of SD Clock cycles for 0.25sec should be minimum
  341. * (SD Clock/sec * 0.25 sec) SD Clock cycles
  342. * = (mmc->clock * 1/4) SD Clock cycles
  343. * As 1) >= 2)
  344. * => (2^(timeout+13)) >= mmc->clock * 1/4
  345. * Taking log2 both the sides
  346. * => timeout + 13 >= log2(mmc->clock/4)
  347. * Rounding up to next power of 2
  348. * => timeout + 13 = log2(mmc->clock/4) + 1
  349. * => timeout + 13 = fls(mmc->clock/4)
  350. *
  351. * However, the MMC spec "It is strongly recommended for hosts to
  352. * implement more than 500ms timeout value even if the card
  353. * indicates the 250ms maximum busy length." Even the previous
  354. * value of 300ms is known to be insufficient for some cards.
  355. * So, we use
  356. * => timeout + 13 = fls(mmc->clock/2)
  357. */
  358. timeout = fls(mmc->clock/2);
  359. timeout -= 13;
  360. if (timeout > 14)
  361. timeout = 14;
  362. if (timeout < 0)
  363. timeout = 0;
  364. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
  365. if ((timeout == 4) || (timeout == 8) || (timeout == 12))
  366. timeout++;
  367. #endif
  368. #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
  369. timeout = 0xE;
  370. #endif
  371. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
  372. return 0;
  373. }
  374. static void check_and_invalidate_dcache_range
  375. (struct mmc_cmd *cmd,
  376. struct mmc_data *data) {
  377. unsigned start = 0;
  378. unsigned end = 0;
  379. unsigned size = roundup(ARCH_DMA_MINALIGN,
  380. data->blocks*data->blocksize);
  381. #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) || \
  382. defined(CONFIG_IMX8ULP)
  383. dma_addr_t addr;
  384. addr = virt_to_phys((void *)(data->dest));
  385. if (upper_32_bits(addr))
  386. printf("Error found for upper 32 bits\n");
  387. else
  388. start = lower_32_bits(addr);
  389. #else
  390. start = (unsigned)data->dest;
  391. #endif
  392. end = start + size;
  393. invalidate_dcache_range(start, end);
  394. }
  395. #ifdef CONFIG_MCF5441x
  396. /*
  397. * Swaps 32-bit words to little-endian byte order.
  398. */
  399. static inline void sd_swap_dma_buff(struct mmc_data *data)
  400. {
  401. int i, size = data->blocksize >> 2;
  402. u32 *buffer = (u32 *)data->dest;
  403. u32 sw;
  404. while (data->blocks--) {
  405. for (i = 0; i < size; i++) {
  406. sw = __sw32(*buffer);
  407. *buffer++ = sw;
  408. }
  409. }
  410. }
  411. #endif
  412. /*
  413. * Sends a command out on the bus. Takes the mmc pointer,
  414. * a command pointer, and an optional data pointer.
  415. */
  416. static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
  417. struct mmc_cmd *cmd, struct mmc_data *data)
  418. {
  419. int err = 0;
  420. uint xfertyp;
  421. uint irqstat;
  422. u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
  423. struct fsl_esdhc *regs = priv->esdhc_regs;
  424. unsigned long start;
  425. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
  426. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  427. return 0;
  428. #endif
  429. esdhc_write32(&regs->irqstat, -1);
  430. sync();
  431. /* Wait for the bus to be idle */
  432. while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
  433. (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
  434. ;
  435. while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
  436. ;
  437. /* Set up for a data transfer if we have one */
  438. if (data) {
  439. err = esdhc_setup_data(priv, mmc, data);
  440. if(err)
  441. return err;
  442. if (data->flags & MMC_DATA_READ)
  443. check_and_invalidate_dcache_range(cmd, data);
  444. }
  445. /* Figure out the transfer arguments */
  446. xfertyp = esdhc_xfertyp(cmd, data);
  447. /* Mask all irqs */
  448. esdhc_write32(&regs->irqsigen, 0);
  449. /* Send the command */
  450. esdhc_write32(&regs->cmdarg, cmd->cmdarg);
  451. #if defined(CONFIG_FSL_USDHC)
  452. esdhc_write32(&regs->mixctrl,
  453. (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
  454. | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
  455. esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
  456. #else
  457. esdhc_write32(&regs->xfertyp, xfertyp);
  458. #endif
  459. if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
  460. (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
  461. flags = IRQSTAT_BRR;
  462. /* Wait for the command to complete */
  463. start = get_timer(0);
  464. while (!(esdhc_read32(&regs->irqstat) & flags)) {
  465. if (get_timer(start) > 1000) {
  466. err = -ETIMEDOUT;
  467. goto out;
  468. }
  469. }
  470. irqstat = esdhc_read32(&regs->irqstat);
  471. if (irqstat & CMD_ERR) {
  472. err = -ECOMM;
  473. goto out;
  474. }
  475. if (irqstat & IRQSTAT_CTOE) {
  476. err = -ETIMEDOUT;
  477. goto out;
  478. }
  479. /* Workaround for ESDHC errata ENGcm03648 */
  480. if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
  481. int timeout = 50000;
  482. /* Poll on DATA0 line for cmd with busy signal for 5000 ms */
  483. while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
  484. PRSSTAT_DAT0)) {
  485. udelay(100);
  486. timeout--;
  487. }
  488. if (timeout <= 0) {
  489. printf("Timeout waiting for DAT0 to go high!\n");
  490. err = -ETIMEDOUT;
  491. goto out;
  492. }
  493. }
  494. /* Copy the response to the response buffer */
  495. if (cmd->resp_type & MMC_RSP_136) {
  496. u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
  497. cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
  498. cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
  499. cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
  500. cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
  501. cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
  502. cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
  503. cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
  504. cmd->response[3] = (cmdrsp0 << 8);
  505. } else
  506. cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
  507. /* Wait until all of the blocks are transferred */
  508. if (data) {
  509. #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
  510. esdhc_pio_read_write(priv, data);
  511. #else
  512. flags = DATA_COMPLETE;
  513. if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
  514. (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
  515. flags = IRQSTAT_BRR;
  516. }
  517. do {
  518. irqstat = esdhc_read32(&regs->irqstat);
  519. if (irqstat & IRQSTAT_DTOE) {
  520. err = -ETIMEDOUT;
  521. goto out;
  522. }
  523. if (irqstat & DATA_ERR) {
  524. err = -ECOMM;
  525. goto out;
  526. }
  527. } while ((irqstat & flags) != flags);
  528. /*
  529. * Need invalidate the dcache here again to avoid any
  530. * cache-fill during the DMA operations such as the
  531. * speculative pre-fetching etc.
  532. */
  533. if (data->flags & MMC_DATA_READ) {
  534. check_and_invalidate_dcache_range(cmd, data);
  535. #ifdef CONFIG_MCF5441x
  536. sd_swap_dma_buff(data);
  537. #endif
  538. }
  539. #endif
  540. }
  541. out:
  542. /* Reset CMD and DATA portions on error */
  543. if (err) {
  544. esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
  545. SYSCTL_RSTC);
  546. while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
  547. ;
  548. if (data) {
  549. esdhc_write32(&regs->sysctl,
  550. esdhc_read32(&regs->sysctl) |
  551. SYSCTL_RSTD);
  552. while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
  553. ;
  554. }
  555. /* If this was CMD11, then notify that power cycle is needed */
  556. if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
  557. printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
  558. }
  559. esdhc_write32(&regs->irqstat, -1);
  560. return err;
  561. }
  562. static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
  563. {
  564. struct fsl_esdhc *regs = priv->esdhc_regs;
  565. int div = 1;
  566. u32 tmp;
  567. int ret;
  568. #ifdef ARCH_MXC
  569. #ifdef CONFIG_MX53
  570. /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
  571. int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
  572. #else
  573. int pre_div = 1;
  574. #endif
  575. #else
  576. int pre_div = 2;
  577. #endif
  578. int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
  579. int sdhc_clk = priv->sdhc_clk;
  580. uint clk;
  581. while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
  582. pre_div *= 2;
  583. while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
  584. div++;
  585. pre_div >>= 1;
  586. div -= 1;
  587. clk = (pre_div << 8) | (div << 4);
  588. #ifdef CONFIG_FSL_USDHC
  589. esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
  590. #else
  591. esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
  592. #endif
  593. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
  594. ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDSTB, 100);
  595. if (ret)
  596. pr_warn("fsl_esdhc_imx: Internal clock never stabilised.\n");
  597. #ifdef CONFIG_FSL_USDHC
  598. esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
  599. #else
  600. esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
  601. #endif
  602. priv->clock = clock;
  603. }
  604. #ifdef MMC_SUPPORTS_TUNING
  605. static int esdhc_change_pinstate(struct udevice *dev)
  606. {
  607. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  608. int ret;
  609. switch (priv->mode) {
  610. case UHS_SDR50:
  611. case UHS_DDR50:
  612. ret = pinctrl_select_state(dev, "state_100mhz");
  613. break;
  614. case UHS_SDR104:
  615. case MMC_HS_200:
  616. case MMC_HS_400:
  617. case MMC_HS_400_ES:
  618. ret = pinctrl_select_state(dev, "state_200mhz");
  619. break;
  620. default:
  621. ret = pinctrl_select_state(dev, "default");
  622. break;
  623. }
  624. if (ret)
  625. printf("%s %d error\n", __func__, priv->mode);
  626. return ret;
  627. }
  628. static void esdhc_reset_tuning(struct mmc *mmc)
  629. {
  630. struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
  631. struct fsl_esdhc *regs = priv->esdhc_regs;
  632. if (priv->flags & ESDHC_FLAG_USDHC) {
  633. if (priv->flags & ESDHC_FLAG_STD_TUNING) {
  634. esdhc_clrbits32(&regs->autoc12err,
  635. MIX_CTRL_SMPCLK_SEL |
  636. MIX_CTRL_EXE_TUNE);
  637. }
  638. }
  639. }
  640. static void esdhc_set_strobe_dll(struct mmc *mmc)
  641. {
  642. struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
  643. struct fsl_esdhc *regs = priv->esdhc_regs;
  644. u32 val;
  645. if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
  646. esdhc_write32(&regs->strobe_dllctrl, ESDHC_STROBE_DLL_CTRL_RESET);
  647. /*
  648. * enable strobe dll ctrl and adjust the delay target
  649. * for the uSDHC loopback read clock
  650. */
  651. val = ESDHC_STROBE_DLL_CTRL_ENABLE |
  652. (priv->strobe_dll_delay_target <<
  653. ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
  654. esdhc_write32(&regs->strobe_dllctrl, val);
  655. /* wait 1us to make sure strobe dll status register stable */
  656. mdelay(1);
  657. val = esdhc_read32(&regs->strobe_dllstat);
  658. if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
  659. pr_warn("HS400 strobe DLL status REF not lock!\n");
  660. if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
  661. pr_warn("HS400 strobe DLL status SLV not lock!\n");
  662. }
  663. }
  664. static int esdhc_set_timing(struct mmc *mmc)
  665. {
  666. struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
  667. struct fsl_esdhc *regs = priv->esdhc_regs;
  668. u32 mixctrl;
  669. mixctrl = esdhc_read32(&regs->mixctrl);
  670. mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
  671. switch (mmc->selected_mode) {
  672. case MMC_LEGACY:
  673. esdhc_reset_tuning(mmc);
  674. esdhc_write32(&regs->mixctrl, mixctrl);
  675. break;
  676. case MMC_HS_400:
  677. case MMC_HS_400_ES:
  678. mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
  679. esdhc_write32(&regs->mixctrl, mixctrl);
  680. break;
  681. case MMC_HS:
  682. case MMC_HS_52:
  683. case MMC_HS_200:
  684. case SD_HS:
  685. case UHS_SDR12:
  686. case UHS_SDR25:
  687. case UHS_SDR50:
  688. case UHS_SDR104:
  689. esdhc_write32(&regs->mixctrl, mixctrl);
  690. break;
  691. case UHS_DDR50:
  692. case MMC_DDR_52:
  693. mixctrl |= MIX_CTRL_DDREN;
  694. esdhc_write32(&regs->mixctrl, mixctrl);
  695. break;
  696. default:
  697. printf("Not supported %d\n", mmc->selected_mode);
  698. return -EINVAL;
  699. }
  700. priv->mode = mmc->selected_mode;
  701. return esdhc_change_pinstate(mmc->dev);
  702. }
  703. static int esdhc_set_voltage(struct mmc *mmc)
  704. {
  705. struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
  706. struct fsl_esdhc *regs = priv->esdhc_regs;
  707. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  708. int ret;
  709. #endif
  710. priv->signal_voltage = mmc->signal_voltage;
  711. switch (mmc->signal_voltage) {
  712. case MMC_SIGNAL_VOLTAGE_330:
  713. if (priv->vs18_enable)
  714. return -ENOTSUPP;
  715. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  716. if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
  717. ret = regulator_set_value(priv->vqmmc_dev, 3300000);
  718. if (ret) {
  719. printf("Setting to 3.3V error");
  720. return -EIO;
  721. }
  722. /* Wait for 5ms */
  723. mdelay(5);
  724. }
  725. #endif
  726. esdhc_clrbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
  727. if (!(esdhc_read32(&regs->vendorspec) &
  728. ESDHC_VENDORSPEC_VSELECT))
  729. return 0;
  730. return -EAGAIN;
  731. case MMC_SIGNAL_VOLTAGE_180:
  732. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  733. if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
  734. ret = regulator_set_value(priv->vqmmc_dev, 1800000);
  735. if (ret) {
  736. printf("Setting to 1.8V error");
  737. return -EIO;
  738. }
  739. }
  740. #endif
  741. esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
  742. /*
  743. * some board like imx8mm-evk need about 18ms to switch
  744. * the IO voltage from 3.3v to 1.8v, common code only
  745. * delay 10ms, so need to delay extra time to make sure
  746. * the IO voltage change to 1.8v.
  747. */
  748. if (priv->signal_voltage_switch_extra_delay_ms)
  749. mdelay(priv->signal_voltage_switch_extra_delay_ms);
  750. if (esdhc_read32(&regs->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
  751. return 0;
  752. return -EAGAIN;
  753. case MMC_SIGNAL_VOLTAGE_120:
  754. return -ENOTSUPP;
  755. default:
  756. return 0;
  757. }
  758. }
  759. static void esdhc_stop_tuning(struct mmc *mmc)
  760. {
  761. struct mmc_cmd cmd;
  762. cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
  763. cmd.cmdarg = 0;
  764. cmd.resp_type = MMC_RSP_R1b;
  765. mmc_send_cmd(mmc, &cmd, NULL);
  766. }
  767. static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
  768. {
  769. struct fsl_esdhc_plat *plat = dev_get_plat(dev);
  770. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  771. struct fsl_esdhc *regs = priv->esdhc_regs;
  772. struct mmc *mmc = &plat->mmc;
  773. u32 irqstaten = esdhc_read32(&regs->irqstaten);
  774. u32 irqsigen = esdhc_read32(&regs->irqsigen);
  775. int i, ret = -ETIMEDOUT;
  776. u32 val, mixctrl;
  777. /* clock tuning is not needed for upto 52MHz */
  778. if (mmc->clock <= 52000000)
  779. return 0;
  780. /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
  781. if (priv->flags & ESDHC_FLAG_STD_TUNING) {
  782. val = esdhc_read32(&regs->autoc12err);
  783. mixctrl = esdhc_read32(&regs->mixctrl);
  784. val &= ~MIX_CTRL_SMPCLK_SEL;
  785. mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
  786. val |= MIX_CTRL_EXE_TUNE;
  787. mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
  788. esdhc_write32(&regs->autoc12err, val);
  789. esdhc_write32(&regs->mixctrl, mixctrl);
  790. }
  791. /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
  792. mixctrl = esdhc_read32(&regs->mixctrl);
  793. mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
  794. esdhc_write32(&regs->mixctrl, mixctrl);
  795. esdhc_write32(&regs->irqstaten, IRQSTATEN_BRR);
  796. esdhc_write32(&regs->irqsigen, IRQSTATEN_BRR);
  797. /*
  798. * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
  799. * of loops reaches 40 times.
  800. */
  801. for (i = 0; i < MAX_TUNING_LOOP; i++) {
  802. u32 ctrl;
  803. if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
  804. if (mmc->bus_width == 8)
  805. esdhc_write32(&regs->blkattr, 0x7080);
  806. else if (mmc->bus_width == 4)
  807. esdhc_write32(&regs->blkattr, 0x7040);
  808. } else {
  809. esdhc_write32(&regs->blkattr, 0x7040);
  810. }
  811. /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
  812. val = esdhc_read32(&regs->mixctrl);
  813. val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
  814. esdhc_write32(&regs->mixctrl, val);
  815. /* We are using STD tuning, no need to check return value */
  816. mmc_send_tuning(mmc, opcode, NULL);
  817. ctrl = esdhc_read32(&regs->autoc12err);
  818. if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
  819. (ctrl & MIX_CTRL_SMPCLK_SEL)) {
  820. ret = 0;
  821. break;
  822. }
  823. }
  824. esdhc_write32(&regs->irqstaten, irqstaten);
  825. esdhc_write32(&regs->irqsigen, irqsigen);
  826. esdhc_stop_tuning(mmc);
  827. return ret;
  828. }
  829. #endif
  830. static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
  831. {
  832. struct fsl_esdhc *regs = priv->esdhc_regs;
  833. int ret __maybe_unused;
  834. u32 clock;
  835. #ifdef MMC_SUPPORTS_TUNING
  836. /*
  837. * call esdhc_set_timing() before update the clock rate,
  838. * This is because current we support DDR and SDR mode,
  839. * Once the DDR_EN bit is set, the card clock will be
  840. * divide by 2 automatically. So need to do this before
  841. * setting clock rate.
  842. */
  843. if (priv->mode != mmc->selected_mode) {
  844. ret = esdhc_set_timing(mmc);
  845. if (ret) {
  846. printf("esdhc_set_timing error %d\n", ret);
  847. return ret;
  848. }
  849. }
  850. #endif
  851. /* Set the clock speed */
  852. clock = mmc->clock;
  853. if (clock < mmc->cfg->f_min)
  854. clock = mmc->cfg->f_min;
  855. if (priv->clock != clock)
  856. set_sysctl(priv, mmc, clock);
  857. #ifdef MMC_SUPPORTS_TUNING
  858. if (mmc->clk_disable) {
  859. #ifdef CONFIG_FSL_USDHC
  860. esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
  861. #else
  862. esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
  863. #endif
  864. } else {
  865. #ifdef CONFIG_FSL_USDHC
  866. esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
  867. VENDORSPEC_CKEN);
  868. #else
  869. esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
  870. #endif
  871. }
  872. /*
  873. * For HS400/HS400ES mode, make sure set the strobe dll in the
  874. * target clock rate. So call esdhc_set_strobe_dll() after the
  875. * clock updated.
  876. */
  877. if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES)
  878. esdhc_set_strobe_dll(mmc);
  879. if (priv->signal_voltage != mmc->signal_voltage) {
  880. ret = esdhc_set_voltage(mmc);
  881. if (ret) {
  882. if (ret != -ENOTSUPP)
  883. printf("esdhc_set_voltage error %d\n", ret);
  884. return ret;
  885. }
  886. }
  887. #endif
  888. /* Set the bus width */
  889. esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
  890. if (mmc->bus_width == 4)
  891. esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
  892. else if (mmc->bus_width == 8)
  893. esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
  894. return 0;
  895. }
  896. static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
  897. {
  898. struct fsl_esdhc *regs = priv->esdhc_regs;
  899. ulong start;
  900. /* Reset the entire host controller */
  901. esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
  902. /* Wait until the controller is available */
  903. start = get_timer(0);
  904. while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
  905. if (get_timer(start) > 1000)
  906. return -ETIMEDOUT;
  907. }
  908. #if defined(CONFIG_FSL_USDHC)
  909. /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
  910. esdhc_write32(&regs->mmcboot, 0x0);
  911. /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
  912. esdhc_write32(&regs->mixctrl, 0x0);
  913. esdhc_write32(&regs->clktunectrlstatus, 0x0);
  914. /* Put VEND_SPEC to default value */
  915. if (priv->vs18_enable)
  916. esdhc_write32(&regs->vendorspec, (VENDORSPEC_INIT |
  917. ESDHC_VENDORSPEC_VSELECT));
  918. else
  919. esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
  920. /* Disable DLL_CTRL delay line */
  921. esdhc_write32(&regs->dllctrl, 0x0);
  922. #endif
  923. #ifndef ARCH_MXC
  924. /* Enable cache snooping */
  925. esdhc_write32(&regs->scr, 0x00000040);
  926. #endif
  927. #ifndef CONFIG_FSL_USDHC
  928. esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
  929. #else
  930. esdhc_setbits32(&regs->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
  931. #endif
  932. /* Set the initial clock speed */
  933. mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
  934. /* Disable the BRR and BWR bits in IRQSTAT */
  935. esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
  936. #ifdef CONFIG_MCF5441x
  937. esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
  938. #else
  939. /* Put the PROCTL reg back to the default */
  940. esdhc_write32(&regs->proctl, PROCTL_INIT);
  941. #endif
  942. /* Set timout to the maximum value */
  943. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
  944. return 0;
  945. }
  946. static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
  947. {
  948. struct fsl_esdhc *regs = priv->esdhc_regs;
  949. int timeout = 1000;
  950. #ifdef CONFIG_ESDHC_DETECT_QUIRK
  951. if (CONFIG_ESDHC_DETECT_QUIRK)
  952. return 1;
  953. #endif
  954. #if CONFIG_IS_ENABLED(DM_MMC)
  955. if (priv->non_removable)
  956. return 1;
  957. if (priv->broken_cd)
  958. return 1;
  959. #if CONFIG_IS_ENABLED(DM_GPIO)
  960. if (dm_gpio_is_valid(&priv->cd_gpio))
  961. return dm_gpio_get_value(&priv->cd_gpio);
  962. #endif
  963. #endif
  964. while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
  965. udelay(1000);
  966. return timeout > 0;
  967. }
  968. static int esdhc_reset(struct fsl_esdhc *regs)
  969. {
  970. ulong start;
  971. /* reset the controller */
  972. esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
  973. /* hardware clears the bit when it is done */
  974. start = get_timer(0);
  975. while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
  976. if (get_timer(start) > 100) {
  977. printf("MMC/SD: Reset never completed.\n");
  978. return -ETIMEDOUT;
  979. }
  980. }
  981. return 0;
  982. }
  983. #if !CONFIG_IS_ENABLED(DM_MMC)
  984. static int esdhc_getcd(struct mmc *mmc)
  985. {
  986. struct fsl_esdhc_priv *priv = mmc->priv;
  987. return esdhc_getcd_common(priv);
  988. }
  989. static int esdhc_init(struct mmc *mmc)
  990. {
  991. struct fsl_esdhc_priv *priv = mmc->priv;
  992. return esdhc_init_common(priv, mmc);
  993. }
  994. static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  995. struct mmc_data *data)
  996. {
  997. struct fsl_esdhc_priv *priv = mmc->priv;
  998. return esdhc_send_cmd_common(priv, mmc, cmd, data);
  999. }
  1000. static int esdhc_set_ios(struct mmc *mmc)
  1001. {
  1002. struct fsl_esdhc_priv *priv = mmc->priv;
  1003. return esdhc_set_ios_common(priv, mmc);
  1004. }
  1005. static const struct mmc_ops esdhc_ops = {
  1006. .getcd = esdhc_getcd,
  1007. .init = esdhc_init,
  1008. .send_cmd = esdhc_send_cmd,
  1009. .set_ios = esdhc_set_ios,
  1010. };
  1011. #endif
  1012. static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
  1013. struct fsl_esdhc_plat *plat)
  1014. {
  1015. struct mmc_config *cfg;
  1016. struct fsl_esdhc *regs;
  1017. u32 caps, voltage_caps;
  1018. int ret;
  1019. if (!priv)
  1020. return -EINVAL;
  1021. regs = priv->esdhc_regs;
  1022. /* First reset the eSDHC controller */
  1023. ret = esdhc_reset(regs);
  1024. if (ret)
  1025. return ret;
  1026. #ifdef CONFIG_MCF5441x
  1027. /* ColdFire, using SDHC_DATA[3] for card detection */
  1028. esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
  1029. #endif
  1030. #ifndef CONFIG_FSL_USDHC
  1031. esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
  1032. | SYSCTL_IPGEN | SYSCTL_CKEN);
  1033. /* Clearing tuning bits in case ROM has set it already */
  1034. esdhc_write32(&regs->mixctrl, 0);
  1035. esdhc_write32(&regs->autoc12err, 0);
  1036. esdhc_write32(&regs->clktunectrlstatus, 0);
  1037. #else
  1038. esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
  1039. VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
  1040. #endif
  1041. if (priv->vs18_enable)
  1042. esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
  1043. esdhc_write32(&regs->irqstaten, SDHCI_IRQ_EN_BITS);
  1044. cfg = &plat->cfg;
  1045. #ifndef CONFIG_DM_MMC
  1046. memset(cfg, '\0', sizeof(*cfg));
  1047. #endif
  1048. voltage_caps = 0;
  1049. caps = esdhc_read32(&regs->hostcapblt);
  1050. #ifdef CONFIG_MCF5441x
  1051. /*
  1052. * MCF5441x RM declares in more points that sdhc clock speed must
  1053. * never exceed 25 Mhz. From this, the HS bit needs to be disabled
  1054. * from host capabilities.
  1055. */
  1056. caps &= ~ESDHC_HOSTCAPBLT_HSS;
  1057. #endif
  1058. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
  1059. caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
  1060. ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
  1061. #endif
  1062. if (caps & ESDHC_HOSTCAPBLT_VS18)
  1063. voltage_caps |= MMC_VDD_165_195;
  1064. if (caps & ESDHC_HOSTCAPBLT_VS30)
  1065. voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
  1066. if (caps & ESDHC_HOSTCAPBLT_VS33)
  1067. voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
  1068. cfg->name = "FSL_SDHC";
  1069. #if !CONFIG_IS_ENABLED(DM_MMC)
  1070. cfg->ops = &esdhc_ops;
  1071. #endif
  1072. #ifdef CONFIG_SYS_SD_VOLTAGE
  1073. cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
  1074. #else
  1075. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  1076. #endif
  1077. if ((cfg->voltages & voltage_caps) == 0) {
  1078. printf("voltage not supported by controller\n");
  1079. return -1;
  1080. }
  1081. if (priv->bus_width == 8)
  1082. cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
  1083. else if (priv->bus_width == 4)
  1084. cfg->host_caps = MMC_MODE_4BIT;
  1085. cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
  1086. #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
  1087. cfg->host_caps |= MMC_MODE_DDR_52MHz;
  1088. #endif
  1089. if (priv->bus_width > 0) {
  1090. if (priv->bus_width < 8)
  1091. cfg->host_caps &= ~MMC_MODE_8BIT;
  1092. if (priv->bus_width < 4)
  1093. cfg->host_caps &= ~MMC_MODE_4BIT;
  1094. }
  1095. if (caps & ESDHC_HOSTCAPBLT_HSS)
  1096. cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  1097. #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
  1098. if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
  1099. cfg->host_caps &= ~MMC_MODE_8BIT;
  1100. #endif
  1101. cfg->host_caps |= priv->caps;
  1102. cfg->f_min = 400000;
  1103. cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
  1104. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  1105. esdhc_write32(&regs->dllctrl, 0);
  1106. if (priv->flags & ESDHC_FLAG_USDHC) {
  1107. if (priv->flags & ESDHC_FLAG_STD_TUNING) {
  1108. u32 val = esdhc_read32(&regs->tuning_ctrl);
  1109. val |= ESDHC_STD_TUNING_EN;
  1110. val &= ~ESDHC_TUNING_START_TAP_MASK;
  1111. val |= priv->tuning_start_tap;
  1112. val &= ~ESDHC_TUNING_STEP_MASK;
  1113. val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
  1114. /* Disable the CMD CRC check for tuning, if not, need to
  1115. * add some delay after every tuning command, because
  1116. * hardware standard tuning logic will directly go to next
  1117. * step once it detect the CMD CRC error, will not wait for
  1118. * the card side to finally send out the tuning data, trigger
  1119. * the buffer read ready interrupt immediately. If usdhc send
  1120. * the next tuning command some eMMC card will stuck, can't
  1121. * response, block the tuning procedure or the first command
  1122. * after the whole tuning procedure always can't get any response.
  1123. */
  1124. val |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
  1125. esdhc_write32(&regs->tuning_ctrl, val);
  1126. }
  1127. }
  1128. return 0;
  1129. }
  1130. #if !CONFIG_IS_ENABLED(DM_MMC)
  1131. static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
  1132. struct fsl_esdhc_priv *priv)
  1133. {
  1134. if (!cfg || !priv)
  1135. return -EINVAL;
  1136. priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
  1137. priv->bus_width = cfg->max_bus_width;
  1138. priv->sdhc_clk = cfg->sdhc_clk;
  1139. priv->wp_enable = cfg->wp_enable;
  1140. priv->vs18_enable = cfg->vs18_enable;
  1141. return 0;
  1142. };
  1143. int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg)
  1144. {
  1145. struct fsl_esdhc_plat *plat;
  1146. struct fsl_esdhc_priv *priv;
  1147. struct mmc *mmc;
  1148. int ret;
  1149. if (!cfg)
  1150. return -EINVAL;
  1151. priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
  1152. if (!priv)
  1153. return -ENOMEM;
  1154. plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
  1155. if (!plat) {
  1156. free(priv);
  1157. return -ENOMEM;
  1158. }
  1159. ret = fsl_esdhc_cfg_to_priv(cfg, priv);
  1160. if (ret) {
  1161. debug("%s xlate failure\n", __func__);
  1162. free(plat);
  1163. free(priv);
  1164. return ret;
  1165. }
  1166. ret = fsl_esdhc_init(priv, plat);
  1167. if (ret) {
  1168. debug("%s init failure\n", __func__);
  1169. free(plat);
  1170. free(priv);
  1171. return ret;
  1172. }
  1173. mmc = mmc_create(&plat->cfg, priv);
  1174. if (!mmc)
  1175. return -EIO;
  1176. priv->mmc = mmc;
  1177. return 0;
  1178. }
  1179. int fsl_esdhc_mmc_init(struct bd_info *bis)
  1180. {
  1181. struct fsl_esdhc_cfg *cfg;
  1182. cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
  1183. cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
  1184. cfg->sdhc_clk = gd->arch.sdhc_clk;
  1185. return fsl_esdhc_initialize(bis, cfg);
  1186. }
  1187. #endif
  1188. #ifdef CONFIG_OF_LIBFDT
  1189. __weak int esdhc_status_fixup(void *blob, const char *compat)
  1190. {
  1191. #ifdef CONFIG_FSL_ESDHC_PIN_MUX
  1192. if (!hwconfig("esdhc")) {
  1193. do_fixup_by_compat(blob, compat, "status", "disabled",
  1194. sizeof("disabled"), 1);
  1195. return 1;
  1196. }
  1197. #endif
  1198. return 0;
  1199. }
  1200. void fdt_fixup_esdhc(void *blob, struct bd_info *bd)
  1201. {
  1202. const char *compat = "fsl,esdhc";
  1203. if (esdhc_status_fixup(blob, compat))
  1204. return;
  1205. do_fixup_by_compat_u32(blob, compat, "clock-frequency",
  1206. gd->arch.sdhc_clk, 1);
  1207. }
  1208. #endif
  1209. #if CONFIG_IS_ENABLED(DM_MMC)
  1210. #include <asm/arch/clock.h>
  1211. __weak void init_clk_usdhc(u32 index)
  1212. {
  1213. }
  1214. static int fsl_esdhc_of_to_plat(struct udevice *dev)
  1215. {
  1216. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  1217. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1218. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  1219. struct udevice *vqmmc_dev;
  1220. int ret;
  1221. #endif
  1222. const void *fdt = gd->fdt_blob;
  1223. int node = dev_of_offset(dev);
  1224. fdt_addr_t addr;
  1225. unsigned int val;
  1226. addr = dev_read_addr(dev);
  1227. if (addr == FDT_ADDR_T_NONE)
  1228. return -EINVAL;
  1229. priv->esdhc_regs = (struct fsl_esdhc *)addr;
  1230. priv->dev = dev;
  1231. priv->mode = -1;
  1232. val = dev_read_u32_default(dev, "bus-width", -1);
  1233. if (val == 8)
  1234. priv->bus_width = 8;
  1235. else if (val == 4)
  1236. priv->bus_width = 4;
  1237. else
  1238. priv->bus_width = 1;
  1239. val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
  1240. priv->tuning_step = val;
  1241. val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
  1242. ESDHC_TUNING_START_TAP_DEFAULT);
  1243. priv->tuning_start_tap = val;
  1244. val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
  1245. ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
  1246. priv->strobe_dll_delay_target = val;
  1247. val = fdtdec_get_int(fdt, node, "fsl,signal-voltage-switch-extra-delay-ms", 0);
  1248. priv->signal_voltage_switch_extra_delay_ms = val;
  1249. if (dev_read_bool(dev, "broken-cd"))
  1250. priv->broken_cd = 1;
  1251. if (dev_read_bool(dev, "non-removable")) {
  1252. priv->non_removable = 1;
  1253. } else {
  1254. priv->non_removable = 0;
  1255. #if CONFIG_IS_ENABLED(DM_GPIO)
  1256. gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
  1257. GPIOD_IS_IN);
  1258. #endif
  1259. }
  1260. if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
  1261. priv->wp_enable = 1;
  1262. } else {
  1263. priv->wp_enable = 0;
  1264. #if CONFIG_IS_ENABLED(DM_GPIO)
  1265. gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
  1266. GPIOD_IS_IN);
  1267. #endif
  1268. }
  1269. priv->vs18_enable = 0;
  1270. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  1271. /*
  1272. * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
  1273. * otherwise, emmc will work abnormally.
  1274. */
  1275. ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
  1276. if (ret) {
  1277. dev_dbg(dev, "no vqmmc-supply\n");
  1278. } else {
  1279. priv->vqmmc_dev = vqmmc_dev;
  1280. ret = regulator_set_enable(vqmmc_dev, true);
  1281. if (ret) {
  1282. dev_err(dev, "fail to enable vqmmc-supply\n");
  1283. return ret;
  1284. }
  1285. if (regulator_get_value(vqmmc_dev) == 1800000)
  1286. priv->vs18_enable = 1;
  1287. }
  1288. #endif
  1289. #endif
  1290. return 0;
  1291. }
  1292. static int fsl_esdhc_probe(struct udevice *dev)
  1293. {
  1294. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  1295. struct fsl_esdhc_plat *plat = dev_get_plat(dev);
  1296. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1297. struct esdhc_soc_data *data =
  1298. (struct esdhc_soc_data *)dev_get_driver_data(dev);
  1299. struct mmc *mmc;
  1300. #if !CONFIG_IS_ENABLED(BLK)
  1301. struct blk_desc *bdesc;
  1302. #endif
  1303. int ret;
  1304. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  1305. struct dtd_fsl_esdhc *dtplat = &plat->dtplat;
  1306. unsigned int val;
  1307. priv->esdhc_regs = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
  1308. val = plat->dtplat.bus_width;
  1309. if (val == 8)
  1310. priv->bus_width = 8;
  1311. else if (val == 4)
  1312. priv->bus_width = 4;
  1313. else
  1314. priv->bus_width = 1;
  1315. if (dtplat->non_removable)
  1316. priv->non_removable = 1;
  1317. else
  1318. priv->non_removable = 0;
  1319. if (CONFIG_IS_ENABLED(DM_GPIO) && !priv->non_removable) {
  1320. struct udevice *gpiodev;
  1321. ret = device_get_by_ofplat_idx(dtplat->cd_gpios->idx, &gpiodev);
  1322. if (ret)
  1323. return ret;
  1324. ret = gpio_dev_request_index(gpiodev, gpiodev->name, "cd-gpios",
  1325. dtplat->cd_gpios->arg[0], GPIOD_IS_IN,
  1326. dtplat->cd_gpios->arg[1], &priv->cd_gpio);
  1327. if (ret)
  1328. return ret;
  1329. }
  1330. #endif
  1331. if (data)
  1332. priv->flags = data->flags;
  1333. /*
  1334. * TODO:
  1335. * Because lack of clk driver, if SDHC clk is not enabled,
  1336. * need to enable it first before this driver is invoked.
  1337. *
  1338. * we use MXC_ESDHC_CLK to get clk freq.
  1339. * If one would like to make this function work,
  1340. * the aliases should be provided in dts as this:
  1341. *
  1342. * aliases {
  1343. * mmc0 = &usdhc1;
  1344. * mmc1 = &usdhc2;
  1345. * mmc2 = &usdhc3;
  1346. * mmc3 = &usdhc4;
  1347. * };
  1348. * Then if your board only supports mmc2 and mmc3, but we can
  1349. * correctly get the seq as 2 and 3, then let mxc_get_clock
  1350. * work as expected.
  1351. */
  1352. init_clk_usdhc(dev_seq(dev));
  1353. #if CONFIG_IS_ENABLED(CLK)
  1354. /* Assigned clock already set clock */
  1355. ret = clk_get_by_name(dev, "per", &priv->per_clk);
  1356. if (ret) {
  1357. printf("Failed to get per_clk\n");
  1358. return ret;
  1359. }
  1360. ret = clk_enable(&priv->per_clk);
  1361. if (ret) {
  1362. printf("Failed to enable per_clk\n");
  1363. return ret;
  1364. }
  1365. priv->sdhc_clk = clk_get_rate(&priv->per_clk);
  1366. #else
  1367. priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev_seq(dev));
  1368. if (priv->sdhc_clk <= 0) {
  1369. dev_err(dev, "Unable to get clk for %s\n", dev->name);
  1370. return -EINVAL;
  1371. }
  1372. #endif
  1373. ret = fsl_esdhc_init(priv, plat);
  1374. if (ret) {
  1375. dev_err(dev, "fsl_esdhc_init failure\n");
  1376. return ret;
  1377. }
  1378. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  1379. ret = mmc_of_parse(dev, &plat->cfg);
  1380. if (ret)
  1381. return ret;
  1382. #endif
  1383. mmc = &plat->mmc;
  1384. mmc->cfg = &plat->cfg;
  1385. mmc->dev = dev;
  1386. #if !CONFIG_IS_ENABLED(BLK)
  1387. mmc->priv = priv;
  1388. /* Setup dsr related values */
  1389. mmc->dsr_imp = 0;
  1390. mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
  1391. /* Setup the universal parts of the block interface just once */
  1392. bdesc = mmc_get_blk_desc(mmc);
  1393. bdesc->if_type = IF_TYPE_MMC;
  1394. bdesc->removable = 1;
  1395. bdesc->devnum = mmc_get_next_devnum();
  1396. bdesc->block_read = mmc_bread;
  1397. bdesc->block_write = mmc_bwrite;
  1398. bdesc->block_erase = mmc_berase;
  1399. /* setup initial part type */
  1400. bdesc->part_type = mmc->cfg->part_type;
  1401. mmc_list_add(mmc);
  1402. #endif
  1403. upriv->mmc = mmc;
  1404. return esdhc_init_common(priv, mmc);
  1405. }
  1406. #if CONFIG_IS_ENABLED(DM_MMC)
  1407. static int fsl_esdhc_get_cd(struct udevice *dev)
  1408. {
  1409. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1410. return esdhc_getcd_common(priv);
  1411. }
  1412. static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  1413. struct mmc_data *data)
  1414. {
  1415. struct fsl_esdhc_plat *plat = dev_get_plat(dev);
  1416. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1417. return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
  1418. }
  1419. static int fsl_esdhc_set_ios(struct udevice *dev)
  1420. {
  1421. struct fsl_esdhc_plat *plat = dev_get_plat(dev);
  1422. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1423. return esdhc_set_ios_common(priv, &plat->mmc);
  1424. }
  1425. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  1426. static int fsl_esdhc_set_enhanced_strobe(struct udevice *dev)
  1427. {
  1428. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1429. struct fsl_esdhc *regs = priv->esdhc_regs;
  1430. u32 m;
  1431. m = esdhc_read32(&regs->mixctrl);
  1432. m |= MIX_CTRL_HS400_ES;
  1433. esdhc_write32(&regs->mixctrl, m);
  1434. return 0;
  1435. }
  1436. #endif
  1437. static int fsl_esdhc_wait_dat0(struct udevice *dev, int state,
  1438. int timeout_us)
  1439. {
  1440. int ret;
  1441. u32 tmp;
  1442. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1443. struct fsl_esdhc *regs = priv->esdhc_regs;
  1444. ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp,
  1445. !!(tmp & PRSSTAT_DAT0) == !!state,
  1446. timeout_us);
  1447. return ret;
  1448. }
  1449. static const struct dm_mmc_ops fsl_esdhc_ops = {
  1450. .get_cd = fsl_esdhc_get_cd,
  1451. .send_cmd = fsl_esdhc_send_cmd,
  1452. .set_ios = fsl_esdhc_set_ios,
  1453. #ifdef MMC_SUPPORTS_TUNING
  1454. .execute_tuning = fsl_esdhc_execute_tuning,
  1455. #endif
  1456. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  1457. .set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe,
  1458. #endif
  1459. .wait_dat0 = fsl_esdhc_wait_dat0,
  1460. };
  1461. #endif
  1462. static struct esdhc_soc_data usdhc_imx7d_data = {
  1463. .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
  1464. | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
  1465. | ESDHC_FLAG_HS400,
  1466. };
  1467. static struct esdhc_soc_data usdhc_imx8qm_data = {
  1468. .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING |
  1469. ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 |
  1470. ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES,
  1471. };
  1472. static const struct udevice_id fsl_esdhc_ids[] = {
  1473. { .compatible = "fsl,imx51-esdhc", },
  1474. { .compatible = "fsl,imx53-esdhc", },
  1475. { .compatible = "fsl,imx6ul-usdhc", },
  1476. { .compatible = "fsl,imx6sx-usdhc", },
  1477. { .compatible = "fsl,imx6sl-usdhc", },
  1478. { .compatible = "fsl,imx6q-usdhc", },
  1479. { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
  1480. { .compatible = "fsl,imx7ulp-usdhc", },
  1481. { .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
  1482. { .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
  1483. { .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
  1484. { .compatible = "fsl,imx8mq-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
  1485. { .compatible = "fsl,imxrt-usdhc", },
  1486. { .compatible = "fsl,esdhc", },
  1487. { /* sentinel */ }
  1488. };
  1489. #if CONFIG_IS_ENABLED(BLK)
  1490. static int fsl_esdhc_bind(struct udevice *dev)
  1491. {
  1492. struct fsl_esdhc_plat *plat = dev_get_plat(dev);
  1493. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  1494. }
  1495. #endif
  1496. U_BOOT_DRIVER(fsl_esdhc) = {
  1497. .name = "fsl_esdhc",
  1498. .id = UCLASS_MMC,
  1499. .of_match = fsl_esdhc_ids,
  1500. .of_to_plat = fsl_esdhc_of_to_plat,
  1501. .ops = &fsl_esdhc_ops,
  1502. #if CONFIG_IS_ENABLED(BLK)
  1503. .bind = fsl_esdhc_bind,
  1504. #endif
  1505. .probe = fsl_esdhc_probe,
  1506. .plat_auto = sizeof(struct fsl_esdhc_plat),
  1507. .priv_auto = sizeof(struct fsl_esdhc_priv),
  1508. };
  1509. DM_DRIVER_ALIAS(fsl_esdhc, fsl_imx6q_usdhc)
  1510. #endif