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- # SPDX-License-Identifier: GPL-2.0+
- #
- # Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
- config SIFIVE_FU540
- bool
- select ARCH_EARLY_INIT_R
- select SUPPORT_SPL
- select RAM
- select SPL_RAM if SPL
- imply CPU
- imply CPU_RISCV
- imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
- imply SPL_SIFIVE_CLINT
- imply CMD_CPU
- imply SPL_CPU
- imply SPL_OPENSBI
- imply SPL_LOAD_FIT
- imply SMP
- imply CLK_SIFIVE
- imply CLK_SIFIVE_PRCI
- imply SIFIVE_SERIAL
- imply MACB
- imply MII
- imply SPI
- imply SPI_SIFIVE
- imply MMC
- imply MMC_SPI
- imply MMC_BROKEN_CD
- imply CMD_MMC
- imply DM_GPIO
- imply SIFIVE_GPIO
- imply CMD_GPIO
- imply MISC
- imply SIFIVE_OTP
- imply DM_PWM
- imply PWM_SIFIVE
- imply DM_I2C
- imply SYS_I2C_OCORES
- if ENV_IS_IN_SPI_FLASH
- config ENV_OFFSET
- default 0x505000
- config ENV_SIZE
- default 0x20000
- config ENV_SECT_SIZE
- default 0x10000
- endif # ENV_IS_IN_SPI_FLASH
- config SIFIVE_FU540_L2CC_FLUSH
- bool "Support Level 2 Cache Controller Flush operation of SiFive fu540"
- menu "Level 2 Cache Controller Flush range"
- depends on SIFIVE_FU540_L2CC_FLUSH
- config SIFIVE_FU540_L2CC_FLUSH_START
- hex "Level 2 Cache Flush operation start"
- default 0x80000000
- config SIFIVE_FU540_L2CC_FLUSH_SIZE
- hex "Level 2 Cache Flush operation size"
- default 0x800000000
- endmenu # SIFIVE_FU540_L2CC_FLUSH
- config SIFIVE_FU540_L2CC_WAYENABLE_DIY
- bool "Config Level 2 Cache Controller: the largest way which has been enabled"
- menu "The index of the largest way"
- depends on SIFIVE_FU540_L2CC_WAYENABLE_DIY
- config SIFIVE_FU540_L2CC_WAYENABLE_DIY_NUM
- int "The index of the largest way which has been enabled for level 2 Cache "
- default 1
- range 0 255
- help
- Range[0, 255]. The index of the largest way which has been enabled.
- endmenu # SIFIVE_FU540_L2CC_WAYENABLE_DIY
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