km83xx.c 9.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2006 Freescale Semiconductor, Inc.
  4. * Dave Liu <daveliu@freescale.com>
  5. *
  6. * Copyright (C) 2007 Logic Product Development, Inc.
  7. * Peter Barada <peterb@logicpd.com>
  8. *
  9. * Copyright (C) 2007 MontaVista Software, Inc.
  10. * Anton Vorontsov <avorontsov@ru.mvista.com>
  11. *
  12. * (C) Copyright 2008 - 2010
  13. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14. */
  15. #include <common.h>
  16. #include <env.h>
  17. #include <fdt_support.h>
  18. #include <init.h>
  19. #include <ioports.h>
  20. #include <mpc83xx.h>
  21. #include <i2c.h>
  22. #include <miiphy.h>
  23. #include <asm/io.h>
  24. #include <asm/mmu.h>
  25. #include <asm/processor.h>
  26. #include <pci.h>
  27. #include <linux/libfdt.h>
  28. #include <post.h>
  29. #include "../common/common.h"
  30. DECLARE_GLOBAL_DATA_PTR;
  31. static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
  32. const qe_iop_conf_t qe_iop_conf_tab[] = {
  33. /* port pin dir open_drain assign */
  34. #if defined(CONFIG_ARCH_MPC8360)
  35. /* MDIO */
  36. {0, 1, 3, 0, 2}, /* MDIO */
  37. {0, 2, 1, 0, 1}, /* MDC */
  38. /* UCC4 - UEC */
  39. {1, 14, 1, 0, 1}, /* TxD0 */
  40. {1, 15, 1, 0, 1}, /* TxD1 */
  41. {1, 20, 2, 0, 1}, /* RxD0 */
  42. {1, 21, 2, 0, 1}, /* RxD1 */
  43. {1, 18, 1, 0, 1}, /* TX_EN */
  44. {1, 26, 2, 0, 1}, /* RX_DV */
  45. {1, 27, 2, 0, 1}, /* RX_ER */
  46. {1, 24, 2, 0, 1}, /* COL */
  47. {1, 25, 2, 0, 1}, /* CRS */
  48. {2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */
  49. {2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */
  50. /* DUART - UART2 */
  51. {5, 0, 1, 0, 2}, /* UART2_SOUT */
  52. {5, 2, 1, 0, 1}, /* UART2_RTS */
  53. {5, 3, 2, 0, 2}, /* UART2_SIN */
  54. {5, 1, 2, 0, 3}, /* UART2_CTS */
  55. #elif !defined(CONFIG_ARCH_MPC8309)
  56. /* Local Bus */
  57. {0, 16, 1, 0, 3}, /* LA00 */
  58. {0, 17, 1, 0, 3}, /* LA01 */
  59. {0, 18, 1, 0, 3}, /* LA02 */
  60. {0, 19, 1, 0, 3}, /* LA03 */
  61. {0, 20, 1, 0, 3}, /* LA04 */
  62. {0, 21, 1, 0, 3}, /* LA05 */
  63. {0, 22, 1, 0, 3}, /* LA06 */
  64. {0, 23, 1, 0, 3}, /* LA07 */
  65. {0, 24, 1, 0, 3}, /* LA08 */
  66. {0, 25, 1, 0, 3}, /* LA09 */
  67. {0, 26, 1, 0, 3}, /* LA10 */
  68. {0, 27, 1, 0, 3}, /* LA11 */
  69. {0, 28, 1, 0, 3}, /* LA12 */
  70. {0, 29, 1, 0, 3}, /* LA13 */
  71. {0, 30, 1, 0, 3}, /* LA14 */
  72. {0, 31, 1, 0, 3}, /* LA15 */
  73. /* MDIO */
  74. {3, 4, 3, 0, 2}, /* MDIO */
  75. {3, 5, 1, 0, 2}, /* MDC */
  76. /* UCC4 - UEC */
  77. {1, 18, 1, 0, 1}, /* TxD0 */
  78. {1, 19, 1, 0, 1}, /* TxD1 */
  79. {1, 22, 2, 0, 1}, /* RxD0 */
  80. {1, 23, 2, 0, 1}, /* RxD1 */
  81. {1, 26, 2, 0, 1}, /* RxER */
  82. {1, 28, 2, 0, 1}, /* Rx_DV */
  83. {1, 30, 1, 0, 1}, /* TxEN */
  84. {1, 31, 2, 0, 1}, /* CRS */
  85. {3, 10, 2, 0, 3}, /* TxCLK->CLK17 */
  86. #endif
  87. /* END of table */
  88. {0, 0, 0, 0, QE_IOP_TAB_END},
  89. };
  90. #if defined(CONFIG_SUVD3)
  91. const uint upma_table[] = {
  92. 0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, /* Words 0 to 3 */
  93. 0x0ffcdc00, 0xffffcc00, 0xffffcc01, 0xfffffc01, /* Words 4 to 7 */
  94. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 8 to 11 */
  95. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 12 to 15 */
  96. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 16 to 19 */
  97. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 20 to 23 */
  98. 0x9cfffc00, 0x00fffc80, 0x00fffc80, 0x00fffc00, /* Words 24 to 27 */
  99. 0xffffec04, 0xffffec01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */
  100. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 32 to 35 */
  101. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 36 to 39 */
  102. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 40 to 43 */
  103. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 44 to 47 */
  104. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 48 to 51 */
  105. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 52 to 55 */
  106. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 56 to 59 */
  107. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01 /* Words 60 to 63 */
  108. };
  109. #endif
  110. static int piggy_present(void)
  111. {
  112. struct km_bec_fpga __iomem *base =
  113. (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
  114. return in_8(&base->bprth) & PIGGY_PRESENT;
  115. }
  116. int ethernet_present(void)
  117. {
  118. return piggy_present();
  119. }
  120. int board_early_init_r(void)
  121. {
  122. struct km_bec_fpga *base =
  123. (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
  124. #if defined(CONFIG_SUVD3)
  125. immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  126. fsl_lbc_t *lbc = &immap->im_lbc;
  127. u32 *mxmr = &lbc->mamr;
  128. #endif
  129. #if defined(CONFIG_ARCH_MPC8360)
  130. unsigned short svid;
  131. /*
  132. * Because of errata in the UCCs, we have to write to the reserved
  133. * registers to slow the clocks down.
  134. */
  135. svid = SVR_REV(mfspr(SVR));
  136. switch (svid) {
  137. case 0x0020:
  138. /*
  139. * MPC8360ECE.pdf QE_ENET10 table 4:
  140. * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
  141. * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
  142. */
  143. setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
  144. break;
  145. case 0x0021:
  146. /*
  147. * MPC8360ECE.pdf QE_ENET10 table 4:
  148. * IMMR + 0x14AC[24:27] = 1010
  149. */
  150. clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
  151. 0x00000050, 0x000000a0);
  152. break;
  153. }
  154. #endif
  155. /* enable the PHY on the PIGGY */
  156. setbits_8(&base->pgy_eth, 0x01);
  157. /* enable the Unit LED (green) */
  158. setbits_8(&base->oprth, WRL_BOOT);
  159. /* enable Application Buffer */
  160. setbits_8(&base->oprtl, OPRTL_XBUFENA);
  161. #if defined(CONFIG_SUVD3)
  162. /* configure UPMA for APP1 */
  163. upmconfig(UPMA, (uint *) upma_table,
  164. sizeof(upma_table) / sizeof(uint));
  165. out_be32(mxmr, CONFIG_SYS_MAMR);
  166. #endif
  167. return 0;
  168. }
  169. int misc_init_r(void)
  170. {
  171. ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
  172. CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
  173. return 0;
  174. }
  175. int last_stage_init(void)
  176. {
  177. #if defined(CONFIG_TARGET_KMCOGE5NE)
  178. struct bfticu_iomap *base =
  179. (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
  180. u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
  181. if (dip_switch != 0) {
  182. /* start bootloader */
  183. puts("DIP: Enabled\n");
  184. env_set("actual_bank", "0");
  185. }
  186. #endif
  187. set_km_env();
  188. return 0;
  189. }
  190. static int fixed_sdram(void)
  191. {
  192. immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  193. u32 msize = 0;
  194. u32 ddr_size;
  195. u32 ddr_size_log2;
  196. out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
  197. out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f);
  198. out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
  199. out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
  200. out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
  201. out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
  202. out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
  203. out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
  204. out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
  205. out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
  206. out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
  207. out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
  208. out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
  209. udelay(200);
  210. setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
  211. msize = CONFIG_SYS_DDR_SIZE << 20;
  212. disable_addr_trans();
  213. msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
  214. enable_addr_trans();
  215. msize /= (1024 * 1024);
  216. if (CONFIG_SYS_DDR_SIZE != msize) {
  217. for (ddr_size = msize << 20, ddr_size_log2 = 0;
  218. (ddr_size > 1);
  219. ddr_size = ddr_size >> 1, ddr_size_log2++)
  220. if (ddr_size & 1)
  221. return -1;
  222. out_be32(&im->sysconf.ddrlaw[0].ar,
  223. (LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE)));
  224. out_be32(&im->ddr.csbnds[0].csbnds,
  225. (((msize / 16) - 1) & 0xff));
  226. }
  227. return msize;
  228. }
  229. int dram_init(void)
  230. {
  231. immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  232. u32 msize = 0;
  233. if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
  234. return -ENXIO;
  235. out_be32(&im->sysconf.ddrlaw[0].bar,
  236. CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR);
  237. msize = fixed_sdram();
  238. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  239. /*
  240. * Initialize DDR ECC byte
  241. */
  242. ddr_enable_ecc(msize * 1024 * 1024);
  243. #endif
  244. /* return total bus SDRAM size(bytes) -- DDR */
  245. gd->ram_size = msize * 1024 * 1024;
  246. return 0;
  247. }
  248. int checkboard(void)
  249. {
  250. puts("Board: ABB " CONFIG_SYS_CONFIG_NAME);
  251. if (piggy_present())
  252. puts(" with PIGGY.");
  253. puts("\n");
  254. return 0;
  255. }
  256. int ft_board_setup(void *blob, bd_t *bd)
  257. {
  258. ft_cpu_setup(blob, bd);
  259. return 0;
  260. }
  261. #if defined(CONFIG_HUSH_INIT_VAR)
  262. int hush_init_var(void)
  263. {
  264. ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
  265. return 0;
  266. }
  267. #endif
  268. #if defined(CONFIG_POST)
  269. int post_hotkeys_pressed(void)
  270. {
  271. int testpin = 0;
  272. struct km_bec_fpga *base =
  273. (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
  274. int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG);
  275. testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0;
  276. debug("post_hotkeys_pressed: %d\n", !testpin);
  277. return testpin;
  278. }
  279. ulong post_word_load(void)
  280. {
  281. void* addr = (ulong *) (CPM_POST_WORD_ADDR);
  282. debug("post_word_load 0x%08lX: 0x%08X\n", (ulong)addr, in_le32(addr));
  283. return in_le32(addr);
  284. }
  285. void post_word_store(ulong value)
  286. {
  287. void* addr = (ulong *) (CPM_POST_WORD_ADDR);
  288. debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value);
  289. out_le32(addr, value);
  290. }
  291. int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
  292. {
  293. /*
  294. * These match CONFIG_SYS_MEMTEST_START and
  295. * (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START)
  296. */
  297. *vstart = 0x00100000;
  298. *size = 0xe00000;
  299. debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size);
  300. return 0;
  301. }
  302. #endif