cgtqmx6eval.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
  4. * Based on mx6qsabrelite.c file
  5. * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
  6. * Leo Sartre, <lsartre@adeneo-embedded.com>
  7. */
  8. #include <common.h>
  9. #include <init.h>
  10. #include <net.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include <asm/arch/iomux.h>
  15. #include <asm/arch/mx6-pins.h>
  16. #include <asm/gpio.h>
  17. #include <asm/mach-imx/iomux-v3.h>
  18. #include <asm/mach-imx/sata.h>
  19. #include <asm/mach-imx/boot_mode.h>
  20. #include <asm/mach-imx/mxc_i2c.h>
  21. #include <asm/arch/sys_proto.h>
  22. #include <asm/arch/mxc_hdmi.h>
  23. #include <asm/arch/crm_regs.h>
  24. #include <env.h>
  25. #include <mmc.h>
  26. #include <fsl_esdhc_imx.h>
  27. #include <i2c.h>
  28. #include <input.h>
  29. #include <linux/delay.h>
  30. #include <power/pmic.h>
  31. #include <power/pfuze100_pmic.h>
  32. #include <linux/fb.h>
  33. #include <ipu_pixfmt.h>
  34. #include <malloc.h>
  35. #include <miiphy.h>
  36. #include <netdev.h>
  37. #include <micrel.h>
  38. #include <spi_flash.h>
  39. #include <spi.h>
  40. DECLARE_GLOBAL_DATA_PTR;
  41. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |\
  42. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  43. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
  44. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  45. #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  46. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  47. PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  48. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  49. #define SPI_PAD_CTRL (PAD_CTL_HYS | \
  50. PAD_CTL_SPEED_MED | \
  51. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  52. #define MX6Q_QMX6_PFUZE_MUX IMX_GPIO_NR(6, 9)
  53. #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  54. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  55. PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  56. int dram_init(void)
  57. {
  58. gd->ram_size = imx_ddr_size();
  59. return 0;
  60. }
  61. static iomux_v3_cfg_t const uart2_pads[] = {
  62. IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  63. IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  64. };
  65. #ifndef CONFIG_SPL_BUILD
  66. static iomux_v3_cfg_t const usdhc2_pads[] = {
  67. IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  68. IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  69. IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  70. IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  71. IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  72. IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  73. IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  74. };
  75. static iomux_v3_cfg_t const usdhc3_pads[] = {
  76. IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  77. IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  78. IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  79. IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  80. IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  81. IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  82. IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  83. IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  84. IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  85. IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  86. IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  87. };
  88. #endif
  89. static iomux_v3_cfg_t const usdhc4_pads[] = {
  90. IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  91. IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  92. IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  93. IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  94. IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  95. IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  96. IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  97. IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  98. IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  99. IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  100. IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  101. };
  102. static iomux_v3_cfg_t const usb_otg_pads[] = {
  103. IOMUX_PADS(PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)),
  104. IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
  105. };
  106. static iomux_v3_cfg_t enet_pads_ksz9031[] = {
  107. IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  108. IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  109. IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  110. IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  111. IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  112. IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  113. IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  114. IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  115. IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  116. IOMUX_PADS(PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  117. IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  118. IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  119. IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  120. IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  121. IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  122. };
  123. static iomux_v3_cfg_t enet_pads_final_ksz9031[] = {
  124. IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  125. IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  126. IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  127. IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  128. IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  129. IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  130. };
  131. static iomux_v3_cfg_t enet_pads_ar8035[] = {
  132. IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  133. IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  134. IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  135. IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  136. IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  137. IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  138. IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  139. IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  140. IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  141. IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  142. IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  143. IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  144. IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  145. IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  146. IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  147. };
  148. static iomux_v3_cfg_t const ecspi1_pads[] = {
  149. IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  150. IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  151. IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  152. IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  153. };
  154. #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  155. struct i2c_pads_info mx6q_i2c_pad_info1 = {
  156. .scl = {
  157. .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
  158. .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
  159. .gp = IMX_GPIO_NR(4, 12)
  160. },
  161. .sda = {
  162. .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
  163. .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
  164. .gp = IMX_GPIO_NR(4, 13)
  165. }
  166. };
  167. struct i2c_pads_info mx6dl_i2c_pad_info1 = {
  168. .scl = {
  169. .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
  170. .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
  171. .gp = IMX_GPIO_NR(4, 12)
  172. },
  173. .sda = {
  174. .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
  175. .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
  176. .gp = IMX_GPIO_NR(4, 13)
  177. }
  178. };
  179. #define I2C_PMIC 1 /* I2C2 port is used to connect to the PMIC */
  180. struct interface_level {
  181. char *name;
  182. uchar value;
  183. };
  184. static struct interface_level mipi_levels[] = {
  185. {"0V0", 0x00},
  186. {"2V5", 0x17},
  187. };
  188. /* setup board specific PMIC */
  189. int power_init_board(void)
  190. {
  191. struct pmic *p;
  192. u32 id1, id2, i;
  193. int ret;
  194. char const *lv_mipi;
  195. /* configure I2C multiplexer */
  196. gpio_direction_output(MX6Q_QMX6_PFUZE_MUX, 1);
  197. power_pfuze100_init(I2C_PMIC);
  198. p = pmic_get("PFUZE100");
  199. if (!p)
  200. return -EINVAL;
  201. ret = pmic_probe(p);
  202. if (ret)
  203. return ret;
  204. pmic_reg_read(p, PFUZE100_DEVICEID, &id1);
  205. pmic_reg_read(p, PFUZE100_REVID, &id2);
  206. printf("PFUZE100 Rev. [%02x/%02x] detected\n", id1, id2);
  207. if (id2 >= 0x20)
  208. return 0;
  209. /* set level of MIPI if specified */
  210. lv_mipi = env_get("lv_mipi");
  211. if (lv_mipi)
  212. return 0;
  213. for (i = 0; i < ARRAY_SIZE(mipi_levels); i++) {
  214. if (!strcmp(mipi_levels[i].name, lv_mipi)) {
  215. printf("set MIPI level %s\n", mipi_levels[i].name);
  216. ret = pmic_reg_write(p, PFUZE100_VGEN4VOL,
  217. mipi_levels[i].value);
  218. if (ret)
  219. return ret;
  220. }
  221. }
  222. return 0;
  223. }
  224. int board_eth_init(bd_t *bis)
  225. {
  226. struct phy_device *phydev;
  227. struct mii_dev *bus;
  228. unsigned short id1, id2;
  229. int ret;
  230. /* check whether KSZ9031 or AR8035 has to be configured */
  231. SETUP_IOMUX_PADS(enet_pads_ar8035);
  232. /* phy reset */
  233. gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
  234. udelay(2000);
  235. gpio_set_value(IMX_GPIO_NR(3, 23), 1);
  236. udelay(500);
  237. bus = fec_get_miibus(IMX_FEC_BASE, -1);
  238. if (!bus)
  239. return -EINVAL;
  240. phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
  241. if (!phydev) {
  242. printf("Error: phy device not found.\n");
  243. ret = -ENODEV;
  244. goto free_bus;
  245. }
  246. /* get the PHY id */
  247. id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
  248. id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
  249. if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
  250. /* re-configure for Micrel KSZ9031 */
  251. printf("configure Micrel KSZ9031 Ethernet Phy at address %d\n",
  252. phydev->addr);
  253. /* phy reset: gpio3-23 */
  254. gpio_set_value(IMX_GPIO_NR(3, 23), 0);
  255. gpio_set_value(IMX_GPIO_NR(6, 30), (phydev->addr >> 2));
  256. gpio_set_value(IMX_GPIO_NR(6, 25), 1);
  257. gpio_set_value(IMX_GPIO_NR(6, 27), 1);
  258. gpio_set_value(IMX_GPIO_NR(6, 28), 1);
  259. gpio_set_value(IMX_GPIO_NR(6, 29), 1);
  260. SETUP_IOMUX_PADS(enet_pads_ksz9031);
  261. gpio_set_value(IMX_GPIO_NR(6, 24), 1);
  262. udelay(500);
  263. gpio_set_value(IMX_GPIO_NR(3, 23), 1);
  264. SETUP_IOMUX_PADS(enet_pads_final_ksz9031);
  265. } else if ((id1 == 0x004d) && (id2 == 0xd072)) {
  266. /* configure Atheros AR8035 - actually nothing to do */
  267. printf("configure Atheros AR8035 Ethernet Phy at address %d\n",
  268. phydev->addr);
  269. } else {
  270. printf("Unknown Ethernet-Phy: 0x%04x 0x%04x\n", id1, id2);
  271. ret = -EINVAL;
  272. goto free_phydev;
  273. }
  274. ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);
  275. if (ret)
  276. goto free_phydev;
  277. return 0;
  278. free_phydev:
  279. free(phydev);
  280. free_bus:
  281. free(bus);
  282. return ret;
  283. }
  284. int mx6_rgmii_rework(struct phy_device *phydev)
  285. {
  286. unsigned short id1, id2;
  287. unsigned short val;
  288. /* check whether KSZ9031 or AR8035 has to be configured */
  289. id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
  290. id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
  291. if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
  292. /* finalize phy configuration for Micrel KSZ9031 */
  293. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
  294. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 4);
  295. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
  296. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x0000);
  297. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
  298. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 5);
  299. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
  300. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_REG);
  301. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
  302. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 6);
  303. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
  304. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0xFFFF);
  305. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
  306. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 8);
  307. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
  308. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x3FFF);
  309. /* fix KSZ9031 link up issue */
  310. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 0x0);
  311. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x4);
  312. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC);
  313. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x6);
  314. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_REG);
  315. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x3);
  316. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC);
  317. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x1A80);
  318. }
  319. if ((id1 == 0x004d) && (id2 == 0xd072)) {
  320. /* enable AR8035 ouput a 125MHz clk from CLK_25M */
  321. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 0x7);
  322. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_DATA_POST_INC_RW | 0x16);
  323. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC | 0x7);
  324. val = phy_read(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA);
  325. val &= 0xfe63;
  326. val |= 0x18;
  327. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, val);
  328. /* introduce tx clock delay */
  329. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  330. val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  331. val |= 0x0100;
  332. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
  333. /* disable hibernation */
  334. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0xb);
  335. val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  336. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3c40);
  337. }
  338. return 0;
  339. }
  340. int board_phy_config(struct phy_device *phydev)
  341. {
  342. mx6_rgmii_rework(phydev);
  343. if (phydev->drv->config)
  344. phydev->drv->config(phydev);
  345. return 0;
  346. }
  347. static void setup_iomux_uart(void)
  348. {
  349. SETUP_IOMUX_PADS(uart2_pads);
  350. }
  351. #ifdef CONFIG_MXC_SPI
  352. static void setup_spi(void)
  353. {
  354. SETUP_IOMUX_PADS(ecspi1_pads);
  355. gpio_direction_output(IMX_GPIO_NR(3, 19), 0);
  356. }
  357. #endif
  358. #ifdef CONFIG_FSL_ESDHC_IMX
  359. static struct fsl_esdhc_cfg usdhc_cfg[] = {
  360. {USDHC2_BASE_ADDR},
  361. {USDHC3_BASE_ADDR},
  362. {USDHC4_BASE_ADDR},
  363. };
  364. int board_mmc_getcd(struct mmc *mmc)
  365. {
  366. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  367. int ret = 0;
  368. switch (cfg->esdhc_base) {
  369. case USDHC2_BASE_ADDR:
  370. gpio_direction_input(IMX_GPIO_NR(1, 4));
  371. ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
  372. break;
  373. case USDHC3_BASE_ADDR:
  374. ret = 1; /* eMMC is always present */
  375. break;
  376. case USDHC4_BASE_ADDR:
  377. gpio_direction_input(IMX_GPIO_NR(2, 6));
  378. ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
  379. break;
  380. default:
  381. printf("Bad USDHC interface\n");
  382. }
  383. return ret;
  384. }
  385. int board_mmc_init(bd_t *bis)
  386. {
  387. #ifndef CONFIG_SPL_BUILD
  388. s32 status = 0;
  389. int i;
  390. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  391. usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  392. usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  393. SETUP_IOMUX_PADS(usdhc2_pads);
  394. SETUP_IOMUX_PADS(usdhc3_pads);
  395. SETUP_IOMUX_PADS(usdhc4_pads);
  396. for (i = 0; i < ARRAY_SIZE(usdhc_cfg); i++) {
  397. status = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  398. if (status)
  399. return status;
  400. }
  401. return 0;
  402. #else
  403. SETUP_IOMUX_PADS(usdhc4_pads);
  404. usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
  405. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  406. gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  407. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  408. #endif
  409. }
  410. #endif
  411. int board_ehci_hcd_init(int port)
  412. {
  413. switch (port) {
  414. case 0:
  415. SETUP_IOMUX_PADS(usb_otg_pads);
  416. /*
  417. * set daisy chain for otg_pin_id on 6q.
  418. * for 6dl, this bit is reserved
  419. */
  420. imx_iomux_set_gpr_register(1, 13, 1, 1);
  421. break;
  422. case 1:
  423. /* nothing to do */
  424. break;
  425. default:
  426. printf("Invalid USB port: %d\n", port);
  427. return -EINVAL;
  428. }
  429. return 0;
  430. }
  431. int board_ehci_power(int port, int on)
  432. {
  433. switch (port) {
  434. case 0:
  435. break;
  436. case 1:
  437. gpio_direction_output(IMX_GPIO_NR(5, 5), on);
  438. break;
  439. default:
  440. printf("Invalid USB port: %d\n", port);
  441. return -EINVAL;
  442. }
  443. return 0;
  444. }
  445. struct display_info_t {
  446. int bus;
  447. int addr;
  448. int pixfmt;
  449. int (*detect)(struct display_info_t const *dev);
  450. void (*enable)(struct display_info_t const *dev);
  451. struct fb_videomode mode;
  452. };
  453. static void disable_lvds(struct display_info_t const *dev)
  454. {
  455. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  456. clrbits_le32(&iomux->gpr[2], IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
  457. IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
  458. }
  459. static void do_enable_hdmi(struct display_info_t const *dev)
  460. {
  461. disable_lvds(dev);
  462. imx_enable_hdmi_phy();
  463. }
  464. static struct display_info_t const displays[] = {
  465. {
  466. .bus = -1,
  467. .addr = 0,
  468. .pixfmt = IPU_PIX_FMT_RGB666,
  469. .detect = NULL,
  470. .enable = NULL,
  471. .mode = {
  472. .name =
  473. "Hannstar-XGA",
  474. .refresh = 60,
  475. .xres = 1024,
  476. .yres = 768,
  477. .pixclock = 15385,
  478. .left_margin = 220,
  479. .right_margin = 40,
  480. .upper_margin = 21,
  481. .lower_margin = 7,
  482. .hsync_len = 60,
  483. .vsync_len = 10,
  484. .sync = FB_SYNC_EXT,
  485. .vmode = FB_VMODE_NONINTERLACED } },
  486. {
  487. .bus = -1,
  488. .addr = 0,
  489. .pixfmt = IPU_PIX_FMT_RGB24,
  490. .detect = NULL,
  491. .enable = do_enable_hdmi,
  492. .mode = {
  493. .name = "HDMI",
  494. .refresh = 60,
  495. .xres = 1024,
  496. .yres = 768,
  497. .pixclock = 15385,
  498. .left_margin = 220,
  499. .right_margin = 40,
  500. .upper_margin = 21,
  501. .lower_margin = 7,
  502. .hsync_len = 60,
  503. .vsync_len = 10,
  504. .sync = FB_SYNC_EXT,
  505. .vmode = FB_VMODE_NONINTERLACED } }
  506. };
  507. int board_video_skip(void)
  508. {
  509. int i;
  510. int ret;
  511. char const *panel = env_get("panel");
  512. if (!panel) {
  513. for (i = 0; i < ARRAY_SIZE(displays); i++) {
  514. struct display_info_t const *dev = displays + i;
  515. if (dev->detect && dev->detect(dev)) {
  516. panel = dev->mode.name;
  517. printf("auto-detected panel %s\n", panel);
  518. break;
  519. }
  520. }
  521. if (!panel) {
  522. panel = displays[0].mode.name;
  523. printf("No panel detected: default to %s\n", panel);
  524. i = 0;
  525. }
  526. } else {
  527. for (i = 0; i < ARRAY_SIZE(displays); i++) {
  528. if (!strcmp(panel, displays[i].mode.name))
  529. break;
  530. }
  531. }
  532. if (i < ARRAY_SIZE(displays)) {
  533. ret = ipuv3_fb_init(&displays[i].mode, 0, displays[i].pixfmt);
  534. if (!ret) {
  535. if (displays[i].enable)
  536. displays[i].enable(displays + i);
  537. printf("Display: %s (%ux%u)\n",
  538. displays[i].mode.name, displays[i].mode.xres,
  539. displays[i].mode.yres);
  540. } else
  541. printf("LCD %s cannot be configured: %d\n",
  542. displays[i].mode.name, ret);
  543. } else {
  544. printf("unsupported panel %s\n", panel);
  545. return -EINVAL;
  546. }
  547. return 0;
  548. }
  549. int ipu_displays_init(void)
  550. {
  551. return board_video_skip();
  552. }
  553. static void setup_display(void)
  554. {
  555. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  556. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  557. int reg;
  558. enable_ipu_clock();
  559. imx_setup_hdmi();
  560. /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
  561. setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK |
  562. MXC_CCM_CCGR3_LDB_DI1_MASK);
  563. /* set LDB0, LDB1 clk select to 011/011 */
  564. reg = readl(&mxc_ccm->cs2cdr);
  565. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
  566. MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  567. reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
  568. (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  569. writel(reg, &mxc_ccm->cs2cdr);
  570. setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV |
  571. MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV);
  572. setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 <<
  573. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET |
  574. CHSCCDR_CLK_SEL_LDB_DI0 <<
  575. MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
  576. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  577. | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
  578. | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  579. | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  580. | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
  581. | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  582. | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
  583. | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
  584. | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
  585. writel(reg, &iomux->gpr[2]);
  586. reg = readl(&iomux->gpr[3]);
  587. reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
  588. IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) |
  589. (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
  590. IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
  591. writel(reg, &iomux->gpr[3]);
  592. }
  593. /*
  594. * Do not overwrite the console
  595. * Use always serial for U-Boot console
  596. */
  597. int overwrite_console(void)
  598. {
  599. return 1;
  600. }
  601. int board_early_init_f(void)
  602. {
  603. setup_iomux_uart();
  604. #ifdef CONFIG_MXC_SPI
  605. setup_spi();
  606. #endif
  607. return 0;
  608. }
  609. int board_init(void)
  610. {
  611. /* address of boot parameters */
  612. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  613. if (is_mx6dq())
  614. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
  615. else
  616. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
  617. setup_display();
  618. #ifdef CONFIG_SATA
  619. setup_sata();
  620. #endif
  621. return 0;
  622. }
  623. int checkboard(void)
  624. {
  625. char *type = "unknown";
  626. if (is_cpu_type(MXC_CPU_MX6Q))
  627. type = "Quad";
  628. else if (is_cpu_type(MXC_CPU_MX6D))
  629. type = "Dual";
  630. else if (is_cpu_type(MXC_CPU_MX6DL))
  631. type = "Dual-Lite";
  632. else if (is_cpu_type(MXC_CPU_MX6SOLO))
  633. type = "Solo";
  634. printf("Board: conga-QMX6 %s\n", type);
  635. return 0;
  636. }
  637. #ifdef CONFIG_MXC_SPI
  638. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  639. {
  640. return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -EINVAL;
  641. }
  642. #endif
  643. #ifdef CONFIG_CMD_BMODE
  644. static const struct boot_mode board_boot_modes[] = {
  645. /* 4 bit bus width */
  646. {"mmc0", MAKE_CFGVAL(0x50, 0x20, 0x00, 0x00)},
  647. {"mmc1", MAKE_CFGVAL(0x50, 0x38, 0x00, 0x00)},
  648. {NULL, 0},
  649. };
  650. #endif
  651. int misc_init_r(void)
  652. {
  653. #ifdef CONFIG_CMD_BMODE
  654. add_board_boot_modes(board_boot_modes);
  655. #endif
  656. return 0;
  657. }
  658. int board_late_init(void)
  659. {
  660. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  661. if (is_mx6dq())
  662. env_set("board_rev", "MX6Q");
  663. else
  664. env_set("board_rev", "MX6DL");
  665. #endif
  666. return 0;
  667. }
  668. #ifdef CONFIG_SPL_BUILD
  669. #include <asm/arch/mx6-ddr.h>
  670. #include <spl.h>
  671. #include <linux/libfdt.h>
  672. #include <spi_flash.h>
  673. #include <spi.h>
  674. const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
  675. .dram_sdclk_0 = 0x00000030,
  676. .dram_sdclk_1 = 0x00000030,
  677. .dram_cas = 0x00000030,
  678. .dram_ras = 0x00000030,
  679. .dram_reset = 0x00000030,
  680. .dram_sdcke0 = 0x00003000,
  681. .dram_sdcke1 = 0x00003000,
  682. .dram_sdba2 = 0x00000000,
  683. .dram_sdodt0 = 0x00000030,
  684. .dram_sdodt1 = 0x00000030,
  685. .dram_sdqs0 = 0x00000030,
  686. .dram_sdqs1 = 0x00000030,
  687. .dram_sdqs2 = 0x00000030,
  688. .dram_sdqs3 = 0x00000030,
  689. .dram_sdqs4 = 0x00000030,
  690. .dram_sdqs5 = 0x00000030,
  691. .dram_sdqs6 = 0x00000030,
  692. .dram_sdqs7 = 0x00000030,
  693. .dram_dqm0 = 0x00000030,
  694. .dram_dqm1 = 0x00000030,
  695. .dram_dqm2 = 0x00000030,
  696. .dram_dqm3 = 0x00000030,
  697. .dram_dqm4 = 0x00000030,
  698. .dram_dqm5 = 0x00000030,
  699. .dram_dqm6 = 0x00000030,
  700. .dram_dqm7 = 0x00000030,
  701. };
  702. static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
  703. .dram_sdclk_0 = 0x00000030,
  704. .dram_sdclk_1 = 0x00000030,
  705. .dram_cas = 0x00000030,
  706. .dram_ras = 0x00000030,
  707. .dram_reset = 0x00000030,
  708. .dram_sdcke0 = 0x00003000,
  709. .dram_sdcke1 = 0x00003000,
  710. .dram_sdba2 = 0x00000000,
  711. .dram_sdodt0 = 0x00000030,
  712. .dram_sdodt1 = 0x00000030,
  713. .dram_sdqs0 = 0x00000030,
  714. .dram_sdqs1 = 0x00000030,
  715. .dram_sdqs2 = 0x00000030,
  716. .dram_sdqs3 = 0x00000030,
  717. .dram_sdqs4 = 0x00000030,
  718. .dram_sdqs5 = 0x00000030,
  719. .dram_sdqs6 = 0x00000030,
  720. .dram_sdqs7 = 0x00000030,
  721. .dram_dqm0 = 0x00000030,
  722. .dram_dqm1 = 0x00000030,
  723. .dram_dqm2 = 0x00000030,
  724. .dram_dqm3 = 0x00000030,
  725. .dram_dqm4 = 0x00000030,
  726. .dram_dqm5 = 0x00000030,
  727. .dram_dqm6 = 0x00000030,
  728. .dram_dqm7 = 0x00000030,
  729. };
  730. const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
  731. .grp_ddr_type = 0x000C0000,
  732. .grp_ddrmode_ctl = 0x00020000,
  733. .grp_ddrpke = 0x00000000,
  734. .grp_addds = 0x00000030,
  735. .grp_ctlds = 0x00000030,
  736. .grp_ddrmode = 0x00020000,
  737. .grp_b0ds = 0x00000030,
  738. .grp_b1ds = 0x00000030,
  739. .grp_b2ds = 0x00000030,
  740. .grp_b3ds = 0x00000030,
  741. .grp_b4ds = 0x00000030,
  742. .grp_b5ds = 0x00000030,
  743. .grp_b6ds = 0x00000030,
  744. .grp_b7ds = 0x00000030,
  745. };
  746. static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
  747. .grp_ddr_type = 0x000c0000,
  748. .grp_ddrmode_ctl = 0x00020000,
  749. .grp_ddrpke = 0x00000000,
  750. .grp_addds = 0x00000030,
  751. .grp_ctlds = 0x00000030,
  752. .grp_ddrmode = 0x00020000,
  753. .grp_b0ds = 0x00000030,
  754. .grp_b1ds = 0x00000030,
  755. .grp_b2ds = 0x00000030,
  756. .grp_b3ds = 0x00000030,
  757. .grp_b4ds = 0x00000030,
  758. .grp_b5ds = 0x00000030,
  759. .grp_b6ds = 0x00000030,
  760. .grp_b7ds = 0x00000030,
  761. };
  762. const struct mx6_mmdc_calibration mx6q_mmcd_calib = {
  763. .p0_mpwldectrl0 = 0x0016001A,
  764. .p0_mpwldectrl1 = 0x0023001C,
  765. .p1_mpwldectrl0 = 0x0028003A,
  766. .p1_mpwldectrl1 = 0x001F002C,
  767. .p0_mpdgctrl0 = 0x43440354,
  768. .p0_mpdgctrl1 = 0x033C033C,
  769. .p1_mpdgctrl0 = 0x43300368,
  770. .p1_mpdgctrl1 = 0x03500330,
  771. .p0_mprddlctl = 0x3228242E,
  772. .p1_mprddlctl = 0x2C2C2636,
  773. .p0_mpwrdlctl = 0x36323A38,
  774. .p1_mpwrdlctl = 0x42324440,
  775. };
  776. const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
  777. .p0_mpwldectrl0 = 0x00080016,
  778. .p0_mpwldectrl1 = 0x001D0016,
  779. .p1_mpwldectrl0 = 0x0018002C,
  780. .p1_mpwldectrl1 = 0x000D001D,
  781. .p0_mpdgctrl0 = 0x43200334,
  782. .p0_mpdgctrl1 = 0x0320031C,
  783. .p1_mpdgctrl0 = 0x0344034C,
  784. .p1_mpdgctrl1 = 0x03380314,
  785. .p0_mprddlctl = 0x3E36383A,
  786. .p1_mprddlctl = 0x38363240,
  787. .p0_mpwrdlctl = 0x36364238,
  788. .p1_mpwrdlctl = 0x4230423E,
  789. };
  790. static const struct mx6_mmdc_calibration mx6s_mmcd_calib = {
  791. .p0_mpwldectrl0 = 0x00480049,
  792. .p0_mpwldectrl1 = 0x00410044,
  793. .p0_mpdgctrl0 = 0x42480248,
  794. .p0_mpdgctrl1 = 0x023C023C,
  795. .p0_mprddlctl = 0x40424644,
  796. .p0_mpwrdlctl = 0x34323034,
  797. };
  798. const struct mx6_mmdc_calibration mx6dl_mmcd_calib = {
  799. .p0_mpwldectrl0 = 0x0043004B,
  800. .p0_mpwldectrl1 = 0x003A003E,
  801. .p1_mpwldectrl0 = 0x0047004F,
  802. .p1_mpwldectrl1 = 0x004E0061,
  803. .p0_mpdgctrl0 = 0x42500250,
  804. .p0_mpdgctrl1 = 0x0238023C,
  805. .p1_mpdgctrl0 = 0x42640264,
  806. .p1_mpdgctrl1 = 0x02500258,
  807. .p0_mprddlctl = 0x40424846,
  808. .p1_mprddlctl = 0x46484842,
  809. .p0_mpwrdlctl = 0x38382C30,
  810. .p1_mpwrdlctl = 0x34343430,
  811. };
  812. static struct mx6_ddr3_cfg mem_ddr_2g = {
  813. .mem_speed = 1600,
  814. .density = 2,
  815. .width = 16,
  816. .banks = 8,
  817. .rowaddr = 14,
  818. .coladdr = 10,
  819. .pagesz = 2,
  820. .trcd = 1310,
  821. .trcmin = 4875,
  822. .trasmin = 3500,
  823. };
  824. static struct mx6_ddr3_cfg mem_ddr_4g = {
  825. .mem_speed = 1600,
  826. .density = 4,
  827. .width = 16,
  828. .banks = 8,
  829. .rowaddr = 15,
  830. .coladdr = 10,
  831. .pagesz = 2,
  832. .trcd = 1310,
  833. .trcmin = 4875,
  834. .trasmin = 3500,
  835. };
  836. static void ccgr_init(void)
  837. {
  838. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  839. writel(0x00C03F3F, &ccm->CCGR0);
  840. writel(0x0030FC03, &ccm->CCGR1);
  841. writel(0x0FFFC000, &ccm->CCGR2);
  842. writel(0x3FF00000, &ccm->CCGR3);
  843. writel(0x00FFF300, &ccm->CCGR4);
  844. writel(0x0F0000C3, &ccm->CCGR5);
  845. writel(0x000003FF, &ccm->CCGR6);
  846. }
  847. /* Define a minimal structure so that the part number can be read via SPL */
  848. struct mfgdata {
  849. unsigned char tsize;
  850. /* size of checksummed part in bytes */
  851. unsigned char ckcnt;
  852. /* checksum corrected byte */
  853. unsigned char cksum;
  854. /* decimal serial number, packed BCD */
  855. unsigned char serial[6];
  856. /* part number, right justified, ASCII */
  857. unsigned char pn[16];
  858. };
  859. static void conv_ascii(unsigned char *dst, unsigned char *src, int len)
  860. {
  861. int remain = len;
  862. unsigned char *sptr = src;
  863. unsigned char *dptr = dst;
  864. while (remain) {
  865. if (*sptr) {
  866. *dptr = *sptr;
  867. dptr++;
  868. }
  869. sptr++;
  870. remain--;
  871. }
  872. *dptr = 0x0;
  873. }
  874. #define CFG_MFG_ADDR_OFFSET (spi->size - SZ_16K)
  875. static bool is_2gb(void)
  876. {
  877. struct spi_flash *spi;
  878. int ret;
  879. char buf[sizeof(struct mfgdata)];
  880. struct mfgdata *data = (struct mfgdata *)buf;
  881. unsigned char outbuf[32];
  882. spi = spi_flash_probe(CONFIG_ENV_SPI_BUS,
  883. CONFIG_ENV_SPI_CS,
  884. CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
  885. ret = spi_flash_read(spi, CFG_MFG_ADDR_OFFSET, sizeof(struct mfgdata),
  886. buf);
  887. if (ret)
  888. return false;
  889. /* Congatec Part Numbers 104 and 105 have 2GiB of RAM */
  890. conv_ascii(outbuf, data->pn, sizeof(data->pn));
  891. if (!memcmp(outbuf, "016104", 6) || !memcmp(outbuf, "016105", 6))
  892. return true;
  893. else
  894. return false;
  895. }
  896. static void spl_dram_init(int width)
  897. {
  898. struct mx6_ddr_sysinfo sysinfo = {
  899. /* width of data bus:0=16,1=32,2=64 */
  900. .dsize = width / 32,
  901. /* config for full 4GB range so that get_mem_size() works */
  902. .cs_density = 32, /* 32Gb per CS */
  903. /* single chip select */
  904. .ncs = 1,
  905. .cs1_mirror = 0,
  906. .rtt_wr = 2,
  907. .rtt_nom = 2,
  908. .walat = 0,
  909. .ralat = 5,
  910. .mif3_mode = 3,
  911. .bi_on = 1,
  912. .sde_to_rst = 0x0d,
  913. .rst_to_cke = 0x20,
  914. .refsel = 1, /* Refresh cycles at 32KHz */
  915. .refr = 7, /* 8 refresh commands per refresh cycle */
  916. };
  917. if (is_cpu_type(MXC_CPU_MX6Q) && is_2gb()) {
  918. mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
  919. mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
  920. return;
  921. }
  922. if (is_mx6dq()) {
  923. mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
  924. mx6_dram_cfg(&sysinfo, &mx6q_mmcd_calib, &mem_ddr_2g);
  925. } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
  926. sysinfo.walat = 1;
  927. mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
  928. mx6_dram_cfg(&sysinfo, &mx6s_mmcd_calib, &mem_ddr_4g);
  929. } else if (is_cpu_type(MXC_CPU_MX6DL)) {
  930. sysinfo.walat = 1;
  931. mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
  932. mx6_dram_cfg(&sysinfo, &mx6dl_mmcd_calib, &mem_ddr_2g);
  933. }
  934. }
  935. void board_init_f(ulong dummy)
  936. {
  937. /* setup AIPS and disable watchdog */
  938. arch_cpu_init();
  939. ccgr_init();
  940. gpr_init();
  941. /* iomux and setup of i2c */
  942. board_early_init_f();
  943. /* setup GP timer */
  944. timer_init();
  945. /* UART clocks enabled and gd valid - init serial console */
  946. preloader_console_init();
  947. /* Needed for malloc() to work in SPL prior to board_init_r() */
  948. spl_init();
  949. /* DDR initialization */
  950. if (is_cpu_type(MXC_CPU_MX6SOLO))
  951. spl_dram_init(32);
  952. else
  953. spl_dram_init(64);
  954. /* Clear the BSS. */
  955. memset(__bss_start, 0, __bss_end - __bss_start);
  956. /* load/boot image from boot device */
  957. board_init_r(NULL, 0);
  958. }
  959. #endif