Kconfig 32 KB

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  1. menu "mpc85xx CPU"
  2. depends on MPC85xx
  3. config SYS_CPU
  4. default "mpc85xx"
  5. config CMD_ERRATA
  6. bool "Enable the 'errata' command"
  7. depends on MPC85xx
  8. default y
  9. help
  10. This enables the 'errata' command which displays a list of errata
  11. work-arounds which are enabled for the current board.
  12. choice
  13. prompt "Target select"
  14. optional
  15. config TARGET_SBC8548
  16. bool "Support sbc8548"
  17. select ARCH_MPC8548
  18. config TARGET_SOCRATES
  19. bool "Support socrates"
  20. select ARCH_MPC8544
  21. config TARGET_P3041DS
  22. bool "Support P3041DS"
  23. select PHYS_64BIT
  24. select ARCH_P3041
  25. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  26. imply CMD_SATA
  27. imply PANIC_HANG
  28. config TARGET_P4080DS
  29. bool "Support P4080DS"
  30. select PHYS_64BIT
  31. select ARCH_P4080
  32. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  33. imply CMD_SATA
  34. imply PANIC_HANG
  35. config TARGET_P5020DS
  36. bool "Support P5020DS"
  37. select PHYS_64BIT
  38. select ARCH_P5020
  39. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  40. imply CMD_SATA
  41. imply PANIC_HANG
  42. config TARGET_P5040DS
  43. bool "Support P5040DS"
  44. select PHYS_64BIT
  45. select ARCH_P5040
  46. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  47. imply CMD_SATA
  48. imply PANIC_HANG
  49. config TARGET_MPC8541CDS
  50. bool "Support MPC8541CDS"
  51. select ARCH_MPC8541
  52. config TARGET_MPC8544DS
  53. bool "Support MPC8544DS"
  54. select ARCH_MPC8544
  55. imply PANIC_HANG
  56. config TARGET_MPC8548CDS
  57. bool "Support MPC8548CDS"
  58. select ARCH_MPC8548
  59. config TARGET_MPC8555CDS
  60. bool "Support MPC8555CDS"
  61. select ARCH_MPC8555
  62. config TARGET_MPC8568MDS
  63. bool "Support MPC8568MDS"
  64. select ARCH_MPC8568
  65. config TARGET_MPC8569MDS
  66. bool "Support MPC8569MDS"
  67. select ARCH_MPC8569
  68. config TARGET_MPC8572DS
  69. bool "Support MPC8572DS"
  70. select ARCH_MPC8572
  71. # Use DDR3 controller with DDR2 DIMMs on this board
  72. select SYS_FSL_DDRC_GEN3
  73. imply SCSI
  74. imply PANIC_HANG
  75. config TARGET_P1010RDB_PA
  76. bool "Support P1010RDB_PA"
  77. select ARCH_P1010
  78. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  79. select SUPPORT_SPL
  80. select SUPPORT_TPL
  81. imply CMD_EEPROM
  82. imply CMD_SATA
  83. imply PANIC_HANG
  84. config TARGET_P1010RDB_PB
  85. bool "Support P1010RDB_PB"
  86. select ARCH_P1010
  87. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  88. select SUPPORT_SPL
  89. select SUPPORT_TPL
  90. imply CMD_EEPROM
  91. imply CMD_SATA
  92. imply PANIC_HANG
  93. config TARGET_P1023RDB
  94. bool "Support P1023RDB"
  95. select ARCH_P1023
  96. select FSL_DDR_INTERACTIVE
  97. imply CMD_EEPROM
  98. imply PANIC_HANG
  99. config TARGET_P1020MBG
  100. bool "Support P1020MBG-PC"
  101. select SUPPORT_SPL
  102. select SUPPORT_TPL
  103. select ARCH_P1020
  104. imply CMD_EEPROM
  105. imply CMD_SATA
  106. imply PANIC_HANG
  107. config TARGET_P1020RDB_PC
  108. bool "Support P1020RDB-PC"
  109. select SUPPORT_SPL
  110. select SUPPORT_TPL
  111. select ARCH_P1020
  112. imply CMD_EEPROM
  113. imply CMD_SATA
  114. imply PANIC_HANG
  115. config TARGET_P1020RDB_PD
  116. bool "Support P1020RDB-PD"
  117. select SUPPORT_SPL
  118. select SUPPORT_TPL
  119. select ARCH_P1020
  120. imply CMD_EEPROM
  121. imply CMD_SATA
  122. imply PANIC_HANG
  123. config TARGET_P1020UTM
  124. bool "Support P1020UTM"
  125. select SUPPORT_SPL
  126. select SUPPORT_TPL
  127. select ARCH_P1020
  128. imply CMD_EEPROM
  129. imply CMD_SATA
  130. imply PANIC_HANG
  131. config TARGET_P1021RDB
  132. bool "Support P1021RDB"
  133. select SUPPORT_SPL
  134. select SUPPORT_TPL
  135. select ARCH_P1021
  136. imply CMD_EEPROM
  137. imply CMD_SATA
  138. imply PANIC_HANG
  139. config TARGET_P1024RDB
  140. bool "Support P1024RDB"
  141. select SUPPORT_SPL
  142. select SUPPORT_TPL
  143. select ARCH_P1024
  144. imply CMD_EEPROM
  145. imply CMD_SATA
  146. imply PANIC_HANG
  147. config TARGET_P1025RDB
  148. bool "Support P1025RDB"
  149. select SUPPORT_SPL
  150. select SUPPORT_TPL
  151. select ARCH_P1025
  152. imply CMD_EEPROM
  153. imply CMD_SATA
  154. imply SATA_SIL
  155. config TARGET_P2020RDB
  156. bool "Support P2020RDB-PC"
  157. select SUPPORT_SPL
  158. select SUPPORT_TPL
  159. select ARCH_P2020
  160. imply CMD_EEPROM
  161. imply CMD_SATA
  162. imply SATA_SIL
  163. config TARGET_P2041RDB
  164. bool "Support P2041RDB"
  165. select ARCH_P2041
  166. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  167. select PHYS_64BIT
  168. imply CMD_SATA
  169. imply FSL_SATA
  170. config TARGET_QEMU_PPCE500
  171. bool "Support qemu-ppce500"
  172. select ARCH_QEMU_E500
  173. select PHYS_64BIT
  174. config TARGET_T1023RDB
  175. bool "Support T1023RDB"
  176. select ARCH_T1023
  177. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  178. select SUPPORT_SPL
  179. select PHYS_64BIT
  180. select FSL_DDR_INTERACTIVE
  181. imply CMD_EEPROM
  182. imply PANIC_HANG
  183. config TARGET_T1024RDB
  184. bool "Support T1024RDB"
  185. select ARCH_T1024
  186. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  187. select SUPPORT_SPL
  188. select PHYS_64BIT
  189. select FSL_DDR_INTERACTIVE
  190. imply CMD_EEPROM
  191. imply PANIC_HANG
  192. config TARGET_T1040RDB
  193. bool "Support T1040RDB"
  194. select ARCH_T1040
  195. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  196. select SUPPORT_SPL
  197. select PHYS_64BIT
  198. imply CMD_SATA
  199. imply PANIC_HANG
  200. config TARGET_T1040D4RDB
  201. bool "Support T1040D4RDB"
  202. select ARCH_T1040
  203. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  204. select SUPPORT_SPL
  205. select PHYS_64BIT
  206. imply CMD_SATA
  207. imply PANIC_HANG
  208. config TARGET_T1042RDB
  209. bool "Support T1042RDB"
  210. select ARCH_T1042
  211. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  212. select SUPPORT_SPL
  213. select PHYS_64BIT
  214. imply CMD_SATA
  215. config TARGET_T1042D4RDB
  216. bool "Support T1042D4RDB"
  217. select ARCH_T1042
  218. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  219. select SUPPORT_SPL
  220. select PHYS_64BIT
  221. imply CMD_SATA
  222. imply PANIC_HANG
  223. config TARGET_T1042RDB_PI
  224. bool "Support T1042RDB_PI"
  225. select ARCH_T1042
  226. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  227. select SUPPORT_SPL
  228. select PHYS_64BIT
  229. imply CMD_SATA
  230. imply PANIC_HANG
  231. config TARGET_T2080QDS
  232. bool "Support T2080QDS"
  233. select ARCH_T2080
  234. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  235. select SUPPORT_SPL
  236. select PHYS_64BIT
  237. select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
  238. select FSL_DDR_INTERACTIVE
  239. imply CMD_SATA
  240. config TARGET_T2080RDB
  241. bool "Support T2080RDB"
  242. select ARCH_T2080
  243. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  244. select SUPPORT_SPL
  245. select PHYS_64BIT
  246. imply CMD_SATA
  247. imply PANIC_HANG
  248. config TARGET_T2081QDS
  249. bool "Support T2081QDS"
  250. select ARCH_T2081
  251. select SUPPORT_SPL
  252. select PHYS_64BIT
  253. select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
  254. select FSL_DDR_INTERACTIVE
  255. config TARGET_T4160RDB
  256. bool "Support T4160RDB"
  257. select ARCH_T4160
  258. select SUPPORT_SPL
  259. select PHYS_64BIT
  260. imply PANIC_HANG
  261. config TARGET_T4240RDB
  262. bool "Support T4240RDB"
  263. select ARCH_T4240
  264. select SUPPORT_SPL
  265. select PHYS_64BIT
  266. select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
  267. imply CMD_SATA
  268. imply PANIC_HANG
  269. config TARGET_CONTROLCENTERD
  270. bool "Support controlcenterd"
  271. select ARCH_P1022
  272. config TARGET_KMP204X
  273. bool "Support kmp204x"
  274. select VENDOR_KM
  275. config TARGET_XPEDITE520X
  276. bool "Support xpedite520x"
  277. select ARCH_MPC8548
  278. config TARGET_XPEDITE537X
  279. bool "Support xpedite537x"
  280. select ARCH_MPC8572
  281. # Use DDR3 controller with DDR2 DIMMs on this board
  282. select SYS_FSL_DDRC_GEN3
  283. config TARGET_XPEDITE550X
  284. bool "Support xpedite550x"
  285. select ARCH_P2020
  286. config TARGET_UCP1020
  287. bool "Support uCP1020"
  288. select ARCH_P1020
  289. imply CMD_SATA
  290. imply PANIC_HANG
  291. config TARGET_CYRUS_P5020
  292. bool "Support Varisys Cyrus P5020"
  293. select ARCH_P5020
  294. select PHYS_64BIT
  295. imply PANIC_HANG
  296. config TARGET_CYRUS_P5040
  297. bool "Support Varisys Cyrus P5040"
  298. select ARCH_P5040
  299. select PHYS_64BIT
  300. imply PANIC_HANG
  301. endchoice
  302. config ARCH_B4420
  303. bool
  304. select E500MC
  305. select E6500
  306. select FSL_LAW
  307. select SYS_FSL_DDR_VER_47
  308. select SYS_FSL_ERRATUM_A004477
  309. select SYS_FSL_ERRATUM_A005871
  310. select SYS_FSL_ERRATUM_A006379
  311. select SYS_FSL_ERRATUM_A006384
  312. select SYS_FSL_ERRATUM_A006475
  313. select SYS_FSL_ERRATUM_A006593
  314. select SYS_FSL_ERRATUM_A007075
  315. select SYS_FSL_ERRATUM_A007186
  316. select SYS_FSL_ERRATUM_A007212
  317. select SYS_FSL_ERRATUM_A009942
  318. select SYS_FSL_HAS_DDR3
  319. select SYS_FSL_HAS_SEC
  320. select SYS_FSL_QORIQ_CHASSIS2
  321. select SYS_FSL_SEC_BE
  322. select SYS_FSL_SEC_COMPAT_4
  323. select SYS_PPC64
  324. select FSL_IFC
  325. imply CMD_EEPROM
  326. imply CMD_NAND
  327. imply CMD_REGINFO
  328. config ARCH_B4860
  329. bool
  330. select E500MC
  331. select E6500
  332. select FSL_LAW
  333. select SYS_FSL_DDR_VER_47
  334. select SYS_FSL_ERRATUM_A004477
  335. select SYS_FSL_ERRATUM_A005871
  336. select SYS_FSL_ERRATUM_A006379
  337. select SYS_FSL_ERRATUM_A006384
  338. select SYS_FSL_ERRATUM_A006475
  339. select SYS_FSL_ERRATUM_A006593
  340. select SYS_FSL_ERRATUM_A007075
  341. select SYS_FSL_ERRATUM_A007186
  342. select SYS_FSL_ERRATUM_A007212
  343. select SYS_FSL_ERRATUM_A007907
  344. select SYS_FSL_ERRATUM_A009942
  345. select SYS_FSL_HAS_DDR3
  346. select SYS_FSL_HAS_SEC
  347. select SYS_FSL_QORIQ_CHASSIS2
  348. select SYS_FSL_SEC_BE
  349. select SYS_FSL_SEC_COMPAT_4
  350. select SYS_PPC64
  351. select FSL_IFC
  352. imply CMD_EEPROM
  353. imply CMD_NAND
  354. imply CMD_REGINFO
  355. config ARCH_BSC9131
  356. bool
  357. select FSL_LAW
  358. select SYS_FSL_DDR_VER_44
  359. select SYS_FSL_ERRATUM_A004477
  360. select SYS_FSL_ERRATUM_A005125
  361. select SYS_FSL_ERRATUM_ESDHC111
  362. select SYS_FSL_HAS_DDR3
  363. select SYS_FSL_HAS_SEC
  364. select SYS_FSL_SEC_BE
  365. select SYS_FSL_SEC_COMPAT_4
  366. select FSL_IFC
  367. imply CMD_EEPROM
  368. imply CMD_NAND
  369. imply CMD_REGINFO
  370. config ARCH_BSC9132
  371. bool
  372. select FSL_LAW
  373. select SYS_FSL_DDR_VER_46
  374. select SYS_FSL_ERRATUM_A004477
  375. select SYS_FSL_ERRATUM_A005125
  376. select SYS_FSL_ERRATUM_A005434
  377. select SYS_FSL_ERRATUM_ESDHC111
  378. select SYS_FSL_ERRATUM_I2C_A004447
  379. select SYS_FSL_ERRATUM_IFC_A002769
  380. select FSL_PCIE_RESET
  381. select SYS_FSL_HAS_DDR3
  382. select SYS_FSL_HAS_SEC
  383. select SYS_FSL_SEC_BE
  384. select SYS_FSL_SEC_COMPAT_4
  385. select SYS_PPC_E500_USE_DEBUG_TLB
  386. select FSL_IFC
  387. imply CMD_EEPROM
  388. imply CMD_MTDPARTS
  389. imply CMD_NAND
  390. imply CMD_PCI
  391. imply CMD_REGINFO
  392. config ARCH_C29X
  393. bool
  394. select FSL_LAW
  395. select SYS_FSL_DDR_VER_46
  396. select SYS_FSL_ERRATUM_A005125
  397. select SYS_FSL_ERRATUM_ESDHC111
  398. select FSL_PCIE_RESET
  399. select SYS_FSL_HAS_DDR3
  400. select SYS_FSL_HAS_SEC
  401. select SYS_FSL_SEC_BE
  402. select SYS_FSL_SEC_COMPAT_6
  403. select SYS_PPC_E500_USE_DEBUG_TLB
  404. select FSL_IFC
  405. imply CMD_NAND
  406. imply CMD_PCI
  407. imply CMD_REGINFO
  408. config ARCH_MPC8536
  409. bool
  410. select FSL_LAW
  411. select SYS_FSL_ERRATUM_A004508
  412. select SYS_FSL_ERRATUM_A005125
  413. select FSL_PCIE_RESET
  414. select SYS_FSL_HAS_DDR2
  415. select SYS_FSL_HAS_DDR3
  416. select SYS_FSL_HAS_SEC
  417. select SYS_FSL_SEC_BE
  418. select SYS_FSL_SEC_COMPAT_2
  419. select SYS_PPC_E500_USE_DEBUG_TLB
  420. select FSL_ELBC
  421. imply CMD_NAND
  422. imply CMD_SATA
  423. imply CMD_REGINFO
  424. config ARCH_MPC8540
  425. bool
  426. select FSL_LAW
  427. select SYS_FSL_HAS_DDR1
  428. config ARCH_MPC8541
  429. bool
  430. select FSL_LAW
  431. select SYS_FSL_HAS_DDR1
  432. select SYS_FSL_HAS_SEC
  433. select SYS_FSL_SEC_BE
  434. select SYS_FSL_SEC_COMPAT_2
  435. config ARCH_MPC8544
  436. bool
  437. select FSL_LAW
  438. select SYS_FSL_ERRATUM_A005125
  439. select FSL_PCIE_RESET
  440. select SYS_FSL_HAS_DDR2
  441. select SYS_FSL_HAS_SEC
  442. select SYS_FSL_SEC_BE
  443. select SYS_FSL_SEC_COMPAT_2
  444. select SYS_PPC_E500_USE_DEBUG_TLB
  445. select FSL_ELBC
  446. config ARCH_MPC8548
  447. bool
  448. select FSL_LAW
  449. select SYS_FSL_ERRATUM_A005125
  450. select SYS_FSL_ERRATUM_NMG_DDR120
  451. select SYS_FSL_ERRATUM_NMG_LBC103
  452. select SYS_FSL_ERRATUM_NMG_ETSEC129
  453. select SYS_FSL_ERRATUM_I2C_A004447
  454. select FSL_PCIE_RESET
  455. select SYS_FSL_HAS_DDR2
  456. select SYS_FSL_HAS_DDR1
  457. select SYS_FSL_HAS_SEC
  458. select SYS_FSL_SEC_BE
  459. select SYS_FSL_SEC_COMPAT_2
  460. select SYS_PPC_E500_USE_DEBUG_TLB
  461. imply CMD_REGINFO
  462. config ARCH_MPC8555
  463. bool
  464. select FSL_LAW
  465. select SYS_FSL_HAS_DDR1
  466. select SYS_FSL_HAS_SEC
  467. select SYS_FSL_SEC_BE
  468. select SYS_FSL_SEC_COMPAT_2
  469. config ARCH_MPC8560
  470. bool
  471. select FSL_LAW
  472. select SYS_FSL_HAS_DDR1
  473. config ARCH_MPC8568
  474. bool
  475. select FSL_LAW
  476. select FSL_PCIE_RESET
  477. select SYS_FSL_HAS_DDR2
  478. select SYS_FSL_HAS_SEC
  479. select SYS_FSL_SEC_BE
  480. select SYS_FSL_SEC_COMPAT_2
  481. config ARCH_MPC8569
  482. bool
  483. select FSL_LAW
  484. select SYS_FSL_ERRATUM_A004508
  485. select SYS_FSL_ERRATUM_A005125
  486. select FSL_PCIE_RESET
  487. select SYS_FSL_HAS_DDR3
  488. select SYS_FSL_HAS_SEC
  489. select SYS_FSL_SEC_BE
  490. select SYS_FSL_SEC_COMPAT_2
  491. select FSL_ELBC
  492. imply CMD_NAND
  493. config ARCH_MPC8572
  494. bool
  495. select FSL_LAW
  496. select SYS_FSL_ERRATUM_A004508
  497. select SYS_FSL_ERRATUM_A005125
  498. select SYS_FSL_ERRATUM_DDR_115
  499. select SYS_FSL_ERRATUM_DDR111_DDR134
  500. select FSL_PCIE_RESET
  501. select SYS_FSL_HAS_DDR2
  502. select SYS_FSL_HAS_DDR3
  503. select SYS_FSL_HAS_SEC
  504. select SYS_FSL_SEC_BE
  505. select SYS_FSL_SEC_COMPAT_2
  506. select SYS_PPC_E500_USE_DEBUG_TLB
  507. select FSL_ELBC
  508. imply CMD_NAND
  509. config ARCH_P1010
  510. bool
  511. select FSL_LAW
  512. select SYS_FSL_ERRATUM_A004477
  513. select SYS_FSL_ERRATUM_A004508
  514. select SYS_FSL_ERRATUM_A005125
  515. select SYS_FSL_ERRATUM_A005275
  516. select SYS_FSL_ERRATUM_A006261
  517. select SYS_FSL_ERRATUM_A007075
  518. select SYS_FSL_ERRATUM_ESDHC111
  519. select SYS_FSL_ERRATUM_I2C_A004447
  520. select SYS_FSL_ERRATUM_IFC_A002769
  521. select SYS_FSL_ERRATUM_P1010_A003549
  522. select SYS_FSL_ERRATUM_SEC_A003571
  523. select SYS_FSL_ERRATUM_IFC_A003399
  524. select FSL_PCIE_RESET
  525. select SYS_FSL_HAS_DDR3
  526. select SYS_FSL_HAS_SEC
  527. select SYS_FSL_SEC_BE
  528. select SYS_FSL_SEC_COMPAT_4
  529. select SYS_PPC_E500_USE_DEBUG_TLB
  530. select FSL_IFC
  531. imply CMD_EEPROM
  532. imply CMD_MTDPARTS
  533. imply CMD_NAND
  534. imply CMD_SATA
  535. imply CMD_PCI
  536. imply CMD_REGINFO
  537. imply FSL_SATA
  538. config ARCH_P1011
  539. bool
  540. select FSL_LAW
  541. select SYS_FSL_ERRATUM_A004508
  542. select SYS_FSL_ERRATUM_A005125
  543. select SYS_FSL_ERRATUM_ELBC_A001
  544. select SYS_FSL_ERRATUM_ESDHC111
  545. select FSL_PCIE_DISABLE_ASPM
  546. select SYS_FSL_HAS_DDR3
  547. select SYS_FSL_HAS_SEC
  548. select SYS_FSL_SEC_BE
  549. select SYS_FSL_SEC_COMPAT_2
  550. select SYS_PPC_E500_USE_DEBUG_TLB
  551. select FSL_ELBC
  552. config ARCH_P1020
  553. bool
  554. select FSL_LAW
  555. select SYS_FSL_ERRATUM_A004508
  556. select SYS_FSL_ERRATUM_A005125
  557. select SYS_FSL_ERRATUM_ELBC_A001
  558. select SYS_FSL_ERRATUM_ESDHC111
  559. select FSL_PCIE_DISABLE_ASPM
  560. select FSL_PCIE_RESET
  561. select SYS_FSL_HAS_DDR3
  562. select SYS_FSL_HAS_SEC
  563. select SYS_FSL_SEC_BE
  564. select SYS_FSL_SEC_COMPAT_2
  565. select SYS_PPC_E500_USE_DEBUG_TLB
  566. select FSL_ELBC
  567. imply CMD_NAND
  568. imply CMD_SATA
  569. imply CMD_PCI
  570. imply CMD_REGINFO
  571. imply SATA_SIL
  572. config ARCH_P1021
  573. bool
  574. select FSL_LAW
  575. select SYS_FSL_ERRATUM_A004508
  576. select SYS_FSL_ERRATUM_A005125
  577. select SYS_FSL_ERRATUM_ELBC_A001
  578. select SYS_FSL_ERRATUM_ESDHC111
  579. select FSL_PCIE_DISABLE_ASPM
  580. select FSL_PCIE_RESET
  581. select SYS_FSL_HAS_DDR3
  582. select SYS_FSL_HAS_SEC
  583. select SYS_FSL_SEC_BE
  584. select SYS_FSL_SEC_COMPAT_2
  585. select SYS_PPC_E500_USE_DEBUG_TLB
  586. select FSL_ELBC
  587. imply CMD_REGINFO
  588. imply CMD_NAND
  589. imply CMD_SATA
  590. imply CMD_REGINFO
  591. imply SATA_SIL
  592. config ARCH_P1022
  593. bool
  594. select FSL_LAW
  595. select SYS_FSL_ERRATUM_A004477
  596. select SYS_FSL_ERRATUM_A004508
  597. select SYS_FSL_ERRATUM_A005125
  598. select SYS_FSL_ERRATUM_ELBC_A001
  599. select SYS_FSL_ERRATUM_ESDHC111
  600. select SYS_FSL_ERRATUM_SATA_A001
  601. select FSL_PCIE_RESET
  602. select SYS_FSL_HAS_DDR3
  603. select SYS_FSL_HAS_SEC
  604. select SYS_FSL_SEC_BE
  605. select SYS_FSL_SEC_COMPAT_2
  606. select SYS_PPC_E500_USE_DEBUG_TLB
  607. select FSL_ELBC
  608. config ARCH_P1023
  609. bool
  610. select FSL_LAW
  611. select SYS_FSL_ERRATUM_A004508
  612. select SYS_FSL_ERRATUM_A005125
  613. select SYS_FSL_ERRATUM_I2C_A004447
  614. select FSL_PCIE_RESET
  615. select SYS_FSL_HAS_DDR3
  616. select SYS_FSL_HAS_SEC
  617. select SYS_FSL_SEC_BE
  618. select SYS_FSL_SEC_COMPAT_4
  619. select FSL_ELBC
  620. config ARCH_P1024
  621. bool
  622. select FSL_LAW
  623. select SYS_FSL_ERRATUM_A004508
  624. select SYS_FSL_ERRATUM_A005125
  625. select SYS_FSL_ERRATUM_ELBC_A001
  626. select SYS_FSL_ERRATUM_ESDHC111
  627. select FSL_PCIE_DISABLE_ASPM
  628. select FSL_PCIE_RESET
  629. select SYS_FSL_HAS_DDR3
  630. select SYS_FSL_HAS_SEC
  631. select SYS_FSL_SEC_BE
  632. select SYS_FSL_SEC_COMPAT_2
  633. select SYS_PPC_E500_USE_DEBUG_TLB
  634. select FSL_ELBC
  635. imply CMD_EEPROM
  636. imply CMD_NAND
  637. imply CMD_SATA
  638. imply CMD_PCI
  639. imply CMD_REGINFO
  640. imply SATA_SIL
  641. config ARCH_P1025
  642. bool
  643. select FSL_LAW
  644. select SYS_FSL_ERRATUM_A004508
  645. select SYS_FSL_ERRATUM_A005125
  646. select SYS_FSL_ERRATUM_ELBC_A001
  647. select SYS_FSL_ERRATUM_ESDHC111
  648. select FSL_PCIE_DISABLE_ASPM
  649. select FSL_PCIE_RESET
  650. select SYS_FSL_HAS_DDR3
  651. select SYS_FSL_HAS_SEC
  652. select SYS_FSL_SEC_BE
  653. select SYS_FSL_SEC_COMPAT_2
  654. select SYS_PPC_E500_USE_DEBUG_TLB
  655. select FSL_ELBC
  656. imply CMD_SATA
  657. imply CMD_REGINFO
  658. config ARCH_P2020
  659. bool
  660. select FSL_LAW
  661. select SYS_FSL_ERRATUM_A004477
  662. select SYS_FSL_ERRATUM_A004508
  663. select SYS_FSL_ERRATUM_A005125
  664. select SYS_FSL_ERRATUM_ESDHC111
  665. select SYS_FSL_ERRATUM_ESDHC_A001
  666. select FSL_PCIE_RESET
  667. select SYS_FSL_HAS_DDR3
  668. select SYS_FSL_HAS_SEC
  669. select SYS_FSL_SEC_BE
  670. select SYS_FSL_SEC_COMPAT_2
  671. select SYS_PPC_E500_USE_DEBUG_TLB
  672. select FSL_ELBC
  673. imply CMD_EEPROM
  674. imply CMD_NAND
  675. imply CMD_REGINFO
  676. config ARCH_P2041
  677. bool
  678. select E500MC
  679. select FSL_LAW
  680. select SYS_FSL_ERRATUM_A004510
  681. select SYS_FSL_ERRATUM_A004849
  682. select SYS_FSL_ERRATUM_A005275
  683. select SYS_FSL_ERRATUM_A006261
  684. select SYS_FSL_ERRATUM_CPU_A003999
  685. select SYS_FSL_ERRATUM_DDR_A003
  686. select SYS_FSL_ERRATUM_DDR_A003474
  687. select SYS_FSL_ERRATUM_ESDHC111
  688. select SYS_FSL_ERRATUM_I2C_A004447
  689. select SYS_FSL_ERRATUM_NMG_CPU_A011
  690. select SYS_FSL_ERRATUM_SRIO_A004034
  691. select SYS_FSL_ERRATUM_USB14
  692. select SYS_FSL_HAS_DDR3
  693. select SYS_FSL_HAS_SEC
  694. select SYS_FSL_QORIQ_CHASSIS1
  695. select SYS_FSL_SEC_BE
  696. select SYS_FSL_SEC_COMPAT_4
  697. select FSL_ELBC
  698. imply CMD_NAND
  699. config ARCH_P3041
  700. bool
  701. select E500MC
  702. select FSL_LAW
  703. select SYS_FSL_DDR_VER_44
  704. select SYS_FSL_ERRATUM_A004510
  705. select SYS_FSL_ERRATUM_A004849
  706. select SYS_FSL_ERRATUM_A005275
  707. select SYS_FSL_ERRATUM_A005812
  708. select SYS_FSL_ERRATUM_A006261
  709. select SYS_FSL_ERRATUM_CPU_A003999
  710. select SYS_FSL_ERRATUM_DDR_A003
  711. select SYS_FSL_ERRATUM_DDR_A003474
  712. select SYS_FSL_ERRATUM_ESDHC111
  713. select SYS_FSL_ERRATUM_I2C_A004447
  714. select SYS_FSL_ERRATUM_NMG_CPU_A011
  715. select SYS_FSL_ERRATUM_SRIO_A004034
  716. select SYS_FSL_ERRATUM_USB14
  717. select SYS_FSL_HAS_DDR3
  718. select SYS_FSL_HAS_SEC
  719. select SYS_FSL_QORIQ_CHASSIS1
  720. select SYS_FSL_SEC_BE
  721. select SYS_FSL_SEC_COMPAT_4
  722. select FSL_ELBC
  723. imply CMD_NAND
  724. imply CMD_SATA
  725. imply CMD_REGINFO
  726. imply FSL_SATA
  727. config ARCH_P4080
  728. bool
  729. select E500MC
  730. select FSL_LAW
  731. select SYS_FSL_DDR_VER_44
  732. select SYS_FSL_ERRATUM_A004510
  733. select SYS_FSL_ERRATUM_A004580
  734. select SYS_FSL_ERRATUM_A004849
  735. select SYS_FSL_ERRATUM_A005812
  736. select SYS_FSL_ERRATUM_A007075
  737. select SYS_FSL_ERRATUM_CPC_A002
  738. select SYS_FSL_ERRATUM_CPC_A003
  739. select SYS_FSL_ERRATUM_CPU_A003999
  740. select SYS_FSL_ERRATUM_DDR_A003
  741. select SYS_FSL_ERRATUM_DDR_A003474
  742. select SYS_FSL_ERRATUM_ELBC_A001
  743. select SYS_FSL_ERRATUM_ESDHC111
  744. select SYS_FSL_ERRATUM_ESDHC13
  745. select SYS_FSL_ERRATUM_ESDHC135
  746. select SYS_FSL_ERRATUM_I2C_A004447
  747. select SYS_FSL_ERRATUM_NMG_CPU_A011
  748. select SYS_FSL_ERRATUM_SRIO_A004034
  749. select SYS_P4080_ERRATUM_CPU22
  750. select SYS_P4080_ERRATUM_PCIE_A003
  751. select SYS_P4080_ERRATUM_SERDES8
  752. select SYS_P4080_ERRATUM_SERDES9
  753. select SYS_P4080_ERRATUM_SERDES_A001
  754. select SYS_P4080_ERRATUM_SERDES_A005
  755. select SYS_FSL_HAS_DDR3
  756. select SYS_FSL_HAS_SEC
  757. select SYS_FSL_QORIQ_CHASSIS1
  758. select SYS_FSL_SEC_BE
  759. select SYS_FSL_SEC_COMPAT_4
  760. select FSL_ELBC
  761. imply CMD_SATA
  762. imply CMD_REGINFO
  763. imply SATA_SIL
  764. config ARCH_P5020
  765. bool
  766. select E500MC
  767. select FSL_LAW
  768. select SYS_FSL_DDR_VER_44
  769. select SYS_FSL_ERRATUM_A004510
  770. select SYS_FSL_ERRATUM_A005275
  771. select SYS_FSL_ERRATUM_A006261
  772. select SYS_FSL_ERRATUM_DDR_A003
  773. select SYS_FSL_ERRATUM_DDR_A003474
  774. select SYS_FSL_ERRATUM_ESDHC111
  775. select SYS_FSL_ERRATUM_I2C_A004447
  776. select SYS_FSL_ERRATUM_SRIO_A004034
  777. select SYS_FSL_ERRATUM_USB14
  778. select SYS_FSL_HAS_DDR3
  779. select SYS_FSL_HAS_SEC
  780. select SYS_FSL_QORIQ_CHASSIS1
  781. select SYS_FSL_SEC_BE
  782. select SYS_FSL_SEC_COMPAT_4
  783. select SYS_PPC64
  784. select FSL_ELBC
  785. imply CMD_SATA
  786. imply CMD_REGINFO
  787. imply FSL_SATA
  788. config ARCH_P5040
  789. bool
  790. select E500MC
  791. select FSL_LAW
  792. select SYS_FSL_DDR_VER_44
  793. select SYS_FSL_ERRATUM_A004510
  794. select SYS_FSL_ERRATUM_A004699
  795. select SYS_FSL_ERRATUM_A005275
  796. select SYS_FSL_ERRATUM_A005812
  797. select SYS_FSL_ERRATUM_A006261
  798. select SYS_FSL_ERRATUM_DDR_A003
  799. select SYS_FSL_ERRATUM_DDR_A003474
  800. select SYS_FSL_ERRATUM_ESDHC111
  801. select SYS_FSL_ERRATUM_USB14
  802. select SYS_FSL_HAS_DDR3
  803. select SYS_FSL_HAS_SEC
  804. select SYS_FSL_QORIQ_CHASSIS1
  805. select SYS_FSL_SEC_BE
  806. select SYS_FSL_SEC_COMPAT_4
  807. select SYS_PPC64
  808. select FSL_ELBC
  809. imply CMD_SATA
  810. imply CMD_REGINFO
  811. imply FSL_SATA
  812. config ARCH_QEMU_E500
  813. bool
  814. config ARCH_T1023
  815. bool
  816. select E500MC
  817. select FSL_LAW
  818. select SYS_FSL_DDR_VER_50
  819. select SYS_FSL_ERRATUM_A008378
  820. select SYS_FSL_ERRATUM_A008109
  821. select SYS_FSL_ERRATUM_A009663
  822. select SYS_FSL_ERRATUM_A009942
  823. select SYS_FSL_ERRATUM_ESDHC111
  824. select SYS_FSL_HAS_DDR3
  825. select SYS_FSL_HAS_DDR4
  826. select SYS_FSL_HAS_SEC
  827. select SYS_FSL_QORIQ_CHASSIS2
  828. select SYS_FSL_SEC_BE
  829. select SYS_FSL_SEC_COMPAT_5
  830. select FSL_IFC
  831. imply CMD_EEPROM
  832. imply CMD_NAND
  833. imply CMD_REGINFO
  834. config ARCH_T1024
  835. bool
  836. select E500MC
  837. select FSL_LAW
  838. select SYS_FSL_DDR_VER_50
  839. select SYS_FSL_ERRATUM_A008378
  840. select SYS_FSL_ERRATUM_A008109
  841. select SYS_FSL_ERRATUM_A009663
  842. select SYS_FSL_ERRATUM_A009942
  843. select SYS_FSL_ERRATUM_ESDHC111
  844. select SYS_FSL_HAS_DDR3
  845. select SYS_FSL_HAS_DDR4
  846. select SYS_FSL_HAS_SEC
  847. select SYS_FSL_QORIQ_CHASSIS2
  848. select SYS_FSL_SEC_BE
  849. select SYS_FSL_SEC_COMPAT_5
  850. select FSL_IFC
  851. imply CMD_EEPROM
  852. imply CMD_NAND
  853. imply CMD_MTDPARTS
  854. imply CMD_REGINFO
  855. config ARCH_T1040
  856. bool
  857. select E500MC
  858. select FSL_LAW
  859. select SYS_FSL_DDR_VER_50
  860. select SYS_FSL_ERRATUM_A008044
  861. select SYS_FSL_ERRATUM_A008378
  862. select SYS_FSL_ERRATUM_A008109
  863. select SYS_FSL_ERRATUM_A009663
  864. select SYS_FSL_ERRATUM_A009942
  865. select SYS_FSL_ERRATUM_ESDHC111
  866. select SYS_FSL_HAS_DDR3
  867. select SYS_FSL_HAS_DDR4
  868. select SYS_FSL_HAS_SEC
  869. select SYS_FSL_QORIQ_CHASSIS2
  870. select SYS_FSL_SEC_BE
  871. select SYS_FSL_SEC_COMPAT_5
  872. select FSL_IFC
  873. imply CMD_MTDPARTS
  874. imply CMD_NAND
  875. imply CMD_SATA
  876. imply CMD_REGINFO
  877. imply FSL_SATA
  878. config ARCH_T1042
  879. bool
  880. select E500MC
  881. select FSL_LAW
  882. select SYS_FSL_DDR_VER_50
  883. select SYS_FSL_ERRATUM_A008044
  884. select SYS_FSL_ERRATUM_A008378
  885. select SYS_FSL_ERRATUM_A008109
  886. select SYS_FSL_ERRATUM_A009663
  887. select SYS_FSL_ERRATUM_A009942
  888. select SYS_FSL_ERRATUM_ESDHC111
  889. select SYS_FSL_HAS_DDR3
  890. select SYS_FSL_HAS_DDR4
  891. select SYS_FSL_HAS_SEC
  892. select SYS_FSL_QORIQ_CHASSIS2
  893. select SYS_FSL_SEC_BE
  894. select SYS_FSL_SEC_COMPAT_5
  895. select FSL_IFC
  896. imply CMD_MTDPARTS
  897. imply CMD_NAND
  898. imply CMD_SATA
  899. imply CMD_REGINFO
  900. imply FSL_SATA
  901. config ARCH_T2080
  902. bool
  903. select E500MC
  904. select E6500
  905. select FSL_LAW
  906. select SYS_FSL_DDR_VER_47
  907. select SYS_FSL_ERRATUM_A006379
  908. select SYS_FSL_ERRATUM_A006593
  909. select SYS_FSL_ERRATUM_A007186
  910. select SYS_FSL_ERRATUM_A007212
  911. select SYS_FSL_ERRATUM_A007815
  912. select SYS_FSL_ERRATUM_A007907
  913. select SYS_FSL_ERRATUM_A008109
  914. select SYS_FSL_ERRATUM_A009942
  915. select SYS_FSL_ERRATUM_ESDHC111
  916. select FSL_PCIE_RESET
  917. select SYS_FSL_HAS_DDR3
  918. select SYS_FSL_HAS_SEC
  919. select SYS_FSL_QORIQ_CHASSIS2
  920. select SYS_FSL_SEC_BE
  921. select SYS_FSL_SEC_COMPAT_4
  922. select SYS_PPC64
  923. select FSL_IFC
  924. imply CMD_SATA
  925. imply CMD_NAND
  926. imply CMD_REGINFO
  927. imply FSL_SATA
  928. config ARCH_T2081
  929. bool
  930. select E500MC
  931. select E6500
  932. select FSL_LAW
  933. select SYS_FSL_DDR_VER_47
  934. select SYS_FSL_ERRATUM_A006379
  935. select SYS_FSL_ERRATUM_A006593
  936. select SYS_FSL_ERRATUM_A007186
  937. select SYS_FSL_ERRATUM_A007212
  938. select SYS_FSL_ERRATUM_A009942
  939. select SYS_FSL_ERRATUM_ESDHC111
  940. select FSL_PCIE_RESET
  941. select SYS_FSL_HAS_DDR3
  942. select SYS_FSL_HAS_SEC
  943. select SYS_FSL_QORIQ_CHASSIS2
  944. select SYS_FSL_SEC_BE
  945. select SYS_FSL_SEC_COMPAT_4
  946. select SYS_PPC64
  947. select FSL_IFC
  948. imply CMD_NAND
  949. imply CMD_REGINFO
  950. config ARCH_T4160
  951. bool
  952. select E500MC
  953. select E6500
  954. select FSL_LAW
  955. select SYS_FSL_DDR_VER_47
  956. select SYS_FSL_ERRATUM_A004468
  957. select SYS_FSL_ERRATUM_A005871
  958. select SYS_FSL_ERRATUM_A006379
  959. select SYS_FSL_ERRATUM_A006593
  960. select SYS_FSL_ERRATUM_A007186
  961. select SYS_FSL_ERRATUM_A007798
  962. select SYS_FSL_ERRATUM_A009942
  963. select SYS_FSL_HAS_DDR3
  964. select SYS_FSL_HAS_SEC
  965. select SYS_FSL_QORIQ_CHASSIS2
  966. select SYS_FSL_SEC_BE
  967. select SYS_FSL_SEC_COMPAT_4
  968. select SYS_PPC64
  969. select FSL_IFC
  970. imply CMD_SATA
  971. imply CMD_NAND
  972. imply CMD_REGINFO
  973. imply FSL_SATA
  974. config ARCH_T4240
  975. bool
  976. select E500MC
  977. select E6500
  978. select FSL_LAW
  979. select SYS_FSL_DDR_VER_47
  980. select SYS_FSL_ERRATUM_A004468
  981. select SYS_FSL_ERRATUM_A005871
  982. select SYS_FSL_ERRATUM_A006261
  983. select SYS_FSL_ERRATUM_A006379
  984. select SYS_FSL_ERRATUM_A006593
  985. select SYS_FSL_ERRATUM_A007186
  986. select SYS_FSL_ERRATUM_A007798
  987. select SYS_FSL_ERRATUM_A007815
  988. select SYS_FSL_ERRATUM_A007907
  989. select SYS_FSL_ERRATUM_A008109
  990. select SYS_FSL_ERRATUM_A009942
  991. select SYS_FSL_HAS_DDR3
  992. select SYS_FSL_HAS_SEC
  993. select SYS_FSL_QORIQ_CHASSIS2
  994. select SYS_FSL_SEC_BE
  995. select SYS_FSL_SEC_COMPAT_4
  996. select SYS_PPC64
  997. select FSL_IFC
  998. imply CMD_SATA
  999. imply CMD_NAND
  1000. imply CMD_REGINFO
  1001. imply FSL_SATA
  1002. config MPC85XX_HAVE_RESET_VECTOR
  1003. bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
  1004. depends on MPC85xx
  1005. config BOOKE
  1006. bool
  1007. default y
  1008. config E500
  1009. bool
  1010. default y
  1011. help
  1012. Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
  1013. config E500MC
  1014. bool
  1015. imply CMD_PCI
  1016. help
  1017. Enble PowerPC E500MC core
  1018. config E6500
  1019. bool
  1020. help
  1021. Enable PowerPC E6500 core
  1022. config FSL_LAW
  1023. bool
  1024. help
  1025. Use Freescale common code for Local Access Window
  1026. config NXP_ESBC
  1027. bool "NXP_ESBC"
  1028. help
  1029. Enable Freescale Secure Boot feature. Normally selected
  1030. by defconfig. If unsure, do not change.
  1031. config MAX_CPUS
  1032. int "Maximum number of CPUs permitted for MPC85xx"
  1033. default 12 if ARCH_T4240
  1034. default 8 if ARCH_P4080 || \
  1035. ARCH_T4160
  1036. default 4 if ARCH_B4860 || \
  1037. ARCH_P2041 || \
  1038. ARCH_P3041 || \
  1039. ARCH_P5040 || \
  1040. ARCH_T1040 || \
  1041. ARCH_T1042 || \
  1042. ARCH_T2080 || \
  1043. ARCH_T2081
  1044. default 2 if ARCH_B4420 || \
  1045. ARCH_BSC9132 || \
  1046. ARCH_MPC8572 || \
  1047. ARCH_P1020 || \
  1048. ARCH_P1021 || \
  1049. ARCH_P1022 || \
  1050. ARCH_P1023 || \
  1051. ARCH_P1024 || \
  1052. ARCH_P1025 || \
  1053. ARCH_P2020 || \
  1054. ARCH_P5020 || \
  1055. ARCH_T1023 || \
  1056. ARCH_T1024
  1057. default 1
  1058. help
  1059. Set this number to the maximum number of possible CPUs in the SoC.
  1060. SoCs may have multiple clusters with each cluster may have multiple
  1061. ports. If some ports are reserved but higher ports are used for
  1062. cores, count the reserved ports. This will allocate enough memory
  1063. in spin table to properly handle all cores.
  1064. config SYS_CCSRBAR_DEFAULT
  1065. hex "Default CCSRBAR address"
  1066. default 0xff700000 if ARCH_BSC9131 || \
  1067. ARCH_BSC9132 || \
  1068. ARCH_C29X || \
  1069. ARCH_MPC8536 || \
  1070. ARCH_MPC8540 || \
  1071. ARCH_MPC8541 || \
  1072. ARCH_MPC8544 || \
  1073. ARCH_MPC8548 || \
  1074. ARCH_MPC8555 || \
  1075. ARCH_MPC8560 || \
  1076. ARCH_MPC8568 || \
  1077. ARCH_MPC8569 || \
  1078. ARCH_MPC8572 || \
  1079. ARCH_P1010 || \
  1080. ARCH_P1011 || \
  1081. ARCH_P1020 || \
  1082. ARCH_P1021 || \
  1083. ARCH_P1022 || \
  1084. ARCH_P1024 || \
  1085. ARCH_P1025 || \
  1086. ARCH_P2020
  1087. default 0xff600000 if ARCH_P1023
  1088. default 0xfe000000 if ARCH_B4420 || \
  1089. ARCH_B4860 || \
  1090. ARCH_P2041 || \
  1091. ARCH_P3041 || \
  1092. ARCH_P4080 || \
  1093. ARCH_P5020 || \
  1094. ARCH_P5040 || \
  1095. ARCH_T1023 || \
  1096. ARCH_T1024 || \
  1097. ARCH_T1040 || \
  1098. ARCH_T1042 || \
  1099. ARCH_T2080 || \
  1100. ARCH_T2081 || \
  1101. ARCH_T4160 || \
  1102. ARCH_T4240
  1103. default 0xe0000000 if ARCH_QEMU_E500
  1104. help
  1105. Default value of CCSRBAR comes from power-on-reset. It
  1106. is fixed on each SoC. Some SoCs can have different value
  1107. if changed by pre-boot regime. The value here must match
  1108. the current value in SoC. If not sure, do not change.
  1109. config SYS_FSL_ERRATUM_A004468
  1110. bool
  1111. config SYS_FSL_ERRATUM_A004477
  1112. bool
  1113. config SYS_FSL_ERRATUM_A004508
  1114. bool
  1115. config SYS_FSL_ERRATUM_A004580
  1116. bool
  1117. config SYS_FSL_ERRATUM_A004699
  1118. bool
  1119. config SYS_FSL_ERRATUM_A004849
  1120. bool
  1121. config SYS_FSL_ERRATUM_A004510
  1122. bool
  1123. config SYS_FSL_ERRATUM_A004510_SVR_REV
  1124. hex
  1125. depends on SYS_FSL_ERRATUM_A004510
  1126. default 0x20 if ARCH_P4080
  1127. default 0x10
  1128. config SYS_FSL_ERRATUM_A004510_SVR_REV2
  1129. hex
  1130. depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
  1131. default 0x11
  1132. config SYS_FSL_ERRATUM_A005125
  1133. bool
  1134. config SYS_FSL_ERRATUM_A005434
  1135. bool
  1136. config SYS_FSL_ERRATUM_A005812
  1137. bool
  1138. config SYS_FSL_ERRATUM_A005871
  1139. bool
  1140. config SYS_FSL_ERRATUM_A005275
  1141. bool
  1142. config SYS_FSL_ERRATUM_A006261
  1143. bool
  1144. config SYS_FSL_ERRATUM_A006379
  1145. bool
  1146. config SYS_FSL_ERRATUM_A006384
  1147. bool
  1148. config SYS_FSL_ERRATUM_A006475
  1149. bool
  1150. config SYS_FSL_ERRATUM_A006593
  1151. bool
  1152. config SYS_FSL_ERRATUM_A007075
  1153. bool
  1154. config SYS_FSL_ERRATUM_A007186
  1155. bool
  1156. config SYS_FSL_ERRATUM_A007212
  1157. bool
  1158. config SYS_FSL_ERRATUM_A007815
  1159. bool
  1160. config SYS_FSL_ERRATUM_A007798
  1161. bool
  1162. config SYS_FSL_ERRATUM_A007907
  1163. bool
  1164. config SYS_FSL_ERRATUM_A008044
  1165. bool
  1166. config SYS_FSL_ERRATUM_CPC_A002
  1167. bool
  1168. config SYS_FSL_ERRATUM_CPC_A003
  1169. bool
  1170. config SYS_FSL_ERRATUM_CPU_A003999
  1171. bool
  1172. config SYS_FSL_ERRATUM_ELBC_A001
  1173. bool
  1174. config SYS_FSL_ERRATUM_I2C_A004447
  1175. bool
  1176. config SYS_FSL_A004447_SVR_REV
  1177. hex
  1178. depends on SYS_FSL_ERRATUM_I2C_A004447
  1179. default 0x00 if ARCH_MPC8548
  1180. default 0x10 if ARCH_P1010
  1181. default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
  1182. default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
  1183. config SYS_FSL_ERRATUM_IFC_A002769
  1184. bool
  1185. config SYS_FSL_ERRATUM_IFC_A003399
  1186. bool
  1187. config SYS_FSL_ERRATUM_NMG_CPU_A011
  1188. bool
  1189. config SYS_FSL_ERRATUM_NMG_ETSEC129
  1190. bool
  1191. config SYS_FSL_ERRATUM_NMG_LBC103
  1192. bool
  1193. config SYS_FSL_ERRATUM_P1010_A003549
  1194. bool
  1195. config SYS_FSL_ERRATUM_SATA_A001
  1196. bool
  1197. config SYS_FSL_ERRATUM_SEC_A003571
  1198. bool
  1199. config SYS_FSL_ERRATUM_SRIO_A004034
  1200. bool
  1201. config SYS_FSL_ERRATUM_USB14
  1202. bool
  1203. config SYS_P4080_ERRATUM_CPU22
  1204. bool
  1205. config SYS_P4080_ERRATUM_PCIE_A003
  1206. bool
  1207. config SYS_P4080_ERRATUM_SERDES8
  1208. bool
  1209. config SYS_P4080_ERRATUM_SERDES9
  1210. bool
  1211. config SYS_P4080_ERRATUM_SERDES_A001
  1212. bool
  1213. config SYS_P4080_ERRATUM_SERDES_A005
  1214. bool
  1215. config FSL_PCIE_DISABLE_ASPM
  1216. bool
  1217. config FSL_PCIE_RESET
  1218. bool
  1219. config SYS_FSL_QORIQ_CHASSIS1
  1220. bool
  1221. config SYS_FSL_QORIQ_CHASSIS2
  1222. bool
  1223. config SYS_FSL_NUM_LAWS
  1224. int "Number of local access windows"
  1225. depends on FSL_LAW
  1226. default 32 if ARCH_B4420 || \
  1227. ARCH_B4860 || \
  1228. ARCH_P2041 || \
  1229. ARCH_P3041 || \
  1230. ARCH_P4080 || \
  1231. ARCH_P5020 || \
  1232. ARCH_P5040 || \
  1233. ARCH_T2080 || \
  1234. ARCH_T2081 || \
  1235. ARCH_T4160 || \
  1236. ARCH_T4240
  1237. default 16 if ARCH_T1023 || \
  1238. ARCH_T1024 || \
  1239. ARCH_T1040 || \
  1240. ARCH_T1042
  1241. default 12 if ARCH_BSC9131 || \
  1242. ARCH_BSC9132 || \
  1243. ARCH_C29X || \
  1244. ARCH_MPC8536 || \
  1245. ARCH_MPC8572 || \
  1246. ARCH_P1010 || \
  1247. ARCH_P1011 || \
  1248. ARCH_P1020 || \
  1249. ARCH_P1021 || \
  1250. ARCH_P1022 || \
  1251. ARCH_P1023 || \
  1252. ARCH_P1024 || \
  1253. ARCH_P1025 || \
  1254. ARCH_P2020
  1255. default 10 if ARCH_MPC8544 || \
  1256. ARCH_MPC8548 || \
  1257. ARCH_MPC8568 || \
  1258. ARCH_MPC8569
  1259. default 8 if ARCH_MPC8540 || \
  1260. ARCH_MPC8541 || \
  1261. ARCH_MPC8555 || \
  1262. ARCH_MPC8560
  1263. help
  1264. Number of local access windows. This is fixed per SoC.
  1265. If not sure, do not change.
  1266. config SYS_FSL_THREADS_PER_CORE
  1267. int
  1268. default 2 if E6500
  1269. default 1
  1270. config SYS_NUM_TLBCAMS
  1271. int "Number of TLB CAM entries"
  1272. default 64 if E500MC
  1273. default 16
  1274. help
  1275. Number of TLB CAM entries for Book-E chips. 64 for E500MC,
  1276. 16 for other E500 SoCs.
  1277. config SYS_PPC64
  1278. bool
  1279. config SYS_PPC_E500_USE_DEBUG_TLB
  1280. bool
  1281. config FSL_IFC
  1282. bool
  1283. config FSL_ELBC
  1284. bool
  1285. config SYS_PPC_E500_DEBUG_TLB
  1286. int "Temporary TLB entry for external debugger"
  1287. depends on SYS_PPC_E500_USE_DEBUG_TLB
  1288. default 0 if ARCH_MPC8544 || ARCH_MPC8548
  1289. default 1 if ARCH_MPC8536
  1290. default 2 if ARCH_MPC8572 || \
  1291. ARCH_P1011 || \
  1292. ARCH_P1020 || \
  1293. ARCH_P1021 || \
  1294. ARCH_P1022 || \
  1295. ARCH_P1024 || \
  1296. ARCH_P1025 || \
  1297. ARCH_P2020
  1298. default 3 if ARCH_P1010 || \
  1299. ARCH_BSC9132 || \
  1300. ARCH_C29X
  1301. help
  1302. Select a temporary TLB entry to be used during boot to work
  1303. around limitations in e500v1 and e500v2 external debugger
  1304. support. This reduces the portions of the boot code where
  1305. breakpoints and single stepping do not work. The value of this
  1306. symbol should be set to the TLB1 entry to be used for this
  1307. purpose. If unsure, do not change.
  1308. config SYS_FSL_IFC_CLK_DIV
  1309. int "Divider of platform clock"
  1310. depends on FSL_IFC
  1311. default 2 if ARCH_B4420 || \
  1312. ARCH_B4860 || \
  1313. ARCH_T1024 || \
  1314. ARCH_T1023 || \
  1315. ARCH_T1040 || \
  1316. ARCH_T1042 || \
  1317. ARCH_T4160 || \
  1318. ARCH_T4240
  1319. default 1
  1320. help
  1321. Defines divider of platform clock(clock input to
  1322. IFC controller).
  1323. config SYS_FSL_LBC_CLK_DIV
  1324. int "Divider of platform clock"
  1325. depends on FSL_ELBC || ARCH_MPC8540 || \
  1326. ARCH_MPC8548 || ARCH_MPC8541 || \
  1327. ARCH_MPC8555 || ARCH_MPC8560 || \
  1328. ARCH_MPC8568
  1329. default 2 if ARCH_P2041 || \
  1330. ARCH_P3041 || \
  1331. ARCH_P4080 || \
  1332. ARCH_P5020 || \
  1333. ARCH_P5040
  1334. default 1
  1335. help
  1336. Defines divider of platform clock(clock input to
  1337. eLBC controller).
  1338. source "board/freescale/corenet_ds/Kconfig"
  1339. source "board/freescale/mpc8541cds/Kconfig"
  1340. source "board/freescale/mpc8544ds/Kconfig"
  1341. source "board/freescale/mpc8548cds/Kconfig"
  1342. source "board/freescale/mpc8555cds/Kconfig"
  1343. source "board/freescale/mpc8568mds/Kconfig"
  1344. source "board/freescale/mpc8569mds/Kconfig"
  1345. source "board/freescale/mpc8572ds/Kconfig"
  1346. source "board/freescale/p1010rdb/Kconfig"
  1347. source "board/freescale/p1023rdb/Kconfig"
  1348. source "board/freescale/p1_p2_rdb_pc/Kconfig"
  1349. source "board/freescale/p2041rdb/Kconfig"
  1350. source "board/freescale/qemu-ppce500/Kconfig"
  1351. source "board/freescale/t102xrdb/Kconfig"
  1352. source "board/freescale/t104xrdb/Kconfig"
  1353. source "board/freescale/t208xqds/Kconfig"
  1354. source "board/freescale/t208xrdb/Kconfig"
  1355. source "board/freescale/t4rdb/Kconfig"
  1356. source "board/gdsys/p1022/Kconfig"
  1357. source "board/keymile/Kconfig"
  1358. source "board/sbc8548/Kconfig"
  1359. source "board/socrates/Kconfig"
  1360. source "board/varisys/cyrus/Kconfig"
  1361. source "board/xes/xpedite520x/Kconfig"
  1362. source "board/xes/xpedite537x/Kconfig"
  1363. source "board/xes/xpedite550x/Kconfig"
  1364. source "board/Arcturus/ucp1020/Kconfig"
  1365. endmenu