omap44xx-clocks.dtsi 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Device Tree Source for OMAP4 clock data
  4. *
  5. * Copyright (C) 2013 Texas Instruments, Inc.
  6. */
  7. &cm1_clocks {
  8. extalt_clkin_ck: extalt_clkin_ck {
  9. #clock-cells = <0>;
  10. compatible = "fixed-clock";
  11. clock-frequency = <59000000>;
  12. };
  13. pad_clks_src_ck: pad_clks_src_ck {
  14. #clock-cells = <0>;
  15. compatible = "fixed-clock";
  16. clock-frequency = <12000000>;
  17. };
  18. pad_clks_ck: pad_clks_ck@108 {
  19. #clock-cells = <0>;
  20. compatible = "ti,gate-clock";
  21. clocks = <&pad_clks_src_ck>;
  22. ti,bit-shift = <8>;
  23. reg = <0x0108>;
  24. };
  25. pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck {
  26. #clock-cells = <0>;
  27. compatible = "fixed-clock";
  28. clock-frequency = <12000000>;
  29. };
  30. secure_32k_clk_src_ck: secure_32k_clk_src_ck {
  31. #clock-cells = <0>;
  32. compatible = "fixed-clock";
  33. clock-frequency = <32768>;
  34. };
  35. slimbus_src_clk: slimbus_src_clk {
  36. #clock-cells = <0>;
  37. compatible = "fixed-clock";
  38. clock-frequency = <12000000>;
  39. };
  40. slimbus_clk: slimbus_clk@108 {
  41. #clock-cells = <0>;
  42. compatible = "ti,gate-clock";
  43. clocks = <&slimbus_src_clk>;
  44. ti,bit-shift = <10>;
  45. reg = <0x0108>;
  46. };
  47. sys_32k_ck: sys_32k_ck {
  48. #clock-cells = <0>;
  49. compatible = "fixed-clock";
  50. clock-frequency = <32768>;
  51. };
  52. virt_12000000_ck: virt_12000000_ck {
  53. #clock-cells = <0>;
  54. compatible = "fixed-clock";
  55. clock-frequency = <12000000>;
  56. };
  57. virt_13000000_ck: virt_13000000_ck {
  58. #clock-cells = <0>;
  59. compatible = "fixed-clock";
  60. clock-frequency = <13000000>;
  61. };
  62. virt_16800000_ck: virt_16800000_ck {
  63. #clock-cells = <0>;
  64. compatible = "fixed-clock";
  65. clock-frequency = <16800000>;
  66. };
  67. virt_19200000_ck: virt_19200000_ck {
  68. #clock-cells = <0>;
  69. compatible = "fixed-clock";
  70. clock-frequency = <19200000>;
  71. };
  72. virt_26000000_ck: virt_26000000_ck {
  73. #clock-cells = <0>;
  74. compatible = "fixed-clock";
  75. clock-frequency = <26000000>;
  76. };
  77. virt_27000000_ck: virt_27000000_ck {
  78. #clock-cells = <0>;
  79. compatible = "fixed-clock";
  80. clock-frequency = <27000000>;
  81. };
  82. virt_38400000_ck: virt_38400000_ck {
  83. #clock-cells = <0>;
  84. compatible = "fixed-clock";
  85. clock-frequency = <38400000>;
  86. };
  87. tie_low_clock_ck: tie_low_clock_ck {
  88. #clock-cells = <0>;
  89. compatible = "fixed-clock";
  90. clock-frequency = <0>;
  91. };
  92. utmi_phy_clkout_ck: utmi_phy_clkout_ck {
  93. #clock-cells = <0>;
  94. compatible = "fixed-clock";
  95. clock-frequency = <60000000>;
  96. };
  97. xclk60mhsp1_ck: xclk60mhsp1_ck {
  98. #clock-cells = <0>;
  99. compatible = "fixed-clock";
  100. clock-frequency = <60000000>;
  101. };
  102. xclk60mhsp2_ck: xclk60mhsp2_ck {
  103. #clock-cells = <0>;
  104. compatible = "fixed-clock";
  105. clock-frequency = <60000000>;
  106. };
  107. xclk60motg_ck: xclk60motg_ck {
  108. #clock-cells = <0>;
  109. compatible = "fixed-clock";
  110. clock-frequency = <60000000>;
  111. };
  112. dpll_abe_ck: dpll_abe_ck@1e0 {
  113. #clock-cells = <0>;
  114. compatible = "ti,omap4-dpll-m4xen-clock";
  115. clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
  116. reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
  117. };
  118. dpll_abe_x2_ck: dpll_abe_x2_ck@1f0 {
  119. #clock-cells = <0>;
  120. compatible = "ti,omap4-dpll-x2-clock";
  121. clocks = <&dpll_abe_ck>;
  122. reg = <0x01f0>;
  123. };
  124. dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
  125. #clock-cells = <0>;
  126. compatible = "ti,divider-clock";
  127. clocks = <&dpll_abe_x2_ck>;
  128. ti,max-div = <31>;
  129. ti,autoidle-shift = <8>;
  130. reg = <0x01f0>;
  131. ti,index-starts-at-one;
  132. ti,invert-autoidle-bit;
  133. };
  134. abe_24m_fclk: abe_24m_fclk {
  135. #clock-cells = <0>;
  136. compatible = "fixed-factor-clock";
  137. clocks = <&dpll_abe_m2x2_ck>;
  138. clock-mult = <1>;
  139. clock-div = <8>;
  140. };
  141. abe_clk: abe_clk@108 {
  142. #clock-cells = <0>;
  143. compatible = "ti,divider-clock";
  144. clocks = <&dpll_abe_m2x2_ck>;
  145. ti,max-div = <4>;
  146. reg = <0x0108>;
  147. ti,index-power-of-two;
  148. };
  149. dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
  150. #clock-cells = <0>;
  151. compatible = "ti,divider-clock";
  152. clocks = <&dpll_abe_x2_ck>;
  153. ti,max-div = <31>;
  154. ti,autoidle-shift = <8>;
  155. reg = <0x01f4>;
  156. ti,index-starts-at-one;
  157. ti,invert-autoidle-bit;
  158. };
  159. core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@12c {
  160. #clock-cells = <0>;
  161. compatible = "ti,mux-clock";
  162. clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
  163. ti,bit-shift = <23>;
  164. reg = <0x012c>;
  165. };
  166. dpll_core_ck: dpll_core_ck@120 {
  167. #clock-cells = <0>;
  168. compatible = "ti,omap4-dpll-core-clock";
  169. clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
  170. reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
  171. };
  172. dpll_core_x2_ck: dpll_core_x2_ck {
  173. #clock-cells = <0>;
  174. compatible = "ti,omap4-dpll-x2-clock";
  175. clocks = <&dpll_core_ck>;
  176. };
  177. dpll_core_m6x2_ck: dpll_core_m6x2_ck@140 {
  178. #clock-cells = <0>;
  179. compatible = "ti,divider-clock";
  180. clocks = <&dpll_core_x2_ck>;
  181. ti,max-div = <31>;
  182. ti,autoidle-shift = <8>;
  183. reg = <0x0140>;
  184. ti,index-starts-at-one;
  185. ti,invert-autoidle-bit;
  186. };
  187. dpll_core_m2_ck: dpll_core_m2_ck@130 {
  188. #clock-cells = <0>;
  189. compatible = "ti,divider-clock";
  190. clocks = <&dpll_core_ck>;
  191. ti,max-div = <31>;
  192. ti,autoidle-shift = <8>;
  193. reg = <0x0130>;
  194. ti,index-starts-at-one;
  195. ti,invert-autoidle-bit;
  196. };
  197. ddrphy_ck: ddrphy_ck {
  198. #clock-cells = <0>;
  199. compatible = "fixed-factor-clock";
  200. clocks = <&dpll_core_m2_ck>;
  201. clock-mult = <1>;
  202. clock-div = <2>;
  203. };
  204. dpll_core_m5x2_ck: dpll_core_m5x2_ck@13c {
  205. #clock-cells = <0>;
  206. compatible = "ti,divider-clock";
  207. clocks = <&dpll_core_x2_ck>;
  208. ti,max-div = <31>;
  209. ti,autoidle-shift = <8>;
  210. reg = <0x013c>;
  211. ti,index-starts-at-one;
  212. ti,invert-autoidle-bit;
  213. };
  214. div_core_ck: div_core_ck@100 {
  215. #clock-cells = <0>;
  216. compatible = "ti,divider-clock";
  217. clocks = <&dpll_core_m5x2_ck>;
  218. reg = <0x0100>;
  219. ti,max-div = <2>;
  220. };
  221. div_iva_hs_clk: div_iva_hs_clk@1dc {
  222. #clock-cells = <0>;
  223. compatible = "ti,divider-clock";
  224. clocks = <&dpll_core_m5x2_ck>;
  225. ti,max-div = <4>;
  226. reg = <0x01dc>;
  227. ti,index-power-of-two;
  228. };
  229. div_mpu_hs_clk: div_mpu_hs_clk@19c {
  230. #clock-cells = <0>;
  231. compatible = "ti,divider-clock";
  232. clocks = <&dpll_core_m5x2_ck>;
  233. ti,max-div = <4>;
  234. reg = <0x019c>;
  235. ti,index-power-of-two;
  236. };
  237. dpll_core_m4x2_ck: dpll_core_m4x2_ck@138 {
  238. #clock-cells = <0>;
  239. compatible = "ti,divider-clock";
  240. clocks = <&dpll_core_x2_ck>;
  241. ti,max-div = <31>;
  242. ti,autoidle-shift = <8>;
  243. reg = <0x0138>;
  244. ti,index-starts-at-one;
  245. ti,invert-autoidle-bit;
  246. };
  247. dll_clk_div_ck: dll_clk_div_ck {
  248. #clock-cells = <0>;
  249. compatible = "fixed-factor-clock";
  250. clocks = <&dpll_core_m4x2_ck>;
  251. clock-mult = <1>;
  252. clock-div = <2>;
  253. };
  254. dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
  255. #clock-cells = <0>;
  256. compatible = "ti,divider-clock";
  257. clocks = <&dpll_abe_ck>;
  258. ti,max-div = <31>;
  259. reg = <0x01f0>;
  260. ti,index-starts-at-one;
  261. };
  262. dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck@134 {
  263. #clock-cells = <0>;
  264. compatible = "ti,composite-no-wait-gate-clock";
  265. clocks = <&dpll_core_x2_ck>;
  266. ti,bit-shift = <8>;
  267. reg = <0x0134>;
  268. };
  269. dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@134 {
  270. #clock-cells = <0>;
  271. compatible = "ti,composite-divider-clock";
  272. clocks = <&dpll_core_x2_ck>;
  273. ti,max-div = <31>;
  274. reg = <0x0134>;
  275. ti,index-starts-at-one;
  276. };
  277. dpll_core_m3x2_ck: dpll_core_m3x2_ck {
  278. #clock-cells = <0>;
  279. compatible = "ti,composite-clock";
  280. clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>;
  281. };
  282. dpll_core_m7x2_ck: dpll_core_m7x2_ck@144 {
  283. #clock-cells = <0>;
  284. compatible = "ti,divider-clock";
  285. clocks = <&dpll_core_x2_ck>;
  286. ti,max-div = <31>;
  287. ti,autoidle-shift = <8>;
  288. reg = <0x0144>;
  289. ti,index-starts-at-one;
  290. ti,invert-autoidle-bit;
  291. };
  292. iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@1ac {
  293. #clock-cells = <0>;
  294. compatible = "ti,mux-clock";
  295. clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>;
  296. ti,bit-shift = <23>;
  297. reg = <0x01ac>;
  298. };
  299. dpll_iva_ck: dpll_iva_ck@1a0 {
  300. #clock-cells = <0>;
  301. compatible = "ti,omap4-dpll-clock";
  302. clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
  303. reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
  304. assigned-clocks = <&dpll_iva_ck>;
  305. assigned-clock-rates = <931200000>;
  306. };
  307. dpll_iva_x2_ck: dpll_iva_x2_ck {
  308. #clock-cells = <0>;
  309. compatible = "ti,omap4-dpll-x2-clock";
  310. clocks = <&dpll_iva_ck>;
  311. };
  312. dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@1b8 {
  313. #clock-cells = <0>;
  314. compatible = "ti,divider-clock";
  315. clocks = <&dpll_iva_x2_ck>;
  316. ti,max-div = <31>;
  317. ti,autoidle-shift = <8>;
  318. reg = <0x01b8>;
  319. ti,index-starts-at-one;
  320. ti,invert-autoidle-bit;
  321. assigned-clocks = <&dpll_iva_m4x2_ck>;
  322. assigned-clock-rates = <465600000>;
  323. };
  324. dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc {
  325. #clock-cells = <0>;
  326. compatible = "ti,divider-clock";
  327. clocks = <&dpll_iva_x2_ck>;
  328. ti,max-div = <31>;
  329. ti,autoidle-shift = <8>;
  330. reg = <0x01bc>;
  331. ti,index-starts-at-one;
  332. ti,invert-autoidle-bit;
  333. assigned-clocks = <&dpll_iva_m5x2_ck>;
  334. assigned-clock-rates = <266100000>;
  335. };
  336. dpll_mpu_ck: dpll_mpu_ck@160 {
  337. #clock-cells = <0>;
  338. compatible = "ti,omap4-dpll-clock";
  339. clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>;
  340. reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
  341. };
  342. dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
  343. #clock-cells = <0>;
  344. compatible = "ti,divider-clock";
  345. clocks = <&dpll_mpu_ck>;
  346. ti,max-div = <31>;
  347. ti,autoidle-shift = <8>;
  348. reg = <0x0170>;
  349. ti,index-starts-at-one;
  350. ti,invert-autoidle-bit;
  351. };
  352. per_hs_clk_div_ck: per_hs_clk_div_ck {
  353. #clock-cells = <0>;
  354. compatible = "fixed-factor-clock";
  355. clocks = <&dpll_abe_m3x2_ck>;
  356. clock-mult = <1>;
  357. clock-div = <2>;
  358. };
  359. usb_hs_clk_div_ck: usb_hs_clk_div_ck {
  360. #clock-cells = <0>;
  361. compatible = "fixed-factor-clock";
  362. clocks = <&dpll_abe_m3x2_ck>;
  363. clock-mult = <1>;
  364. clock-div = <3>;
  365. };
  366. l3_div_ck: l3_div_ck@100 {
  367. #clock-cells = <0>;
  368. compatible = "ti,divider-clock";
  369. clocks = <&div_core_ck>;
  370. ti,bit-shift = <4>;
  371. ti,max-div = <2>;
  372. reg = <0x0100>;
  373. };
  374. l4_div_ck: l4_div_ck@100 {
  375. #clock-cells = <0>;
  376. compatible = "ti,divider-clock";
  377. clocks = <&l3_div_ck>;
  378. ti,bit-shift = <8>;
  379. ti,max-div = <2>;
  380. reg = <0x0100>;
  381. };
  382. lp_clk_div_ck: lp_clk_div_ck {
  383. #clock-cells = <0>;
  384. compatible = "fixed-factor-clock";
  385. clocks = <&dpll_abe_m2x2_ck>;
  386. clock-mult = <1>;
  387. clock-div = <16>;
  388. };
  389. mpu_periphclk: mpu_periphclk {
  390. #clock-cells = <0>;
  391. compatible = "fixed-factor-clock";
  392. clocks = <&dpll_mpu_ck>;
  393. clock-mult = <1>;
  394. clock-div = <2>;
  395. };
  396. ocp_abe_iclk: ocp_abe_iclk@528 {
  397. #clock-cells = <0>;
  398. compatible = "ti,divider-clock";
  399. clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 24>;
  400. ti,bit-shift = <24>;
  401. reg = <0x0528>;
  402. ti,dividers = <2>, <1>;
  403. };
  404. per_abe_24m_fclk: per_abe_24m_fclk {
  405. #clock-cells = <0>;
  406. compatible = "fixed-factor-clock";
  407. clocks = <&dpll_abe_m2_ck>;
  408. clock-mult = <1>;
  409. clock-div = <4>;
  410. };
  411. dummy_ck: dummy_ck {
  412. #clock-cells = <0>;
  413. compatible = "fixed-clock";
  414. clock-frequency = <0>;
  415. };
  416. };
  417. &prm_clocks {
  418. sys_clkin_ck: sys_clkin_ck@110 {
  419. #clock-cells = <0>;
  420. compatible = "ti,mux-clock";
  421. clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
  422. reg = <0x0110>;
  423. ti,index-starts-at-one;
  424. };
  425. abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@108 {
  426. #clock-cells = <0>;
  427. compatible = "ti,mux-clock";
  428. clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
  429. ti,bit-shift = <24>;
  430. reg = <0x0108>;
  431. };
  432. abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@10c {
  433. #clock-cells = <0>;
  434. compatible = "ti,mux-clock";
  435. clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
  436. reg = <0x010c>;
  437. };
  438. dbgclk_mux_ck: dbgclk_mux_ck {
  439. #clock-cells = <0>;
  440. compatible = "fixed-factor-clock";
  441. clocks = <&sys_clkin_ck>;
  442. clock-mult = <1>;
  443. clock-div = <1>;
  444. };
  445. l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@108 {
  446. #clock-cells = <0>;
  447. compatible = "ti,mux-clock";
  448. clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>;
  449. reg = <0x0108>;
  450. };
  451. syc_clk_div_ck: syc_clk_div_ck@100 {
  452. #clock-cells = <0>;
  453. compatible = "ti,divider-clock";
  454. clocks = <&sys_clkin_ck>;
  455. reg = <0x0100>;
  456. ti,max-div = <2>;
  457. };
  458. usim_ck: usim_ck@1858 {
  459. #clock-cells = <0>;
  460. compatible = "ti,divider-clock";
  461. clocks = <&dpll_per_m4x2_ck>;
  462. ti,bit-shift = <24>;
  463. reg = <0x1858>;
  464. ti,dividers = <14>, <18>;
  465. };
  466. usim_fclk: usim_fclk@1858 {
  467. #clock-cells = <0>;
  468. compatible = "ti,gate-clock";
  469. clocks = <&usim_ck>;
  470. ti,bit-shift = <8>;
  471. reg = <0x1858>;
  472. };
  473. trace_clk_div_ck: trace_clk_div_ck {
  474. #clock-cells = <0>;
  475. compatible = "ti,clkdm-gate-clock";
  476. clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 24>;
  477. };
  478. };
  479. &prm_clockdomains {
  480. emu_sys_clkdm: emu_sys_clkdm {
  481. compatible = "ti,clockdomain";
  482. clocks = <&trace_clk_div_ck>;
  483. };
  484. };
  485. &cm2_clocks {
  486. per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@14c {
  487. #clock-cells = <0>;
  488. compatible = "ti,mux-clock";
  489. clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>;
  490. ti,bit-shift = <23>;
  491. reg = <0x014c>;
  492. };
  493. dpll_per_ck: dpll_per_ck@140 {
  494. #clock-cells = <0>;
  495. compatible = "ti,omap4-dpll-clock";
  496. clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>;
  497. reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
  498. };
  499. dpll_per_m2_ck: dpll_per_m2_ck@150 {
  500. #clock-cells = <0>;
  501. compatible = "ti,divider-clock";
  502. clocks = <&dpll_per_ck>;
  503. ti,max-div = <31>;
  504. reg = <0x0150>;
  505. ti,index-starts-at-one;
  506. };
  507. dpll_per_x2_ck: dpll_per_x2_ck@150 {
  508. #clock-cells = <0>;
  509. compatible = "ti,omap4-dpll-x2-clock";
  510. clocks = <&dpll_per_ck>;
  511. reg = <0x0150>;
  512. };
  513. dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
  514. #clock-cells = <0>;
  515. compatible = "ti,divider-clock";
  516. clocks = <&dpll_per_x2_ck>;
  517. ti,max-div = <31>;
  518. ti,autoidle-shift = <8>;
  519. reg = <0x0150>;
  520. ti,index-starts-at-one;
  521. ti,invert-autoidle-bit;
  522. };
  523. dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck@154 {
  524. #clock-cells = <0>;
  525. compatible = "ti,composite-no-wait-gate-clock";
  526. clocks = <&dpll_per_x2_ck>;
  527. ti,bit-shift = <8>;
  528. reg = <0x0154>;
  529. };
  530. dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@154 {
  531. #clock-cells = <0>;
  532. compatible = "ti,composite-divider-clock";
  533. clocks = <&dpll_per_x2_ck>;
  534. ti,max-div = <31>;
  535. reg = <0x0154>;
  536. ti,index-starts-at-one;
  537. };
  538. dpll_per_m3x2_ck: dpll_per_m3x2_ck {
  539. #clock-cells = <0>;
  540. compatible = "ti,composite-clock";
  541. clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>;
  542. };
  543. dpll_per_m4x2_ck: dpll_per_m4x2_ck@158 {
  544. #clock-cells = <0>;
  545. compatible = "ti,divider-clock";
  546. clocks = <&dpll_per_x2_ck>;
  547. ti,max-div = <31>;
  548. ti,autoidle-shift = <8>;
  549. reg = <0x0158>;
  550. ti,index-starts-at-one;
  551. ti,invert-autoidle-bit;
  552. };
  553. dpll_per_m5x2_ck: dpll_per_m5x2_ck@15c {
  554. #clock-cells = <0>;
  555. compatible = "ti,divider-clock";
  556. clocks = <&dpll_per_x2_ck>;
  557. ti,max-div = <31>;
  558. ti,autoidle-shift = <8>;
  559. reg = <0x015c>;
  560. ti,index-starts-at-one;
  561. ti,invert-autoidle-bit;
  562. };
  563. dpll_per_m6x2_ck: dpll_per_m6x2_ck@160 {
  564. #clock-cells = <0>;
  565. compatible = "ti,divider-clock";
  566. clocks = <&dpll_per_x2_ck>;
  567. ti,max-div = <31>;
  568. ti,autoidle-shift = <8>;
  569. reg = <0x0160>;
  570. ti,index-starts-at-one;
  571. ti,invert-autoidle-bit;
  572. };
  573. dpll_per_m7x2_ck: dpll_per_m7x2_ck@164 {
  574. #clock-cells = <0>;
  575. compatible = "ti,divider-clock";
  576. clocks = <&dpll_per_x2_ck>;
  577. ti,max-div = <31>;
  578. ti,autoidle-shift = <8>;
  579. reg = <0x0164>;
  580. ti,index-starts-at-one;
  581. ti,invert-autoidle-bit;
  582. };
  583. dpll_usb_ck: dpll_usb_ck@180 {
  584. #clock-cells = <0>;
  585. compatible = "ti,omap4-dpll-j-type-clock";
  586. clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>;
  587. reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
  588. };
  589. dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@1b4 {
  590. #clock-cells = <0>;
  591. compatible = "ti,fixed-factor-clock";
  592. clocks = <&dpll_usb_ck>;
  593. ti,clock-div = <1>;
  594. ti,autoidle-shift = <8>;
  595. reg = <0x01b4>;
  596. ti,clock-mult = <1>;
  597. ti,invert-autoidle-bit;
  598. };
  599. dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
  600. #clock-cells = <0>;
  601. compatible = "ti,divider-clock";
  602. clocks = <&dpll_usb_ck>;
  603. ti,max-div = <127>;
  604. ti,autoidle-shift = <8>;
  605. reg = <0x0190>;
  606. ti,index-starts-at-one;
  607. ti,invert-autoidle-bit;
  608. };
  609. ducati_clk_mux_ck: ducati_clk_mux_ck@100 {
  610. #clock-cells = <0>;
  611. compatible = "ti,mux-clock";
  612. clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>;
  613. reg = <0x0100>;
  614. };
  615. func_12m_fclk: func_12m_fclk {
  616. #clock-cells = <0>;
  617. compatible = "fixed-factor-clock";
  618. clocks = <&dpll_per_m2x2_ck>;
  619. clock-mult = <1>;
  620. clock-div = <16>;
  621. };
  622. func_24m_clk: func_24m_clk {
  623. #clock-cells = <0>;
  624. compatible = "fixed-factor-clock";
  625. clocks = <&dpll_per_m2_ck>;
  626. clock-mult = <1>;
  627. clock-div = <4>;
  628. };
  629. func_24mc_fclk: func_24mc_fclk {
  630. #clock-cells = <0>;
  631. compatible = "fixed-factor-clock";
  632. clocks = <&dpll_per_m2x2_ck>;
  633. clock-mult = <1>;
  634. clock-div = <8>;
  635. };
  636. func_48m_fclk: func_48m_fclk@108 {
  637. #clock-cells = <0>;
  638. compatible = "ti,divider-clock";
  639. clocks = <&dpll_per_m2x2_ck>;
  640. reg = <0x0108>;
  641. ti,dividers = <4>, <8>;
  642. };
  643. func_48mc_fclk: func_48mc_fclk {
  644. #clock-cells = <0>;
  645. compatible = "fixed-factor-clock";
  646. clocks = <&dpll_per_m2x2_ck>;
  647. clock-mult = <1>;
  648. clock-div = <4>;
  649. };
  650. func_64m_fclk: func_64m_fclk@108 {
  651. #clock-cells = <0>;
  652. compatible = "ti,divider-clock";
  653. clocks = <&dpll_per_m4x2_ck>;
  654. reg = <0x0108>;
  655. ti,dividers = <2>, <4>;
  656. };
  657. func_96m_fclk: func_96m_fclk@108 {
  658. #clock-cells = <0>;
  659. compatible = "ti,divider-clock";
  660. clocks = <&dpll_per_m2x2_ck>;
  661. reg = <0x0108>;
  662. ti,dividers = <2>, <4>;
  663. };
  664. init_60m_fclk: init_60m_fclk@104 {
  665. #clock-cells = <0>;
  666. compatible = "ti,divider-clock";
  667. clocks = <&dpll_usb_m2_ck>;
  668. reg = <0x0104>;
  669. ti,dividers = <1>, <8>;
  670. };
  671. per_abe_nc_fclk: per_abe_nc_fclk@108 {
  672. #clock-cells = <0>;
  673. compatible = "ti,divider-clock";
  674. clocks = <&dpll_abe_m2_ck>;
  675. reg = <0x0108>;
  676. ti,max-div = <2>;
  677. };
  678. sha2md5_fck: sha2md5_fck@15c8 {
  679. #clock-cells = <0>;
  680. compatible = "ti,gate-clock";
  681. clocks = <&l3_div_ck>;
  682. ti,bit-shift = <1>;
  683. reg = <0x15c8>;
  684. };
  685. usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
  686. #clock-cells = <0>;
  687. compatible = "ti,gate-clock";
  688. clocks = <&sys_32k_ck>;
  689. ti,bit-shift = <8>;
  690. reg = <0x0640>;
  691. };
  692. };
  693. &cm2_clockdomains {
  694. l3_init_clkdm: l3_init_clkdm {
  695. compatible = "ti,clockdomain";
  696. clocks = <&dpll_usb_ck>;
  697. };
  698. };
  699. &scrm_clocks {
  700. auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
  701. #clock-cells = <0>;
  702. compatible = "ti,composite-no-wait-gate-clock";
  703. clocks = <&dpll_core_m3x2_ck>;
  704. ti,bit-shift = <8>;
  705. reg = <0x0310>;
  706. };
  707. auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
  708. #clock-cells = <0>;
  709. compatible = "ti,composite-mux-clock";
  710. clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
  711. ti,bit-shift = <1>;
  712. reg = <0x0310>;
  713. };
  714. auxclk0_src_ck: auxclk0_src_ck {
  715. #clock-cells = <0>;
  716. compatible = "ti,composite-clock";
  717. clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
  718. };
  719. auxclk0_ck: auxclk0_ck@310 {
  720. #clock-cells = <0>;
  721. compatible = "ti,divider-clock";
  722. clocks = <&auxclk0_src_ck>;
  723. ti,bit-shift = <16>;
  724. ti,max-div = <16>;
  725. reg = <0x0310>;
  726. };
  727. auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
  728. #clock-cells = <0>;
  729. compatible = "ti,composite-no-wait-gate-clock";
  730. clocks = <&dpll_core_m3x2_ck>;
  731. ti,bit-shift = <8>;
  732. reg = <0x0314>;
  733. };
  734. auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
  735. #clock-cells = <0>;
  736. compatible = "ti,composite-mux-clock";
  737. clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
  738. ti,bit-shift = <1>;
  739. reg = <0x0314>;
  740. };
  741. auxclk1_src_ck: auxclk1_src_ck {
  742. #clock-cells = <0>;
  743. compatible = "ti,composite-clock";
  744. clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
  745. };
  746. auxclk1_ck: auxclk1_ck@314 {
  747. #clock-cells = <0>;
  748. compatible = "ti,divider-clock";
  749. clocks = <&auxclk1_src_ck>;
  750. ti,bit-shift = <16>;
  751. ti,max-div = <16>;
  752. reg = <0x0314>;
  753. };
  754. auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
  755. #clock-cells = <0>;
  756. compatible = "ti,composite-no-wait-gate-clock";
  757. clocks = <&dpll_core_m3x2_ck>;
  758. ti,bit-shift = <8>;
  759. reg = <0x0318>;
  760. };
  761. auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
  762. #clock-cells = <0>;
  763. compatible = "ti,composite-mux-clock";
  764. clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
  765. ti,bit-shift = <1>;
  766. reg = <0x0318>;
  767. };
  768. auxclk2_src_ck: auxclk2_src_ck {
  769. #clock-cells = <0>;
  770. compatible = "ti,composite-clock";
  771. clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
  772. };
  773. auxclk2_ck: auxclk2_ck@318 {
  774. #clock-cells = <0>;
  775. compatible = "ti,divider-clock";
  776. clocks = <&auxclk2_src_ck>;
  777. ti,bit-shift = <16>;
  778. ti,max-div = <16>;
  779. reg = <0x0318>;
  780. };
  781. auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
  782. #clock-cells = <0>;
  783. compatible = "ti,composite-no-wait-gate-clock";
  784. clocks = <&dpll_core_m3x2_ck>;
  785. ti,bit-shift = <8>;
  786. reg = <0x031c>;
  787. };
  788. auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
  789. #clock-cells = <0>;
  790. compatible = "ti,composite-mux-clock";
  791. clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
  792. ti,bit-shift = <1>;
  793. reg = <0x031c>;
  794. };
  795. auxclk3_src_ck: auxclk3_src_ck {
  796. #clock-cells = <0>;
  797. compatible = "ti,composite-clock";
  798. clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
  799. };
  800. auxclk3_ck: auxclk3_ck@31c {
  801. #clock-cells = <0>;
  802. compatible = "ti,divider-clock";
  803. clocks = <&auxclk3_src_ck>;
  804. ti,bit-shift = <16>;
  805. ti,max-div = <16>;
  806. reg = <0x031c>;
  807. };
  808. auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
  809. #clock-cells = <0>;
  810. compatible = "ti,composite-no-wait-gate-clock";
  811. clocks = <&dpll_core_m3x2_ck>;
  812. ti,bit-shift = <8>;
  813. reg = <0x0320>;
  814. };
  815. auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
  816. #clock-cells = <0>;
  817. compatible = "ti,composite-mux-clock";
  818. clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
  819. ti,bit-shift = <1>;
  820. reg = <0x0320>;
  821. };
  822. auxclk4_src_ck: auxclk4_src_ck {
  823. #clock-cells = <0>;
  824. compatible = "ti,composite-clock";
  825. clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
  826. };
  827. auxclk4_ck: auxclk4_ck@320 {
  828. #clock-cells = <0>;
  829. compatible = "ti,divider-clock";
  830. clocks = <&auxclk4_src_ck>;
  831. ti,bit-shift = <16>;
  832. ti,max-div = <16>;
  833. reg = <0x0320>;
  834. };
  835. auxclk5_src_gate_ck: auxclk5_src_gate_ck@324 {
  836. #clock-cells = <0>;
  837. compatible = "ti,composite-no-wait-gate-clock";
  838. clocks = <&dpll_core_m3x2_ck>;
  839. ti,bit-shift = <8>;
  840. reg = <0x0324>;
  841. };
  842. auxclk5_src_mux_ck: auxclk5_src_mux_ck@324 {
  843. #clock-cells = <0>;
  844. compatible = "ti,composite-mux-clock";
  845. clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
  846. ti,bit-shift = <1>;
  847. reg = <0x0324>;
  848. };
  849. auxclk5_src_ck: auxclk5_src_ck {
  850. #clock-cells = <0>;
  851. compatible = "ti,composite-clock";
  852. clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>;
  853. };
  854. auxclk5_ck: auxclk5_ck@324 {
  855. #clock-cells = <0>;
  856. compatible = "ti,divider-clock";
  857. clocks = <&auxclk5_src_ck>;
  858. ti,bit-shift = <16>;
  859. ti,max-div = <16>;
  860. reg = <0x0324>;
  861. };
  862. auxclkreq0_ck: auxclkreq0_ck@210 {
  863. #clock-cells = <0>;
  864. compatible = "ti,mux-clock";
  865. clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
  866. ti,bit-shift = <2>;
  867. reg = <0x0210>;
  868. };
  869. auxclkreq1_ck: auxclkreq1_ck@214 {
  870. #clock-cells = <0>;
  871. compatible = "ti,mux-clock";
  872. clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
  873. ti,bit-shift = <2>;
  874. reg = <0x0214>;
  875. };
  876. auxclkreq2_ck: auxclkreq2_ck@218 {
  877. #clock-cells = <0>;
  878. compatible = "ti,mux-clock";
  879. clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
  880. ti,bit-shift = <2>;
  881. reg = <0x0218>;
  882. };
  883. auxclkreq3_ck: auxclkreq3_ck@21c {
  884. #clock-cells = <0>;
  885. compatible = "ti,mux-clock";
  886. clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
  887. ti,bit-shift = <2>;
  888. reg = <0x021c>;
  889. };
  890. auxclkreq4_ck: auxclkreq4_ck@220 {
  891. #clock-cells = <0>;
  892. compatible = "ti,mux-clock";
  893. clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
  894. ti,bit-shift = <2>;
  895. reg = <0x0220>;
  896. };
  897. auxclkreq5_ck: auxclkreq5_ck@224 {
  898. #clock-cells = <0>;
  899. compatible = "ti,mux-clock";
  900. clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
  901. ti,bit-shift = <2>;
  902. reg = <0x0224>;
  903. };
  904. };
  905. &cm1 {
  906. mpuss_cm: mpuss_cm@300 {
  907. compatible = "ti,omap4-cm";
  908. reg = <0x300 0x100>;
  909. #address-cells = <1>;
  910. #size-cells = <1>;
  911. ranges = <0 0x300 0x100>;
  912. mpuss_clkctrl: clk@20 {
  913. compatible = "ti,clkctrl";
  914. reg = <0x20 0x4>;
  915. #clock-cells = <2>;
  916. };
  917. };
  918. tesla_cm: tesla_cm@400 {
  919. compatible = "ti,omap4-cm";
  920. reg = <0x400 0x100>;
  921. #address-cells = <1>;
  922. #size-cells = <1>;
  923. ranges = <0 0x400 0x100>;
  924. tesla_clkctrl: clk@20 {
  925. compatible = "ti,clkctrl";
  926. reg = <0x20 0x4>;
  927. #clock-cells = <2>;
  928. };
  929. };
  930. abe_cm: abe_cm@500 {
  931. compatible = "ti,omap4-cm";
  932. reg = <0x500 0x100>;
  933. #address-cells = <1>;
  934. #size-cells = <1>;
  935. ranges = <0 0x500 0x100>;
  936. abe_clkctrl: clk@20 {
  937. compatible = "ti,clkctrl";
  938. reg = <0x20 0x6c>;
  939. #clock-cells = <2>;
  940. };
  941. };
  942. };
  943. &cm2 {
  944. l4_ao_cm: l4_ao_cm@600 {
  945. compatible = "ti,omap4-cm";
  946. reg = <0x600 0x100>;
  947. #address-cells = <1>;
  948. #size-cells = <1>;
  949. ranges = <0 0x600 0x100>;
  950. l4_ao_clkctrl: clk@20 {
  951. compatible = "ti,clkctrl";
  952. reg = <0x20 0x1c>;
  953. #clock-cells = <2>;
  954. };
  955. };
  956. l3_1_cm: l3_1_cm@700 {
  957. compatible = "ti,omap4-cm";
  958. reg = <0x700 0x100>;
  959. #address-cells = <1>;
  960. #size-cells = <1>;
  961. ranges = <0 0x700 0x100>;
  962. l3_1_clkctrl: clk@20 {
  963. compatible = "ti,clkctrl";
  964. reg = <0x20 0x4>;
  965. #clock-cells = <2>;
  966. };
  967. };
  968. l3_2_cm: l3_2_cm@800 {
  969. compatible = "ti,omap4-cm";
  970. reg = <0x800 0x100>;
  971. #address-cells = <1>;
  972. #size-cells = <1>;
  973. ranges = <0 0x800 0x100>;
  974. l3_2_clkctrl: clk@20 {
  975. compatible = "ti,clkctrl";
  976. reg = <0x20 0x14>;
  977. #clock-cells = <2>;
  978. };
  979. };
  980. ducati_cm: ducati_cm@900 {
  981. compatible = "ti,omap4-cm";
  982. reg = <0x900 0x100>;
  983. #address-cells = <1>;
  984. #size-cells = <1>;
  985. ranges = <0 0x900 0x100>;
  986. ducati_clkctrl: clk@20 {
  987. compatible = "ti,clkctrl";
  988. reg = <0x20 0x4>;
  989. #clock-cells = <2>;
  990. };
  991. };
  992. l3_dma_cm: l3_dma_cm@a00 {
  993. compatible = "ti,omap4-cm";
  994. reg = <0xa00 0x100>;
  995. #address-cells = <1>;
  996. #size-cells = <1>;
  997. ranges = <0 0xa00 0x100>;
  998. l3_dma_clkctrl: clk@20 {
  999. compatible = "ti,clkctrl";
  1000. reg = <0x20 0x4>;
  1001. #clock-cells = <2>;
  1002. };
  1003. };
  1004. l3_emif_cm: l3_emif_cm@b00 {
  1005. compatible = "ti,omap4-cm";
  1006. reg = <0xb00 0x100>;
  1007. #address-cells = <1>;
  1008. #size-cells = <1>;
  1009. ranges = <0 0xb00 0x100>;
  1010. l3_emif_clkctrl: clk@20 {
  1011. compatible = "ti,clkctrl";
  1012. reg = <0x20 0x1c>;
  1013. #clock-cells = <2>;
  1014. };
  1015. };
  1016. d2d_cm: d2d_cm@c00 {
  1017. compatible = "ti,omap4-cm";
  1018. reg = <0xc00 0x100>;
  1019. #address-cells = <1>;
  1020. #size-cells = <1>;
  1021. ranges = <0 0xc00 0x100>;
  1022. d2d_clkctrl: clk@20 {
  1023. compatible = "ti,clkctrl";
  1024. reg = <0x20 0x4>;
  1025. #clock-cells = <2>;
  1026. };
  1027. };
  1028. l4_cfg_cm: l4_cfg_cm@d00 {
  1029. compatible = "ti,omap4-cm";
  1030. reg = <0xd00 0x100>;
  1031. #address-cells = <1>;
  1032. #size-cells = <1>;
  1033. ranges = <0 0xd00 0x100>;
  1034. l4_cfg_clkctrl: clk@20 {
  1035. compatible = "ti,clkctrl";
  1036. reg = <0x20 0x14>;
  1037. #clock-cells = <2>;
  1038. };
  1039. };
  1040. l3_instr_cm: l3_instr_cm@e00 {
  1041. compatible = "ti,omap4-cm";
  1042. reg = <0xe00 0x100>;
  1043. #address-cells = <1>;
  1044. #size-cells = <1>;
  1045. ranges = <0 0xe00 0x100>;
  1046. l3_instr_clkctrl: clk@20 {
  1047. compatible = "ti,clkctrl";
  1048. reg = <0x20 0x24>;
  1049. #clock-cells = <2>;
  1050. };
  1051. };
  1052. ivahd_cm: ivahd_cm@f00 {
  1053. compatible = "ti,omap4-cm";
  1054. reg = <0xf00 0x100>;
  1055. #address-cells = <1>;
  1056. #size-cells = <1>;
  1057. ranges = <0 0xf00 0x100>;
  1058. ivahd_clkctrl: clk@20 {
  1059. compatible = "ti,clkctrl";
  1060. reg = <0x20 0xc>;
  1061. #clock-cells = <2>;
  1062. };
  1063. };
  1064. iss_cm: iss_cm@1000 {
  1065. compatible = "ti,omap4-cm";
  1066. reg = <0x1000 0x100>;
  1067. #address-cells = <1>;
  1068. #size-cells = <1>;
  1069. ranges = <0 0x1000 0x100>;
  1070. iss_clkctrl: clk@20 {
  1071. compatible = "ti,clkctrl";
  1072. reg = <0x20 0xc>;
  1073. #clock-cells = <2>;
  1074. };
  1075. };
  1076. l3_dss_cm: l3_dss_cm@1100 {
  1077. compatible = "ti,omap4-cm";
  1078. reg = <0x1100 0x100>;
  1079. #address-cells = <1>;
  1080. #size-cells = <1>;
  1081. ranges = <0 0x1100 0x100>;
  1082. l3_dss_clkctrl: clk@20 {
  1083. compatible = "ti,clkctrl";
  1084. reg = <0x20 0x4>;
  1085. #clock-cells = <2>;
  1086. };
  1087. };
  1088. l3_gfx_cm: l3_gfx_cm@1200 {
  1089. compatible = "ti,omap4-cm";
  1090. reg = <0x1200 0x100>;
  1091. #address-cells = <1>;
  1092. #size-cells = <1>;
  1093. ranges = <0 0x1200 0x100>;
  1094. l3_gfx_clkctrl: clk@20 {
  1095. compatible = "ti,clkctrl";
  1096. reg = <0x20 0x4>;
  1097. #clock-cells = <2>;
  1098. };
  1099. };
  1100. l3_init_cm: l3_init_cm@1300 {
  1101. compatible = "ti,omap4-cm";
  1102. reg = <0x1300 0x100>;
  1103. #address-cells = <1>;
  1104. #size-cells = <1>;
  1105. ranges = <0 0x1300 0x100>;
  1106. l3_init_clkctrl: clk@20 {
  1107. compatible = "ti,clkctrl";
  1108. reg = <0x20 0xc4>;
  1109. #clock-cells = <2>;
  1110. };
  1111. };
  1112. l4_per_cm: l4_per_cm@1400 {
  1113. compatible = "ti,omap4-cm";
  1114. reg = <0x1400 0x200>;
  1115. #address-cells = <1>;
  1116. #size-cells = <1>;
  1117. ranges = <0 0x1400 0x200>;
  1118. l4_per_clkctrl: clock@20 {
  1119. compatible = "ti,clkctrl-l4-per", "ti,clkctrl";
  1120. reg = <0x20 0x144>;
  1121. #clock-cells = <2>;
  1122. };
  1123. l4_secure_clkctrl: clock@1a0 {
  1124. compatible = "ti,clkctrl-l4-secure", "ti,clkctrl";
  1125. reg = <0x1a0 0x3c>;
  1126. #clock-cells = <2>;
  1127. };
  1128. };
  1129. };
  1130. &prm {
  1131. l4_wkup_cm: l4_wkup_cm@1800 {
  1132. compatible = "ti,omap4-cm";
  1133. reg = <0x1800 0x100>;
  1134. #address-cells = <1>;
  1135. #size-cells = <1>;
  1136. ranges = <0 0x1800 0x100>;
  1137. l4_wkup_clkctrl: clk@20 {
  1138. compatible = "ti,clkctrl";
  1139. reg = <0x20 0x5c>;
  1140. #clock-cells = <2>;
  1141. };
  1142. };
  1143. emu_sys_cm: emu_sys_cm@1a00 {
  1144. compatible = "ti,omap4-cm";
  1145. reg = <0x1a00 0x100>;
  1146. #address-cells = <1>;
  1147. #size-cells = <1>;
  1148. ranges = <0 0x1a00 0x100>;
  1149. emu_sys_clkctrl: clk@20 {
  1150. compatible = "ti,clkctrl";
  1151. reg = <0x20 0x4>;
  1152. #clock-cells = <2>;
  1153. };
  1154. };
  1155. };