omap4460.dtsi 3.4 KB

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  1. /*
  2. * Device Tree Source for OMAP4460 SoC
  3. *
  4. * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  5. *
  6. * This file is licensed under the terms of the GNU General Public License
  7. * version 2. This program is licensed "as is" without any warranty of any
  8. * kind, whether express or implied.
  9. */
  10. #include "omap4.dtsi"
  11. / {
  12. cpus {
  13. /* OMAP446x 'standard device' variants OPP50 to OPPTurbo */
  14. cpu0: cpu@0 {
  15. operating-points = <
  16. /* kHz uV */
  17. 350000 1025000
  18. 700000 1200000
  19. 920000 1313000
  20. >;
  21. clock-latency = <300000>; /* From legacy driver */
  22. /* cooling options */
  23. #cooling-cells = <2>; /* min followed by max */
  24. };
  25. };
  26. pmu {
  27. compatible = "arm,cortex-a9-pmu";
  28. interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
  29. <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
  30. ti,hwmods = "debugss";
  31. };
  32. thermal-zones {
  33. #include "omap4-cpu-thermal.dtsi"
  34. };
  35. ocp {
  36. bandgap: bandgap@4a002260 {
  37. reg = <0x4a002260 0x4
  38. 0x4a00232C 0x4
  39. 0x4a002378 0x18>;
  40. compatible = "ti,omap4460-bandgap";
  41. interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
  42. gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* tshut */
  43. #thermal-sensor-cells = <0>;
  44. };
  45. abb_mpu: regulator-abb-mpu {
  46. status = "okay";
  47. reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>,
  48. <0x4A002268 0x4>;
  49. reg-names = "base-address", "int-address",
  50. "efuse-address";
  51. ti,abb_info = <
  52. /*uV ABB efuse rbb_m fbb_m vset_m*/
  53. 1025000 0 0 0 0 0
  54. 1200000 0 0 0 0 0
  55. 1313000 0 0 0x100000 0x40000 0
  56. 1375000 1 0 0 0 0
  57. 1389000 1 0 0 0 0
  58. >;
  59. };
  60. abb_iva: regulator-abb-iva {
  61. status = "okay";
  62. reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>,
  63. <0x4A002268 0x4>;
  64. reg-names = "base-address", "int-address",
  65. "efuse-address";
  66. ti,abb_info = <
  67. /*uV ABB efuse rbb_m fbb_m vset_m*/
  68. 950000 0 0 0 0 0
  69. 1140000 0 0 0 0 0
  70. 1291000 0 0 0x200000 0 0
  71. 1375000 1 0 0 0 0
  72. 1376000 1 0 0 0 0
  73. >;
  74. };
  75. };
  76. };
  77. &cpu_thermal {
  78. coefficients = <348 (-9301)>;
  79. };
  80. /* Only some L4 CFG interconnect ranges are different on 4460 */
  81. &l4_cfg_segment_300000 {
  82. ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */
  83. <0x00040000 0x00340000 0x001000>, /* ap 68 */
  84. <0x00020000 0x00320000 0x004000>, /* ap 71 */
  85. <0x00024000 0x00324000 0x002000>, /* ap 72 */
  86. <0x00026000 0x00326000 0x001000>, /* ap 73 */
  87. <0x00027000 0x00327000 0x001000>, /* ap 74 */
  88. <0x00028000 0x00328000 0x001000>, /* ap 75 */
  89. <0x00029000 0x00329000 0x001000>, /* ap 76 */
  90. <0x00030000 0x00330000 0x010000>, /* ap 77 */
  91. <0x0002a000 0x0032a000 0x002000>, /* ap 90 */
  92. <0x0002c000 0x0032c000 0x004000>, /* ap 91 */
  93. <0x00010000 0x00310000 0x008000>, /* ap 92 */
  94. <0x00018000 0x00318000 0x004000>, /* ap 93 */
  95. <0x0001c000 0x0031c000 0x002000>, /* ap 94 */
  96. <0x0001e000 0x0031e000 0x002000>; /* ap 95 */
  97. };
  98. &l4_cfg_target_0 {
  99. ranges = <0x00000000 0x00000000 0x00010000>,
  100. <0x00010000 0x00010000 0x00008000>,
  101. <0x00018000 0x00018000 0x00004000>,
  102. <0x0001c000 0x0001c000 0x00002000>,
  103. <0x0001e000 0x0001e000 0x00002000>,
  104. <0x00020000 0x00020000 0x00004000>,
  105. <0x00024000 0x00024000 0x00002000>,
  106. <0x00026000 0x00026000 0x00001000>,
  107. <0x00027000 0x00027000 0x00001000>,
  108. <0x00028000 0x00028000 0x00001000>,
  109. <0x00029000 0x00029000 0x00001000>,
  110. <0x0002a000 0x0002a000 0x00002000>,
  111. <0x0002c000 0x0002c000 0x00004000>,
  112. <0x00030000 0x00030000 0x00010000>;
  113. };
  114. /include/ "omap446x-clocks.dtsi"