omap4-l4-abe.dtsi 15 KB

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  1. &l4_abe { /* 0x40100000 */
  2. compatible = "ti,omap4-l4-abe", "simple-bus";
  3. reg = <0x40100000 0x400>,
  4. <0x40100400 0x400>;
  5. reg-names = "la", "ap";
  6. #address-cells = <1>;
  7. #size-cells = <1>;
  8. ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
  9. <0x49000000 0x49000000 0x100000>;
  10. segment@0 { /* 0x40100000 */
  11. compatible = "simple-bus";
  12. #address-cells = <1>;
  13. #size-cells = <1>;
  14. ranges =
  15. /* CPU to L4 ABE mapping */
  16. <0x00000000 0x00000000 0x000400>, /* ap 0 */
  17. <0x00000400 0x00000400 0x000400>, /* ap 1 */
  18. <0x00022000 0x00022000 0x001000>, /* ap 2 */
  19. <0x00023000 0x00023000 0x001000>, /* ap 3 */
  20. <0x00024000 0x00024000 0x001000>, /* ap 4 */
  21. <0x00025000 0x00025000 0x001000>, /* ap 5 */
  22. <0x00026000 0x00026000 0x001000>, /* ap 6 */
  23. <0x00027000 0x00027000 0x001000>, /* ap 7 */
  24. <0x00028000 0x00028000 0x001000>, /* ap 8 */
  25. <0x00029000 0x00029000 0x001000>, /* ap 9 */
  26. <0x0002a000 0x0002a000 0x001000>, /* ap 10 */
  27. <0x0002b000 0x0002b000 0x001000>, /* ap 11 */
  28. <0x0002e000 0x0002e000 0x001000>, /* ap 12 */
  29. <0x0002f000 0x0002f000 0x001000>, /* ap 13 */
  30. <0x00030000 0x00030000 0x001000>, /* ap 14 */
  31. <0x00031000 0x00031000 0x001000>, /* ap 15 */
  32. <0x00032000 0x00032000 0x001000>, /* ap 16 */
  33. <0x00033000 0x00033000 0x001000>, /* ap 17 */
  34. <0x00038000 0x00038000 0x001000>, /* ap 18 */
  35. <0x00039000 0x00039000 0x001000>, /* ap 19 */
  36. <0x0003a000 0x0003a000 0x001000>, /* ap 20 */
  37. <0x0003b000 0x0003b000 0x001000>, /* ap 21 */
  38. <0x0003c000 0x0003c000 0x001000>, /* ap 22 */
  39. <0x0003d000 0x0003d000 0x001000>, /* ap 23 */
  40. <0x0003e000 0x0003e000 0x001000>, /* ap 24 */
  41. <0x0003f000 0x0003f000 0x001000>, /* ap 25 */
  42. <0x00080000 0x00080000 0x010000>, /* ap 26 */
  43. <0x00080000 0x00080000 0x001000>, /* ap 27 */
  44. <0x000a0000 0x000a0000 0x010000>, /* ap 28 */
  45. <0x000a0000 0x000a0000 0x001000>, /* ap 29 */
  46. <0x000c0000 0x000c0000 0x010000>, /* ap 30 */
  47. <0x000c0000 0x000c0000 0x001000>, /* ap 31 */
  48. <0x000f1000 0x000f1000 0x001000>, /* ap 32 */
  49. <0x000f2000 0x000f2000 0x001000>, /* ap 33 */
  50. /* L3 to L4 ABE mapping */
  51. <0x49000000 0x49000000 0x000400>, /* ap 0 */
  52. <0x49000400 0x49000400 0x000400>, /* ap 1 */
  53. <0x49022000 0x49022000 0x001000>, /* ap 2 */
  54. <0x49023000 0x49023000 0x001000>, /* ap 3 */
  55. <0x49024000 0x49024000 0x001000>, /* ap 4 */
  56. <0x49025000 0x49025000 0x001000>, /* ap 5 */
  57. <0x49026000 0x49026000 0x001000>, /* ap 6 */
  58. <0x49027000 0x49027000 0x001000>, /* ap 7 */
  59. <0x49028000 0x49028000 0x001000>, /* ap 8 */
  60. <0x49029000 0x49029000 0x001000>, /* ap 9 */
  61. <0x4902a000 0x4902a000 0x001000>, /* ap 10 */
  62. <0x4902b000 0x4902b000 0x001000>, /* ap 11 */
  63. <0x4902e000 0x4902e000 0x001000>, /* ap 12 */
  64. <0x4902f000 0x4902f000 0x001000>, /* ap 13 */
  65. <0x49030000 0x49030000 0x001000>, /* ap 14 */
  66. <0x49031000 0x49031000 0x001000>, /* ap 15 */
  67. <0x49032000 0x49032000 0x001000>, /* ap 16 */
  68. <0x49033000 0x49033000 0x001000>, /* ap 17 */
  69. <0x49038000 0x49038000 0x001000>, /* ap 18 */
  70. <0x49039000 0x49039000 0x001000>, /* ap 19 */
  71. <0x4903a000 0x4903a000 0x001000>, /* ap 20 */
  72. <0x4903b000 0x4903b000 0x001000>, /* ap 21 */
  73. <0x4903c000 0x4903c000 0x001000>, /* ap 22 */
  74. <0x4903d000 0x4903d000 0x001000>, /* ap 23 */
  75. <0x4903e000 0x4903e000 0x001000>, /* ap 24 */
  76. <0x4903f000 0x4903f000 0x001000>, /* ap 25 */
  77. <0x49080000 0x49080000 0x010000>, /* ap 26 */
  78. <0x49080000 0x49080000 0x001000>, /* ap 27 */
  79. <0x490a0000 0x490a0000 0x010000>, /* ap 28 */
  80. <0x490a0000 0x490a0000 0x001000>, /* ap 29 */
  81. <0x490c0000 0x490c0000 0x010000>, /* ap 30 */
  82. <0x490c0000 0x490c0000 0x001000>, /* ap 31 */
  83. <0x490f1000 0x490f1000 0x001000>, /* ap 32 */
  84. <0x490f2000 0x490f2000 0x001000>; /* ap 33 */
  85. target-module@22000 { /* 0x40122000, ap 2 02.0 */
  86. compatible = "ti,sysc-omap2", "ti,sysc";
  87. reg = <0x2208c 0x4>;
  88. reg-names = "sysc";
  89. ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  90. SYSC_OMAP2_ENAWAKEUP |
  91. SYSC_OMAP2_SOFTRESET)>;
  92. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  93. <SYSC_IDLE_NO>,
  94. <SYSC_IDLE_SMART>;
  95. /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
  96. clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 0>;
  97. clock-names = "fck";
  98. #address-cells = <1>;
  99. #size-cells = <1>;
  100. ranges = <0x0 0x22000 0x1000>,
  101. <0x49022000 0x49022000 0x1000>;
  102. mcbsp1: mcbsp@0 {
  103. compatible = "ti,omap4-mcbsp";
  104. reg = <0x0 0xff>, /* MPU private access */
  105. <0x49022000 0xff>; /* L3 Interconnect */
  106. reg-names = "mpu", "dma";
  107. interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  108. interrupt-names = "common";
  109. ti,buffer-size = <128>;
  110. dmas = <&sdma 33>,
  111. <&sdma 34>;
  112. dma-names = "tx", "rx";
  113. status = "disabled";
  114. };
  115. };
  116. target-module@24000 { /* 0x40124000, ap 4 04.0 */
  117. compatible = "ti,sysc-omap2", "ti,sysc";
  118. reg = <0x2408c 0x4>;
  119. reg-names = "sysc";
  120. ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  121. SYSC_OMAP2_ENAWAKEUP |
  122. SYSC_OMAP2_SOFTRESET)>;
  123. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  124. <SYSC_IDLE_NO>,
  125. <SYSC_IDLE_SMART>;
  126. /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
  127. clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 0>;
  128. clock-names = "fck";
  129. #address-cells = <1>;
  130. #size-cells = <1>;
  131. ranges = <0x0 0x24000 0x1000>,
  132. <0x49024000 0x49024000 0x1000>;
  133. mcbsp2: mcbsp@0 {
  134. compatible = "ti,omap4-mcbsp";
  135. reg = <0x0 0xff>, /* MPU private access */
  136. <0x49024000 0xff>; /* L3 Interconnect */
  137. reg-names = "mpu", "dma";
  138. interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
  139. interrupt-names = "common";
  140. ti,buffer-size = <128>;
  141. dmas = <&sdma 17>,
  142. <&sdma 18>;
  143. dma-names = "tx", "rx";
  144. status = "disabled";
  145. };
  146. };
  147. target-module@26000 { /* 0x40126000, ap 6 06.0 */
  148. compatible = "ti,sysc-omap2", "ti,sysc";
  149. reg = <0x2608c 0x4>;
  150. reg-names = "sysc";
  151. ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  152. SYSC_OMAP2_ENAWAKEUP |
  153. SYSC_OMAP2_SOFTRESET)>;
  154. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  155. <SYSC_IDLE_NO>,
  156. <SYSC_IDLE_SMART>;
  157. /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
  158. clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 0>;
  159. clock-names = "fck";
  160. #address-cells = <1>;
  161. #size-cells = <1>;
  162. ranges = <0x0 0x26000 0x1000>,
  163. <0x49026000 0x49026000 0x1000>;
  164. mcbsp3: mcbsp@0 {
  165. compatible = "ti,omap4-mcbsp";
  166. reg = <0x0 0xff>, /* MPU private access */
  167. <0x49026000 0xff>; /* L3 Interconnect */
  168. reg-names = "mpu", "dma";
  169. interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
  170. interrupt-names = "common";
  171. ti,buffer-size = <128>;
  172. dmas = <&sdma 19>,
  173. <&sdma 20>;
  174. dma-names = "tx", "rx";
  175. status = "disabled";
  176. };
  177. };
  178. target-module@28000 { /* 0x40128000, ap 8 08.0 */
  179. compatible = "ti,sysc-mcasp", "ti,sysc";
  180. reg = <0x28000 0x4>,
  181. <0x28004 0x4>;
  182. reg-names = "rev", "sysc";
  183. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  184. <SYSC_IDLE_NO>,
  185. <SYSC_IDLE_SMART>,
  186. <SYSC_IDLE_SMART_WKUP>;
  187. /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
  188. clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>;
  189. clock-names = "fck";
  190. #address-cells = <1>;
  191. #size-cells = <1>;
  192. ranges = <0x0 0x28000 0x1000>,
  193. <0x49028000 0x49028000 0x1000>;
  194. /*
  195. * Child device unsupported by davinci-mcasp. At least
  196. * RX path is disabled for omap4, and only DIT mode
  197. * works with no I2S. See also old Android kernel
  198. * omap-mcasp driver for more information.
  199. */
  200. };
  201. target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */
  202. compatible = "ti,sysc";
  203. status = "disabled";
  204. #address-cells = <1>;
  205. #size-cells = <1>;
  206. ranges = <0x0 0x2a000 0x1000>,
  207. <0x4902a000 0x4902a000 0x1000>;
  208. };
  209. target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */
  210. compatible = "ti,sysc-omap4", "ti,sysc";
  211. reg = <0x2e000 0x4>,
  212. <0x2e010 0x4>;
  213. reg-names = "rev", "sysc";
  214. ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
  215. SYSC_OMAP4_SOFTRESET)>;
  216. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  217. <SYSC_IDLE_NO>,
  218. <SYSC_IDLE_SMART>,
  219. <SYSC_IDLE_SMART_WKUP>;
  220. /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
  221. clocks = <&abe_clkctrl OMAP4_DMIC_CLKCTRL 0>;
  222. clock-names = "fck";
  223. #address-cells = <1>;
  224. #size-cells = <1>;
  225. ranges = <0x0 0x2e000 0x1000>,
  226. <0x4902e000 0x4902e000 0x1000>;
  227. dmic: dmic@0 {
  228. compatible = "ti,omap4-dmic";
  229. reg = <0x0 0x7f>, /* MPU private access */
  230. <0x4902e000 0x7f>; /* L3 Interconnect */
  231. reg-names = "mpu", "dma";
  232. interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
  233. dmas = <&sdma 67>;
  234. dma-names = "up_link";
  235. status = "disabled";
  236. };
  237. };
  238. target-module@30000 { /* 0x40130000, ap 14 0e.0 */
  239. compatible = "ti,sysc-omap2", "ti,sysc";
  240. reg = <0x30000 0x4>,
  241. <0x30010 0x4>,
  242. <0x30014 0x4>;
  243. reg-names = "rev", "sysc", "syss";
  244. ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
  245. SYSC_OMAP2_SOFTRESET)>;
  246. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  247. <SYSC_IDLE_NO>,
  248. <SYSC_IDLE_SMART>,
  249. <SYSC_IDLE_SMART_WKUP>;
  250. ti,syss-mask = <1>;
  251. /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
  252. clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>;
  253. clock-names = "fck";
  254. #address-cells = <1>;
  255. #size-cells = <1>;
  256. ranges = <0x0 0x30000 0x1000>,
  257. <0x49030000 0x49030000 0x1000>;
  258. wdt3: wdt@0 {
  259. compatible = "ti,omap4-wdt", "ti,omap3-wdt";
  260. reg = <0x0 0x80>;
  261. interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
  262. };
  263. };
  264. mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */
  265. compatible = "ti,sysc-omap4", "ti,sysc";
  266. reg = <0x32000 0x4>,
  267. <0x32010 0x4>;
  268. reg-names = "rev", "sysc";
  269. ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
  270. SYSC_OMAP4_SOFTRESET)>;
  271. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  272. <SYSC_IDLE_NO>,
  273. <SYSC_IDLE_SMART>,
  274. <SYSC_IDLE_SMART_WKUP>;
  275. /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
  276. clocks = <&abe_clkctrl OMAP4_MCPDM_CLKCTRL 0>;
  277. clock-names = "fck";
  278. #address-cells = <1>;
  279. #size-cells = <1>;
  280. ranges = <0x0 0x32000 0x1000>,
  281. <0x49032000 0x49032000 0x1000>;
  282. /* Must be only enabled for boards with pdmclk wired */
  283. status = "disabled";
  284. mcpdm: mcpdm@0 {
  285. compatible = "ti,omap4-mcpdm";
  286. reg = <0x0 0x7f>, /* MPU private access */
  287. <0x49032000 0x7f>; /* L3 Interconnect */
  288. reg-names = "mpu", "dma";
  289. interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
  290. dmas = <&sdma 65>,
  291. <&sdma 66>;
  292. dma-names = "up_link", "dn_link";
  293. };
  294. };
  295. target-module@38000 { /* 0x40138000, ap 18 12.0 */
  296. compatible = "ti,sysc-omap4-timer", "ti,sysc";
  297. reg = <0x38000 0x4>,
  298. <0x38010 0x4>;
  299. reg-names = "rev", "sysc";
  300. ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
  301. SYSC_OMAP4_SOFTRESET)>;
  302. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  303. <SYSC_IDLE_NO>,
  304. <SYSC_IDLE_SMART>,
  305. <SYSC_IDLE_SMART_WKUP>;
  306. /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
  307. clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 0>;
  308. clock-names = "fck";
  309. #address-cells = <1>;
  310. #size-cells = <1>;
  311. ranges = <0x0 0x38000 0x1000>,
  312. <0x49038000 0x49038000 0x1000>;
  313. timer5: timer@0 {
  314. compatible = "ti,omap4430-timer";
  315. reg = <0x00000000 0x80>,
  316. <0x49038000 0x80>;
  317. clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 24>;
  318. clock-names = "fck";
  319. interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
  320. ti,timer-dsp;
  321. };
  322. };
  323. target-module@3a000 { /* 0x4013a000, ap 20 14.0 */
  324. compatible = "ti,sysc-omap4-timer", "ti,sysc";
  325. reg = <0x3a000 0x4>,
  326. <0x3a010 0x4>;
  327. reg-names = "rev", "sysc";
  328. ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
  329. SYSC_OMAP4_SOFTRESET)>;
  330. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  331. <SYSC_IDLE_NO>,
  332. <SYSC_IDLE_SMART>,
  333. <SYSC_IDLE_SMART_WKUP>;
  334. /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
  335. clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 0>;
  336. clock-names = "fck";
  337. #address-cells = <1>;
  338. #size-cells = <1>;
  339. ranges = <0x0 0x3a000 0x1000>,
  340. <0x4903a000 0x4903a000 0x1000>;
  341. timer6: timer@0 {
  342. compatible = "ti,omap4430-timer";
  343. reg = <0x00000000 0x80>,
  344. <0x4903a000 0x80>;
  345. clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 24>;
  346. clock-names = "fck";
  347. interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
  348. ti,timer-dsp;
  349. };
  350. };
  351. target-module@3c000 { /* 0x4013c000, ap 22 16.0 */
  352. compatible = "ti,sysc-omap4-timer", "ti,sysc";
  353. reg = <0x3c000 0x4>,
  354. <0x3c010 0x4>;
  355. reg-names = "rev", "sysc";
  356. ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
  357. SYSC_OMAP4_SOFTRESET)>;
  358. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  359. <SYSC_IDLE_NO>,
  360. <SYSC_IDLE_SMART>,
  361. <SYSC_IDLE_SMART_WKUP>;
  362. /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
  363. clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 0>;
  364. clock-names = "fck";
  365. #address-cells = <1>;
  366. #size-cells = <1>;
  367. ranges = <0x0 0x3c000 0x1000>,
  368. <0x4903c000 0x4903c000 0x1000>;
  369. timer7: timer@0 {
  370. compatible = "ti,omap4430-timer";
  371. reg = <0x00000000 0x80>,
  372. <0x4903c000 0x80>;
  373. clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 24>;
  374. clock-names = "fck";
  375. interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
  376. ti,timer-dsp;
  377. };
  378. };
  379. target-module@3e000 { /* 0x4013e000, ap 24 18.0 */
  380. compatible = "ti,sysc-omap4-timer", "ti,sysc";
  381. reg = <0x3e000 0x4>,
  382. <0x3e010 0x4>;
  383. reg-names = "rev", "sysc";
  384. ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
  385. SYSC_OMAP4_SOFTRESET)>;
  386. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  387. <SYSC_IDLE_NO>,
  388. <SYSC_IDLE_SMART>,
  389. <SYSC_IDLE_SMART_WKUP>;
  390. /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
  391. clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 0>;
  392. clock-names = "fck";
  393. #address-cells = <1>;
  394. #size-cells = <1>;
  395. ranges = <0x0 0x3e000 0x1000>,
  396. <0x4903e000 0x4903e000 0x1000>;
  397. timer8: timer@0 {
  398. compatible = "ti,omap4430-timer";
  399. reg = <0x00000000 0x80>,
  400. <0x4903e000 0x80>;
  401. clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
  402. clock-names = "fck";
  403. interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
  404. ti,timer-pwm;
  405. ti,timer-dsp;
  406. };
  407. };
  408. target-module@80000 { /* 0x40180000, ap 26 1a.0 */
  409. compatible = "ti,sysc";
  410. status = "disabled";
  411. #address-cells = <1>;
  412. #size-cells = <1>;
  413. ranges = <0x0 0x80000 0x10000>,
  414. <0x49080000 0x49080000 0x10000>;
  415. };
  416. target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */
  417. compatible = "ti,sysc";
  418. status = "disabled";
  419. #address-cells = <1>;
  420. #size-cells = <1>;
  421. ranges = <0x0 0xa0000 0x10000>,
  422. <0x490a0000 0x490a0000 0x10000>;
  423. };
  424. target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */
  425. compatible = "ti,sysc";
  426. status = "disabled";
  427. #address-cells = <1>;
  428. #size-cells = <1>;
  429. ranges = <0x0 0xc0000 0x10000>,
  430. <0x490c0000 0x490c0000 0x10000>;
  431. };
  432. target-module@f1000 { /* 0x401f1000, ap 32 20.0 */
  433. compatible = "ti,sysc-omap4", "ti,sysc";
  434. reg = <0xf1000 0x4>,
  435. <0xf1010 0x4>;
  436. reg-names = "rev", "sysc";
  437. ti,sysc-midle = <SYSC_IDLE_FORCE>,
  438. <SYSC_IDLE_NO>,
  439. <SYSC_IDLE_SMART>,
  440. <SYSC_IDLE_SMART_WKUP>;
  441. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  442. <SYSC_IDLE_NO>,
  443. <SYSC_IDLE_SMART>;
  444. /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
  445. clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>;
  446. clock-names = "fck";
  447. #address-cells = <1>;
  448. #size-cells = <1>;
  449. ranges = <0x0 0xf1000 0x1000>,
  450. <0x490f1000 0x490f1000 0x1000>;
  451. /*
  452. * No child device binding or driver in mainline.
  453. * See Android tree and related upstreaming efforts
  454. * for the old driver.
  455. */
  456. };
  457. };
  458. };