katmai.c 20 KB

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  1. /*
  2. * (C) Copyright 2007-2008
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. *
  23. */
  24. #include <common.h>
  25. #include <ppc4xx.h>
  26. #include <i2c.h>
  27. #include <libfdt.h>
  28. #include <fdt_support.h>
  29. #include <netdev.h>
  30. #include <asm/processor.h>
  31. #include <asm/io.h>
  32. #include <asm/gpio.h>
  33. #include <asm/4xx_pcie.h>
  34. DECLARE_GLOBAL_DATA_PTR;
  35. int board_early_init_f (void)
  36. {
  37. unsigned long mfr;
  38. /*----------------------------------------------------------------------+
  39. * Interrupt controller setup for the Katmai 440SPe Evaluation board.
  40. *-----------------------------------------------------------------------+
  41. *-----------------------------------------------------------------------+
  42. * Interrupt | Source | Pol. | Sensi.| Crit. |
  43. *-----------+-----------------------------------+-------+-------+-------+
  44. * IRQ 00 | UART0 | High | Level | Non |
  45. * IRQ 01 | UART1 | High | Level | Non |
  46. * IRQ 02 | IIC0 | High | Level | Non |
  47. * IRQ 03 | IIC1 | High | Level | Non |
  48. * IRQ 04 | PCI0X0 MSG IN | High | Level | Non |
  49. * IRQ 05 | PCI0X0 CMD Write | High | Level | Non |
  50. * IRQ 06 | PCI0X0 Power Mgt | High | Level | Non |
  51. * IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non |
  52. * IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non |
  53. * IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non |
  54. * IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non |
  55. * IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit |
  56. * IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non |
  57. * IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non |
  58. * IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non |
  59. * IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non |
  60. * IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non |
  61. * IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit |
  62. * IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non |
  63. * IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non |
  64. * IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non |
  65. * IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non |
  66. * IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non |
  67. * IRQ 23 | I2O Inbound Doorbell | High | Level | Non |
  68. * IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non |
  69. * IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non |
  70. * IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non |
  71. * IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non |
  72. * IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non |
  73. * IRQ 29 | GPT Down Count Timer | Rising| Edge | Non |
  74. * IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non |
  75. * IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. |
  76. *------------------------------------------------------------------------
  77. * IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non |
  78. * IRQ 33 | MAL Serr | High | Level | Non |
  79. * IRQ 34 | MAL Txde | High | Level | Non |
  80. * IRQ 35 | MAL Rxde | High | Level | Non |
  81. * IRQ 36 | DMC CE or DMC UE | High | Level | Non |
  82. * IRQ 37 | EBC or UART2 | High |Lvl Edg| Non |
  83. * IRQ 38 | MAL TX EOB | High | Level | Non |
  84. * IRQ 39 | MAL RX EOB | High | Level | Non |
  85. * IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non |
  86. * IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non |
  87. * IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non |
  88. * IRQ 43 | L2 Cache | Risin | Edge | Non |
  89. * IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non |
  90. * IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non |
  91. * IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non |
  92. * IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
  93. * IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
  94. * IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non |
  95. * IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non |
  96. * IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non |
  97. * IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
  98. * IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non |
  99. * IRQ 54 | DMA Error | High | Level | Non |
  100. * IRQ 55 | DMA I2O Error | High | Level | Non |
  101. * IRQ 56 | Serial ROM | High | Level | Non |
  102. * IRQ 57 | PCIX0 Error | High | Edge | Non |
  103. * IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non |
  104. * IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non |
  105. * IRQ 60 | EMAC0 Interrupt | High | Level | Non |
  106. * IRQ 61 | EMAC0 Wake-up | High | Level | Non |
  107. * IRQ 62 | Reserved | High | Level | Non |
  108. * IRQ 63 | XOR | High | Level | Non |
  109. *-----------------------------------------------------------------------
  110. * IRQ 64 | PE0 AL | High | Level | Non |
  111. * IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
  112. * IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
  113. * IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
  114. * IRQ 68 | PE0 TCR | High | Level | Non |
  115. * IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
  116. * IRQ 70 | PE0 DCR Error | High | Level | Non |
  117. * IRQ 71 | Reserved | N/A | N/A | Non |
  118. * IRQ 72 | PE1 AL | High | Level | Non |
  119. * IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
  120. * IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
  121. * IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
  122. * IRQ 76 | PE1 TCR | High | Level | Non |
  123. * IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
  124. * IRQ 78 | PE1 DCR Error | High | Level | Non |
  125. * IRQ 79 | Reserved | N/A | N/A | Non |
  126. * IRQ 80 | PE2 AL | High | Level | Non |
  127. * IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
  128. * IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
  129. * IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
  130. * IRQ 84 | PE2 TCR | High | Level | Non |
  131. * IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
  132. * IRQ 86 | PE2 DCR Error | High | Level | Non |
  133. * IRQ 87 | Reserved | N/A | N/A | Non |
  134. * IRQ 88 | External IRQ(5) | Progr | Progr | Non |
  135. * IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
  136. * IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
  137. * IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
  138. * IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
  139. * IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
  140. * IRQ 94 | Reserved | N/A | N/A | Non |
  141. * IRQ 95 | Reserved | N/A | N/A | Non |
  142. *-----------------------------------------------------------------------
  143. * IRQ 96 | PE0 INTA | High | Level | Non |
  144. * IRQ 97 | PE0 INTB | High | Level | Non |
  145. * IRQ 98 | PE0 INTC | High | Level | Non |
  146. * IRQ 99 | PE0 INTD | High | Level | Non |
  147. * IRQ 100 | PE1 INTA | High | Level | Non |
  148. * IRQ 101 | PE1 INTB | High | Level | Non |
  149. * IRQ 102 | PE1 INTC | High | Level | Non |
  150. * IRQ 103 | PE1 INTD | High | Level | Non |
  151. * IRQ 104 | PE2 INTA | High | Level | Non |
  152. * IRQ 105 | PE2 INTB | High | Level | Non |
  153. * IRQ 106 | PE2 INTC | High | Level | Non |
  154. * IRQ 107 | PE2 INTD | Risin | Edge | Non |
  155. * IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non |
  156. * IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non |
  157. * IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non |
  158. * IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non |
  159. * IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non |
  160. * IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non |
  161. * IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non |
  162. * IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non |
  163. * IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non |
  164. * IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non |
  165. * IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non |
  166. * IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non |
  167. * IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non |
  168. * IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non |
  169. * IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non |
  170. * IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non |
  171. * IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non |
  172. * IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non |
  173. * IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non |
  174. * IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non |
  175. *-----------+-----------------------------------+-------+-------+-------+ */
  176. /*-------------------------------------------------------------------------+
  177. * Put UICs in PowerPC440SPemode.
  178. * Initialise UIC registers. Clear all interrupts. Disable all interrupts.
  179. * Set critical interrupt values. Set interrupt polarities. Set interrupt
  180. * trigger levels. Make bit 0 High priority. Clear all interrupts again.
  181. *------------------------------------------------------------------------*/
  182. mtdcr (uic3sr, 0xffffffff); /* Clear all interrupts */
  183. mtdcr (uic3er, 0x00000000); /* disable all interrupts */
  184. mtdcr (uic3cr, 0x00000000); /* Set Critical / Non Critical interrupts: */
  185. mtdcr (uic3pr, 0xffffffff); /* Set Interrupt Polarities*/
  186. mtdcr (uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */
  187. mtdcr (uic3vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
  188. mtdcr (uic3sr, 0x00000000); /* clear all interrupts*/
  189. mtdcr (uic3sr, 0xffffffff); /* clear all interrupts*/
  190. mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
  191. mtdcr (uic2er, 0x00000000); /* disable all interrupts*/
  192. mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts*/
  193. mtdcr (uic2pr, 0xebebebff); /* Set Interrupt Polarities*/
  194. mtdcr (uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */
  195. mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
  196. mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
  197. mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
  198. mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts*/
  199. mtdcr (uic1er, 0x00000000); /* disable all interrupts*/
  200. mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts*/
  201. mtdcr (uic1pr, 0xffffffff); /* Set Interrupt Polarities */
  202. mtdcr (uic1tr, 0x001f8040); /* Set Interrupt Trigger Levels*/
  203. mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
  204. mtdcr (uic1sr, 0x00000000); /* clear all interrupts*/
  205. mtdcr (uic1sr, 0xffffffff); /* clear all interrupts*/
  206. mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
  207. mtdcr (uic0er, 0x00000000); /* disable all interrupts excepted cascade to be checked */
  208. mtdcr (uic0cr, 0x00104001); /* Set Critical / Non Critical interrupts*/
  209. mtdcr (uic0pr, 0xffffffff); /* Set Interrupt Polarities*/
  210. mtdcr (uic0tr, 0x010f0004); /* Set Interrupt Trigger Levels */
  211. mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
  212. mtdcr (uic0sr, 0x00000000); /* clear all interrupts*/
  213. mtdcr (uic0sr, 0xffffffff); /* clear all interrupts*/
  214. mfsdr(sdr_mfr, mfr);
  215. mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
  216. mtsdr(sdr_mfr, mfr);
  217. mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0);
  218. out32(GPIO0_OR, CONFIG_SYS_GPIO_OR);
  219. out32(GPIO0_ODR, CONFIG_SYS_GPIO_ODR);
  220. out32(GPIO0_TCR, CONFIG_SYS_GPIO_TCR);
  221. return 0;
  222. }
  223. int checkboard (void)
  224. {
  225. char *s = getenv("serial#");
  226. printf("Board: Katmai - AMCC 440SPe Evaluation Board");
  227. if (s != NULL) {
  228. puts(", serial# ");
  229. puts(s);
  230. }
  231. putc('\n');
  232. return 0;
  233. }
  234. /*
  235. * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
  236. * board specific values.
  237. */
  238. u32 ddr_wrdtr(u32 default_val) {
  239. return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
  240. }
  241. u32 ddr_clktr(u32 default_val) {
  242. return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
  243. }
  244. /*************************************************************************
  245. * pci_pre_init
  246. *
  247. * This routine is called just prior to registering the hose and gives
  248. * the board the opportunity to check things. Returning a value of zero
  249. * indicates that things are bad & PCI initialization should be aborted.
  250. *
  251. * Different boards may wish to customize the pci controller structure
  252. * (add regions, override default access routines, etc) or perform
  253. * certain pre-initialization actions.
  254. *
  255. ************************************************************************/
  256. #if defined(CONFIG_PCI)
  257. int pci_pre_init(struct pci_controller * hose )
  258. {
  259. unsigned long strap;
  260. /*-------------------------------------------------------------------+
  261. * The katmai board is always configured as the host & requires the
  262. * PCI arbiter to be enabled.
  263. *-------------------------------------------------------------------*/
  264. mfsdr(sdr_sdstp1, strap);
  265. if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
  266. printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
  267. return 0;
  268. }
  269. return 1;
  270. }
  271. #endif /* defined(CONFIG_PCI) */
  272. /*************************************************************************
  273. * pci_target_init
  274. *
  275. * The bootstrap configuration provides default settings for the pci
  276. * inbound map (PIM). But the bootstrap config choices are limited and
  277. * may not be sufficient for a given board.
  278. *
  279. ************************************************************************/
  280. #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
  281. void pci_target_init(struct pci_controller * hose )
  282. {
  283. /*-------------------------------------------------------------------+
  284. * Disable everything
  285. *-------------------------------------------------------------------*/
  286. out32r( PCIX0_PIM0SA, 0 ); /* disable */
  287. out32r( PCIX0_PIM1SA, 0 ); /* disable */
  288. out32r( PCIX0_PIM2SA, 0 ); /* disable */
  289. out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
  290. /*-------------------------------------------------------------------+
  291. * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
  292. * strapping options to not support sizes such as 128/256 MB.
  293. *-------------------------------------------------------------------*/
  294. out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
  295. out32r( PCIX0_PIM0LAH, 0 );
  296. out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
  297. out32r( PCIX0_BAR0, 0 );
  298. /*-------------------------------------------------------------------+
  299. * Program the board's subsystem id/vendor id
  300. *-------------------------------------------------------------------*/
  301. out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
  302. out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
  303. out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
  304. }
  305. #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
  306. #if defined(CONFIG_PCI)
  307. /*************************************************************************
  308. * is_pci_host
  309. *
  310. * This routine is called to determine if a pci scan should be
  311. * performed. With various hardware environments (especially cPCI and
  312. * PPMC) it's insufficient to depend on the state of the arbiter enable
  313. * bit in the strap register, or generic host/adapter assumptions.
  314. *
  315. * Rather than hard-code a bad assumption in the general 440 code, the
  316. * 440 pci code requires the board to decide at runtime.
  317. *
  318. * Return 0 for adapter mode, non-zero for host (monarch) mode.
  319. *
  320. *
  321. ************************************************************************/
  322. int is_pci_host(struct pci_controller *hose)
  323. {
  324. /* The katmai board is always configured as host. */
  325. return 1;
  326. }
  327. static int katmai_pcie_card_present(int port)
  328. {
  329. u32 val;
  330. val = in32(GPIO0_IR);
  331. switch (port) {
  332. case 0:
  333. return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0));
  334. case 1:
  335. return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1));
  336. case 2:
  337. return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2));
  338. default:
  339. return 0;
  340. }
  341. }
  342. static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
  343. void pcie_setup_hoses(int busno)
  344. {
  345. struct pci_controller *hose;
  346. int i, bus;
  347. int ret = 0;
  348. char *env;
  349. unsigned int delay;
  350. /*
  351. * assume we're called after the PCIX hose is initialized, which takes
  352. * bus ID 0 and therefore start numbering PCIe's from 1.
  353. */
  354. bus = busno;
  355. for (i = 0; i <= 2; i++) {
  356. /* Check for katmai card presence */
  357. if (!katmai_pcie_card_present(i))
  358. continue;
  359. if (is_end_point(i))
  360. ret = ppc4xx_init_pcie_endport(i);
  361. else
  362. ret = ppc4xx_init_pcie_rootport(i);
  363. if (ret) {
  364. printf("PCIE%d: initialization as %s failed\n", i,
  365. is_end_point(i) ? "endpoint" : "root-complex");
  366. continue;
  367. }
  368. hose = &pcie_hose[i];
  369. hose->first_busno = bus;
  370. hose->last_busno = bus;
  371. hose->current_busno = bus;
  372. /* setup mem resource */
  373. pci_set_region(hose->regions + 0,
  374. CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
  375. CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
  376. CONFIG_SYS_PCIE_MEMSIZE,
  377. PCI_REGION_MEM);
  378. hose->region_count = 1;
  379. pci_register_hose(hose);
  380. if (is_end_point(i)) {
  381. ppc4xx_setup_pcie_endpoint(hose, i);
  382. /*
  383. * Reson for no scanning is endpoint can not generate
  384. * upstream configuration accesses.
  385. */
  386. } else {
  387. ppc4xx_setup_pcie_rootpoint(hose, i);
  388. env = getenv ("pciscandelay");
  389. if (env != NULL) {
  390. delay = simple_strtoul(env, NULL, 10);
  391. if (delay > 5)
  392. printf("Warning, expect noticable delay before "
  393. "PCIe scan due to 'pciscandelay' value!\n");
  394. mdelay(delay * 1000);
  395. }
  396. /*
  397. * Config access can only go down stream
  398. */
  399. hose->last_busno = pci_hose_scan(hose);
  400. bus = hose->last_busno + 1;
  401. }
  402. }
  403. }
  404. #endif /* defined(CONFIG_PCI) */
  405. #ifdef CONFIG_POST
  406. /*
  407. * Returns 1 if keys pressed to start the power-on long-running tests
  408. * Called from board_init_f().
  409. */
  410. int post_hotkeys_pressed(void)
  411. {
  412. return (ctrlc());
  413. }
  414. #endif
  415. int board_eth_init(bd_t *bis)
  416. {
  417. return pci_eth_init(bis);
  418. }