init.S 4.8 KB

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  1. /*
  2. * (C) Copyright 2007
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #include <ppc_asm.tmpl>
  26. #include <config.h>
  27. #include <asm-ppc/mmu.h>
  28. /**************************************************************************
  29. * TLB TABLE
  30. *
  31. * This table is used by the cpu boot code to setup the initial tlb
  32. * entries. Rather than make broad assumptions in the cpu source tree,
  33. * this table lets each board set things up however they like.
  34. *
  35. * Pointer to the table is returned in r1
  36. *
  37. *************************************************************************/
  38. .section .bootpg,"ax"
  39. /**************************************************************************
  40. * TLB table for revA
  41. *************************************************************************/
  42. .globl tlbtabA
  43. tlbtabA:
  44. tlbtab_start
  45. /*
  46. * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
  47. * speed up boot process. It is patched after relocation to enable SA_I
  48. */
  49. tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
  50. /*
  51. * TLB entries for SDRAM are not needed on this platform.
  52. * They are dynamically generated in the SPD DDR(2) detection
  53. * routine.
  54. */
  55. tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
  56. tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
  57. tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
  58. tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
  59. tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
  60. tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
  61. tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
  62. tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
  63. tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
  64. tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
  65. tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
  66. tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
  67. tlbtab_end
  68. /**************************************************************************
  69. * TLB table for revB
  70. *
  71. * Notice: revB of the 440SPe chip is very strict about PLB real addresses
  72. * and ranges to be mapped for config space: it seems to only work with
  73. * d_nnnn_nnnn range (hangs the core upon config transaction attempts when
  74. * set otherwise) while revA uses c_nnnn_nnnn.
  75. *************************************************************************/
  76. .globl tlbtabB
  77. tlbtabB:
  78. tlbtab_start
  79. /*
  80. * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
  81. * speed up boot process. It is patched after relocation to enable SA_I
  82. */
  83. tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
  84. /*
  85. * TLB entries for SDRAM are not needed on this platform.
  86. * They are dynamically generated in the SPD DDR(2) detection
  87. * routine.
  88. */
  89. tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
  90. tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
  91. tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K, CONFIG_SYS_ACE_BASE, 4,AC_R|AC_W|SA_G|SA_I)
  92. tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
  93. tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
  94. tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
  95. tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
  96. tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
  97. tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
  98. tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
  99. tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
  100. tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
  101. tlbtab_end