canyonlands.c 13 KB

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  1. /*
  2. * (C) Copyright 2008
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License as
  7. * published by the Free Software Foundation; either version 2 of
  8. * the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18. * MA 02111-1307 USA
  19. */
  20. #include <common.h>
  21. #include <ppc440.h>
  22. #include <libfdt.h>
  23. #include <fdt_support.h>
  24. #include <i2c.h>
  25. #include <asm/processor.h>
  26. #include <asm/io.h>
  27. #include <asm/mmu.h>
  28. #include <asm/4xx_pcie.h>
  29. #include <asm/gpio.h>
  30. extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
  31. DECLARE_GLOBAL_DATA_PTR;
  32. #define CONFIG_SYS_BCSR3_PCIE 0x10
  33. #define BOARD_CANYONLANDS_PCIE 1
  34. #define BOARD_CANYONLANDS_SATA 2
  35. #define BOARD_GLACIER 3
  36. int board_early_init_f(void)
  37. {
  38. u32 sdr0_cust0;
  39. u32 pvr = get_pvr();
  40. /*
  41. * Setup the interrupt controller polarities, triggers, etc.
  42. */
  43. mtdcr(uic0sr, 0xffffffff); /* clear all */
  44. mtdcr(uic0er, 0x00000000); /* disable all */
  45. mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
  46. mtdcr(uic0pr, 0xffffffff); /* per ref-board manual */
  47. mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
  48. mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
  49. mtdcr(uic0sr, 0xffffffff); /* clear all */
  50. mtdcr(uic1sr, 0xffffffff); /* clear all */
  51. mtdcr(uic1er, 0x00000000); /* disable all */
  52. mtdcr(uic1cr, 0x00000000); /* all non-critical */
  53. mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
  54. mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
  55. mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
  56. mtdcr(uic1sr, 0xffffffff); /* clear all */
  57. mtdcr(uic2sr, 0xffffffff); /* clear all */
  58. mtdcr(uic2er, 0x00000000); /* disable all */
  59. mtdcr(uic2cr, 0x00000000); /* all non-critical */
  60. mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
  61. mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
  62. mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
  63. mtdcr(uic2sr, 0xffffffff); /* clear all */
  64. mtdcr(uic3sr, 0xffffffff); /* clear all */
  65. mtdcr(uic3er, 0x00000000); /* disable all */
  66. mtdcr(uic3cr, 0x00000000); /* all non-critical */
  67. mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */
  68. mtdcr(uic3tr, 0x00000000); /* per ref-board manual */
  69. mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
  70. mtdcr(uic3sr, 0xffffffff); /* clear all */
  71. /* SDR Setting - enable NDFC */
  72. mfsdr(SDR0_CUST0, sdr0_cust0);
  73. sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
  74. SDR0_CUST0_NDFC_ENABLE |
  75. SDR0_CUST0_NDFC_BW_8_BIT |
  76. SDR0_CUST0_NDFC_ARE_MASK |
  77. SDR0_CUST0_NDFC_BAC_ENCODE(3) |
  78. (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
  79. mtsdr(SDR0_CUST0, sdr0_cust0);
  80. /*
  81. * Configure PFC (Pin Function Control) registers
  82. * UART0: 4 pins
  83. */
  84. mtsdr(SDR0_PFC1, 0x00040000);
  85. /* Enable PCI host functionality in SDR0_PCI0 */
  86. mtsdr(SDR0_PCI0, 0xe0000000);
  87. /* Enable ethernet and take out of reset */
  88. out_8((void *)CONFIG_SYS_BCSR_BASE + 6, 0);
  89. /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
  90. out_8((void *)CONFIG_SYS_BCSR_BASE + 5, 0);
  91. /* Enable USB host & USB-OTG */
  92. out_8((void *)CONFIG_SYS_BCSR_BASE + 7, 0);
  93. mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
  94. /* Setup PLB4-AHB bridge based on the system address map */
  95. mtdcr(AHB_TOP, 0x8000004B);
  96. mtdcr(AHB_BOT, 0x8000004B);
  97. if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) {
  98. /*
  99. * Configure USB-STP pins as alternate and not GPIO
  100. * It seems to be neccessary to configure the STP pins as GPIO
  101. * input at powerup (perhaps while USB reset is asserted). So
  102. * we configure those pins to their "real" function now.
  103. */
  104. gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
  105. gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
  106. }
  107. return 0;
  108. }
  109. static void canyonlands_sata_init(int board_type)
  110. {
  111. u32 reg;
  112. if (board_type == BOARD_CANYONLANDS_SATA) {
  113. /* Put SATA in reset */
  114. SDR_WRITE(SDR0_SRST1, 0x00020001);
  115. /* Set the phy for SATA, not PCI-E port 0 */
  116. reg = SDR_READ(PESDR0_PHY_CTL_RST);
  117. SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001);
  118. reg = SDR_READ(PESDR0_L0CLK);
  119. SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007);
  120. SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111);
  121. SDR_WRITE(PESDR0_L0DRV, 0x00000104);
  122. /* Bring SATA out of reset */
  123. SDR_WRITE(SDR0_SRST1, 0x00000000);
  124. }
  125. }
  126. int checkboard(void)
  127. {
  128. char *s = getenv("serial#");
  129. u32 pvr = get_pvr();
  130. if ((pvr == PVR_460GT_RA) || (pvr == PVR_460GT_SE_RA)) {
  131. printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
  132. gd->board_type = BOARD_GLACIER;
  133. } else {
  134. printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
  135. if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 3)) & CONFIG_SYS_BCSR3_PCIE)
  136. gd->board_type = BOARD_CANYONLANDS_PCIE;
  137. else
  138. gd->board_type = BOARD_CANYONLANDS_SATA;
  139. }
  140. switch (gd->board_type) {
  141. case BOARD_CANYONLANDS_PCIE:
  142. case BOARD_GLACIER:
  143. puts(", 2*PCIe");
  144. break;
  145. case BOARD_CANYONLANDS_SATA:
  146. puts(", 1*PCIe/1*SATA");
  147. break;
  148. }
  149. printf(", Rev. %X", in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)));
  150. if (s != NULL) {
  151. puts(", serial# ");
  152. puts(s);
  153. }
  154. putc('\n');
  155. canyonlands_sata_init(gd->board_type);
  156. return (0);
  157. }
  158. /*
  159. * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
  160. * board specific values.
  161. */
  162. u32 ddr_wrdtr(u32 default_val) {
  163. return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
  164. }
  165. u32 ddr_clktr(u32 default_val) {
  166. return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
  167. }
  168. #if defined(CONFIG_NAND_U_BOOT)
  169. /*
  170. * NAND booting U-Boot version uses a fixed initialization, since the whole
  171. * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
  172. * code.
  173. */
  174. phys_size_t initdram(int board_type)
  175. {
  176. return CONFIG_SYS_MBYTES_SDRAM << 20;
  177. }
  178. #endif
  179. /*
  180. * pci_target_init
  181. *
  182. * The bootstrap configuration provides default settings for the pci
  183. * inbound map (PIM). But the bootstrap config choices are limited and
  184. * may not be sufficient for a given board.
  185. */
  186. #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
  187. void pci_target_init(struct pci_controller * hose )
  188. {
  189. /*
  190. * Disable everything
  191. */
  192. out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
  193. out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
  194. out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
  195. out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
  196. /*
  197. * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
  198. * strapping options to not support sizes such as 128/256 MB.
  199. */
  200. out_le32((void *)PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
  201. out_le32((void *)PCIX0_PIM0LAH, 0);
  202. out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
  203. out_le32((void *)PCIX0_BAR0, 0);
  204. /*
  205. * Program the board's subsystem id/vendor id
  206. */
  207. out_le16((void *)PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
  208. out_le16((void *)PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
  209. out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
  210. }
  211. #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
  212. #if defined(CONFIG_PCI)
  213. /*
  214. * is_pci_host
  215. *
  216. * This routine is called to determine if a pci scan should be
  217. * performed. With various hardware environments (especially cPCI and
  218. * PPMC) it's insufficient to depend on the state of the arbiter enable
  219. * bit in the strap register, or generic host/adapter assumptions.
  220. *
  221. * Rather than hard-code a bad assumption in the general 440 code, the
  222. * 440 pci code requires the board to decide at runtime.
  223. *
  224. * Return 0 for adapter mode, non-zero for host (monarch) mode.
  225. */
  226. int is_pci_host(struct pci_controller *hose)
  227. {
  228. /* Board is always configured as host. */
  229. return (1);
  230. }
  231. static struct pci_controller pcie_hose[2] = {{0},{0}};
  232. void pcie_setup_hoses(int busno)
  233. {
  234. struct pci_controller *hose;
  235. int i, bus;
  236. int ret = 0;
  237. char *env;
  238. unsigned int delay;
  239. int start;
  240. /*
  241. * assume we're called after the PCIX hose is initialized, which takes
  242. * bus ID 0 and therefore start numbering PCIe's from 1.
  243. */
  244. bus = busno;
  245. /*
  246. * Canyonlands with SATA enabled has only one PCIe slot
  247. * (2nd one).
  248. */
  249. if (gd->board_type == BOARD_CANYONLANDS_SATA)
  250. start = 1;
  251. else
  252. start = 0;
  253. for (i = start; i <= 1; i++) {
  254. if (is_end_point(i))
  255. ret = ppc4xx_init_pcie_endport(i);
  256. else
  257. ret = ppc4xx_init_pcie_rootport(i);
  258. if (ret) {
  259. printf("PCIE%d: initialization as %s failed\n", i,
  260. is_end_point(i) ? "endpoint" : "root-complex");
  261. continue;
  262. }
  263. hose = &pcie_hose[i];
  264. hose->first_busno = bus;
  265. hose->last_busno = bus;
  266. hose->current_busno = bus;
  267. /* setup mem resource */
  268. pci_set_region(hose->regions + 0,
  269. CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
  270. CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
  271. CONFIG_SYS_PCIE_MEMSIZE,
  272. PCI_REGION_MEM);
  273. hose->region_count = 1;
  274. pci_register_hose(hose);
  275. if (is_end_point(i)) {
  276. ppc4xx_setup_pcie_endpoint(hose, i);
  277. /*
  278. * Reson for no scanning is endpoint can not generate
  279. * upstream configuration accesses.
  280. */
  281. } else {
  282. ppc4xx_setup_pcie_rootpoint(hose, i);
  283. env = getenv ("pciscandelay");
  284. if (env != NULL) {
  285. delay = simple_strtoul(env, NULL, 10);
  286. if (delay > 5)
  287. printf("Warning, expect noticable delay before "
  288. "PCIe scan due to 'pciscandelay' value!\n");
  289. mdelay(delay * 1000);
  290. }
  291. /*
  292. * Config access can only go down stream
  293. */
  294. hose->last_busno = pci_hose_scan(hose);
  295. bus = hose->last_busno + 1;
  296. }
  297. }
  298. }
  299. #endif /* CONFIG_PCI */
  300. int board_early_init_r (void)
  301. {
  302. /*
  303. * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
  304. * boot EBC mapping only supports a maximum of 16MBytes
  305. * (4.ff00.0000 - 4.ffff.ffff).
  306. * To solve this problem, the FLASH has to get remapped to another
  307. * EBC address which accepts bigger regions:
  308. *
  309. * 0xfc00.0000 -> 4.cc00.0000
  310. */
  311. /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
  312. #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
  313. mtebc(pb3cr, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
  314. #else
  315. mtebc(pb0cr, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
  316. #endif
  317. /* Remove TLB entry of boot EBC mapping */
  318. remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
  319. /* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
  320. program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE,
  321. TLB_WORD2_I_ENABLE);
  322. /*
  323. * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
  324. * 0xfc00.0000 is possible
  325. */
  326. /*
  327. * Clear potential errors resulting from auto-calibration.
  328. * If not done, then we could get an interrupt later on when
  329. * exceptions are enabled.
  330. */
  331. set_mcsr(get_mcsr());
  332. return 0;
  333. }
  334. int misc_init_r(void)
  335. {
  336. u32 sdr0_srst1 = 0;
  337. u32 eth_cfg;
  338. u32 pvr = get_pvr();
  339. u8 val;
  340. /*
  341. * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
  342. * This is board specific, so let's do it here.
  343. */
  344. mfsdr(SDR0_ETH_CFG, eth_cfg);
  345. /* disable SGMII mode */
  346. eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
  347. SDR0_ETH_CFG_SGMII1_ENABLE |
  348. SDR0_ETH_CFG_SGMII0_ENABLE);
  349. /* Set the for 2 RGMII mode */
  350. /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
  351. eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
  352. if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA))
  353. eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
  354. else
  355. eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
  356. mtsdr(SDR0_ETH_CFG, eth_cfg);
  357. /*
  358. * The AHB Bridge core is held in reset after power-on or reset
  359. * so enable it now
  360. */
  361. mfsdr(SDR0_SRST1, sdr0_srst1);
  362. sdr0_srst1 &= ~SDR0_SRST1_AHB;
  363. mtsdr(SDR0_SRST1, sdr0_srst1);
  364. /*
  365. * RTC/M41T62:
  366. * Disable square wave output: Batterie will be drained
  367. * quickly, when this output is not disabled
  368. */
  369. val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa);
  370. val &= ~0x40;
  371. i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val);
  372. return 0;
  373. }
  374. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  375. void ft_board_setup(void *blob, bd_t *bd)
  376. {
  377. u32 val[4];
  378. int rc;
  379. ft_cpu_setup(blob, bd);
  380. /* Fixup NOR mapping */
  381. val[0] = 0; /* chip select number */
  382. val[1] = 0; /* always 0 */
  383. val[2] = CONFIG_SYS_FLASH_BASE_PHYS_L; /* we fixed up this address */
  384. val[3] = gd->bd->bi_flashsize;
  385. rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
  386. val, sizeof(val), 1);
  387. if (rc) {
  388. printf("Unable to update property NOR mapping, err=%s\n",
  389. fdt_strerror(rc));
  390. }
  391. if (gd->board_type == BOARD_CANYONLANDS_SATA) {
  392. /*
  393. * When SATA is selected we need to disable the first PCIe
  394. * node in the device tree, so that Linux doesn't initialize
  395. * it.
  396. */
  397. fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
  398. "disabled", sizeof("disabled"), 1);
  399. }
  400. if (gd->board_type == BOARD_CANYONLANDS_PCIE) {
  401. /*
  402. * When PCIe is selected we need to disable the SATA
  403. * node in the device tree, so that Linux doesn't initialize
  404. * it.
  405. */
  406. fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
  407. "disabled", sizeof("disabled"), 1);
  408. }
  409. }
  410. #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */