ads5121.c 9.8 KB

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  1. /*
  2. * (C) Copyright 2007 DENX Software Engineering
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. *
  22. */
  23. #include <common.h>
  24. #include <mpc512x.h>
  25. #include <asm/bitops.h>
  26. #include <command.h>
  27. #include <asm/processor.h>
  28. #include <fdt_support.h>
  29. #ifdef CONFIG_MISC_INIT_R
  30. #include <i2c.h>
  31. #endif
  32. /* Clocks in use */
  33. #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
  34. CLOCK_SCCR1_LPC_EN | \
  35. CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
  36. CLOCK_SCCR1_PSCFIFO_EN | \
  37. CLOCK_SCCR1_DDR_EN | \
  38. CLOCK_SCCR1_FEC_EN | \
  39. CLOCK_SCCR1_PCI_EN | \
  40. CLOCK_SCCR1_TPR_EN)
  41. #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
  42. CLOCK_SCCR2_SPDIF_EN | \
  43. CLOCK_SCCR2_DIU_EN | \
  44. CLOCK_SCCR2_I2C_EN)
  45. #define CSAW_START(start) ((start) & 0xFFFF0000)
  46. #define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
  47. long int fixed_sdram(void);
  48. int board_early_init_f (void)
  49. {
  50. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  51. u32 lpcaw;
  52. /*
  53. * Initialize Local Window for the CPLD registers access (CS2 selects
  54. * the CPLD chip)
  55. */
  56. im->sysconf.lpcs2aw = CSAW_START(CONFIG_SYS_CPLD_BASE) |
  57. CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE);
  58. im->lpc.cs_cfg[2] = CONFIG_SYS_CS2_CFG;
  59. /*
  60. * According to MPC5121e RM, configuring local access windows should
  61. * be followed by a dummy read of the config register that was
  62. * modified last and an isync
  63. */
  64. lpcaw = im->sysconf.lpcs2aw;
  65. __asm__ __volatile__ ("isync");
  66. /*
  67. * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
  68. *
  69. * Without this the flash identification routine fails, as it needs to issue
  70. * write commands in order to establish the device ID.
  71. */
  72. #ifdef CONFIG_ADS5121_REV2
  73. *((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0xC1;
  74. #else
  75. if (*((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
  76. *((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0xC1;
  77. } else {
  78. /* running from Backup flash */
  79. *((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0x32;
  80. }
  81. #endif
  82. /*
  83. * Configure Flash Speed
  84. */
  85. *((volatile u32 *)(CONFIG_SYS_IMMR + LPC_OFFSET + CS0_CONFIG)) = CONFIG_SYS_CS0_CFG;
  86. if (SVR_MJREV (im->sysconf.spridr) >= 2) {
  87. *((volatile u32 *)(CONFIG_SYS_IMMR + LPC_OFFSET + CS_ALE_TIMING_CONFIG)) = CONFIG_SYS_CS_ALETIMING;
  88. }
  89. /*
  90. * Enable clocks
  91. */
  92. im->clk.sccr[0] = SCCR1_CLOCKS_EN;
  93. im->clk.sccr[1] = SCCR2_CLOCKS_EN;
  94. return 0;
  95. }
  96. phys_size_t initdram (int board_type)
  97. {
  98. u32 msize = 0;
  99. msize = fixed_sdram ();
  100. return msize;
  101. }
  102. /*
  103. * fixed sdram init -- the board doesn't use memory modules that have serial presence
  104. * detect or similar mechanism for discovery of the DRAM settings
  105. */
  106. long int fixed_sdram (void)
  107. {
  108. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  109. u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
  110. u32 msize_log2 = __ilog2 (msize);
  111. u32 i;
  112. /* Initialize IO Control */
  113. im->io_ctrl.regs[IOCTL_MEM/4] = IOCTRL_MUX_DDR;
  114. /* Initialize DDR Local Window */
  115. im->sysconf.ddrlaw.bar = CONFIG_SYS_DDR_BASE & 0xFFFFF000;
  116. im->sysconf.ddrlaw.ar = msize_log2 - 1;
  117. /*
  118. * According to MPC5121e RM, configuring local access windows should
  119. * be followed by a dummy read of the config register that was
  120. * modified last and an isync
  121. */
  122. i = im->sysconf.ddrlaw.ar;
  123. __asm__ __volatile__ ("isync");
  124. /* Enable DDR */
  125. im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_EN;
  126. /* Initialize DDR Priority Manager */
  127. im->mddrc.prioman_config1 = CONFIG_SYS_MDDRCGRP_PM_CFG1;
  128. im->mddrc.prioman_config2 = CONFIG_SYS_MDDRCGRP_PM_CFG2;
  129. im->mddrc.hiprio_config = CONFIG_SYS_MDDRCGRP_HIPRIO_CFG;
  130. im->mddrc.lut_table0_main_upper = CONFIG_SYS_MDDRCGRP_LUT0_MU;
  131. im->mddrc.lut_table0_main_lower = CONFIG_SYS_MDDRCGRP_LUT0_ML;
  132. im->mddrc.lut_table1_main_upper = CONFIG_SYS_MDDRCGRP_LUT1_MU;
  133. im->mddrc.lut_table1_main_lower = CONFIG_SYS_MDDRCGRP_LUT1_ML;
  134. im->mddrc.lut_table2_main_upper = CONFIG_SYS_MDDRCGRP_LUT2_MU;
  135. im->mddrc.lut_table2_main_lower = CONFIG_SYS_MDDRCGRP_LUT2_ML;
  136. im->mddrc.lut_table3_main_upper = CONFIG_SYS_MDDRCGRP_LUT3_MU;
  137. im->mddrc.lut_table3_main_lower = CONFIG_SYS_MDDRCGRP_LUT3_ML;
  138. im->mddrc.lut_table4_main_upper = CONFIG_SYS_MDDRCGRP_LUT4_MU;
  139. im->mddrc.lut_table4_main_lower = CONFIG_SYS_MDDRCGRP_LUT4_ML;
  140. im->mddrc.lut_table0_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT0_AU;
  141. im->mddrc.lut_table0_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT0_AL;
  142. im->mddrc.lut_table1_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT1_AU;
  143. im->mddrc.lut_table1_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT1_AL;
  144. im->mddrc.lut_table2_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT2_AU;
  145. im->mddrc.lut_table2_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT2_AL;
  146. im->mddrc.lut_table3_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT3_AU;
  147. im->mddrc.lut_table3_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT3_AL;
  148. im->mddrc.lut_table4_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT4_AU;
  149. im->mddrc.lut_table4_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT4_AL;
  150. /* Initialize MDDRC */
  151. im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG;
  152. im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0;
  153. im->mddrc.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1;
  154. im->mddrc.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2;
  155. /* Initialize DDR */
  156. for (i = 0; i < 10; i++)
  157. im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
  158. im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
  159. im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
  160. im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
  161. im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
  162. im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
  163. im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
  164. im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
  165. im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
  166. im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2;
  167. im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
  168. im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
  169. im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2;
  170. im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM3;
  171. im->mddrc.ddr_command = CONFIG_SYS_MICRON_EN_DLL;
  172. im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
  173. im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
  174. im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
  175. im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
  176. im->mddrc.ddr_command = CONFIG_SYS_MICRON_OCD_DEFAULT;
  177. im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
  178. im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
  179. /* Start MDDRC */
  180. im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0_RUN;
  181. im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_RUN;
  182. return msize;
  183. }
  184. int misc_init_r(void)
  185. {
  186. u8 tmp_val;
  187. extern int ads5121_diu_init(void);
  188. /* Using this for DIU init before the driver in linux takes over
  189. * Enable the TFP410 Encoder (I2C address 0x38)
  190. */
  191. i2c_set_bus_num(2);
  192. tmp_val = 0xBF;
  193. i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
  194. /* Verify if enabled */
  195. tmp_val = 0;
  196. i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
  197. debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
  198. tmp_val = 0x10;
  199. i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
  200. /* Verify if enabled */
  201. tmp_val = 0;
  202. i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
  203. debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
  204. #ifdef CONFIG_FSL_DIU_FB
  205. #if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
  206. ads5121_diu_init();
  207. #endif
  208. #endif
  209. return 0;
  210. }
  211. static iopin_t ioregs_init[] = {
  212. /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
  213. {
  214. IOCTL_SPDIF_TXCLK, 3, 0,
  215. IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  216. IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
  217. },
  218. /* Set highest Slew on 9 PATA pins */
  219. {
  220. IOCTL_PATA_CE1, 9, 1,
  221. IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  222. IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
  223. },
  224. /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
  225. {
  226. IOCTL_PSC0_0, 15, 0,
  227. IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  228. IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
  229. },
  230. /* FUNC1=SPDIF_TXCLK */
  231. {
  232. IOCTL_LPC_CS1, 1, 0,
  233. IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  234. IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
  235. },
  236. /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
  237. {
  238. IOCTL_I2C1_SCL, 2, 0,
  239. IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  240. IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
  241. },
  242. /* FUNC2=DIU CLK */
  243. {
  244. IOCTL_PSC6_0, 1, 0,
  245. IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  246. IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
  247. },
  248. /* FUNC2=DIU_HSYNC */
  249. {
  250. IOCTL_PSC6_1, 1, 0,
  251. IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  252. IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
  253. },
  254. /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
  255. {
  256. IOCTL_PSC6_4, 26, 0,
  257. IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  258. IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
  259. }
  260. };
  261. int checkboard (void)
  262. {
  263. ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
  264. uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
  265. printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
  266. brd_rev, cpld_rev);
  267. /* initialize function mux & slew rate IO inter alia on IO Pins */
  268. iopin_initialize(ioregs_init, sizeof(ioregs_init) / sizeof(ioregs_init[0]));
  269. return 0;
  270. }
  271. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  272. void ft_board_setup(void *blob, bd_t *bd)
  273. {
  274. ft_cpu_setup(blob, bd);
  275. fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
  276. }
  277. #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */