adder.c 3.6 KB

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  1. /*
  2. * Copyright (C) 2004-2005 Arabella Software Ltd.
  3. * Yuli Barcohen <yuli@arabellasw.com>
  4. *
  5. * Support for Analogue&Micro Adder boards family.
  6. * Tested on AdderII and Adder87x.
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. #include <common.h>
  27. #include <mpc8xx.h>
  28. #if defined(CONFIG_OF_LIBFDT)
  29. #include <libfdt.h>
  30. #endif
  31. /*
  32. * SDRAM is single Samsung K4S643232F-T70 chip (8MB)
  33. * or single Micron MT48LC4M32B2TG-7 chip (16MB).
  34. * Minimal CPU frequency is 40MHz.
  35. */
  36. static uint sdram_table[] = {
  37. /* Single read (offset 0x00 in UPM RAM) */
  38. 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00,
  39. 0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04,
  40. /* Burst read (offset 0x08 in UPM RAM) */
  41. 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00,
  42. 0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44,
  43. 0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35,
  44. 0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35,
  45. /* Single write (offset 0x18 in UPM RAM) */
  46. 0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47,
  47. 0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
  48. /* Burst write (offset 0x20 in UPM RAM) */
  49. 0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
  50. 0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04,
  51. 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
  52. 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
  53. /* Refresh (offset 0x30 in UPM RAM) */
  54. 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
  55. 0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
  56. 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
  57. /* Exception (offset 0x3C in UPM RAM) */
  58. 0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04
  59. };
  60. phys_size_t initdram (int board_type)
  61. {
  62. long int msize;
  63. volatile immap_t *immap = (volatile immap_t *)CONFIG_SYS_IMMR;
  64. volatile memctl8xx_t *memctl = &immap->im_memctl;
  65. upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
  66. /* Configure SDRAM refresh */
  67. memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */
  68. memctl->memc_mamr = (94 << 24) | CONFIG_SYS_MAMR; /* No refresh */
  69. udelay(200);
  70. /* Run precharge from location 0x15 */
  71. memctl->memc_mar = 0x0;
  72. memctl->memc_mcr = 0x80002115;
  73. udelay(200);
  74. /* Run 8 refresh cycles */
  75. memctl->memc_mcr = 0x80002830;
  76. udelay(200);
  77. /* Run MRS pattern from location 0x16 */
  78. memctl->memc_mar = 0x88;
  79. memctl->memc_mcr = 0x80002116;
  80. udelay(200);
  81. memctl->memc_mamr |= MAMR_PTAE; /* Enable refresh */
  82. memctl->memc_or1 = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
  83. memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
  84. msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE);
  85. memctl->memc_or1 |= ~(msize - 1);
  86. return msize;
  87. }
  88. int checkboard( void )
  89. {
  90. puts("Board: Adder");
  91. #if defined(CONFIG_MPC885_FAMILY)
  92. puts("87x\n");
  93. #elif defined(CONFIG_MPC866_FAMILY)
  94. puts("II\n");
  95. #endif
  96. return 0;
  97. }
  98. #if defined(CONFIG_OF_BOARD_SETUP)
  99. void ft_board_setup(void *blob, bd_t *bd)
  100. {
  101. ft_cpu_setup(blob, bd);
  102. }
  103. #endif