actux1.c 3.8 KB

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  1. /*
  2. * (C) Copyright 2007
  3. * Michael Schwingen, michael@schwingen.org
  4. *
  5. * (C) Copyright 2006
  6. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  7. *
  8. * (C) Copyright 2002
  9. * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  10. *
  11. * (C) Copyright 2002
  12. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  13. * Marius Groeger <mgroeger@sysgo.de>
  14. *
  15. * See file CREDITS for list of people who contributed to this
  16. * project.
  17. *
  18. * This program is free software; you can redistribute it and/or
  19. * modify it under the terms of the GNU General Public License as
  20. * published by the Free Software Foundation; either version 2 of
  21. * the License, or (at your option) any later version.
  22. *
  23. * This program is distributed in the hope that it will be useful,
  24. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  26. * GNU General Public License for more details.
  27. *
  28. * You should have received a copy of the GNU General Public License
  29. * along with this program; if not, write to the Free Software
  30. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  31. * MA 02111-1307 USA
  32. */
  33. #include <common.h>
  34. #include <command.h>
  35. #include <malloc.h>
  36. #include <asm/arch/ixp425.h>
  37. #include <asm/io.h>
  38. #include <miiphy.h>
  39. #include "actux1_hw.h"
  40. DECLARE_GLOBAL_DATA_PTR;
  41. int board_init (void)
  42. {
  43. gd->bd->bi_arch_number = MACH_TYPE_ACTUX1;
  44. /* adress of boot parameters */
  45. gd->bd->bi_boot_params = 0x00000100;
  46. GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
  47. GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
  48. /* Setup GPIO's for PCI INTA */
  49. GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI1_INTA);
  50. GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI1_INTA);
  51. /* Setup GPIO's for 33MHz clock output */
  52. GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
  53. GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
  54. *IXP425_GPIO_GPCLKR = 0x011001FF;
  55. /* CS5: Debug port */
  56. *IXP425_EXP_CS5 = 0x9d520003;
  57. /* CS6: HwRel */
  58. *IXP425_EXP_CS6 = 0x81860001;
  59. /* CS7: LEDs */
  60. *IXP425_EXP_CS7 = 0x80900003;
  61. udelay (533);
  62. GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
  63. ACTUX1_LED1 (2);
  64. ACTUX1_LED2 (2);
  65. ACTUX1_LED3 (0);
  66. ACTUX1_LED4 (0);
  67. ACTUX1_LED5 (0);
  68. ACTUX1_LED6 (0);
  69. ACTUX1_LED7 (0);
  70. ACTUX1_HS (ACTUX1_HS_DCD);
  71. return 0;
  72. }
  73. /*
  74. * Check Board Identity
  75. */
  76. int checkboard (void)
  77. {
  78. char *s = getenv ("serial#");
  79. puts ("Board: AcTux-1 rev.");
  80. putc (ACTUX1_BOARDREL + 'A' - 1);
  81. if (s != NULL) {
  82. puts (", serial# ");
  83. puts (s);
  84. }
  85. putc ('\n');
  86. return (0);
  87. }
  88. /*************************************************************************
  89. * get_board_rev() - setup to pass kernel board revision information
  90. * 0 = reserved
  91. * 1 = Rev. A
  92. * 2 = Rev. B
  93. *************************************************************************/
  94. u32 get_board_rev (void)
  95. {
  96. return ACTUX1_BOARDREL;
  97. }
  98. int dram_init (void)
  99. {
  100. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  101. gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  102. return (0);
  103. }
  104. #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
  105. extern struct pci_controller hose;
  106. extern void pci_ixp_init (struct pci_controller *hose);
  107. void pci_init_board (void)
  108. {
  109. extern void pci_ixp_init (struct pci_controller *hose);
  110. pci_ixp_init (&hose);
  111. }
  112. #endif
  113. void reset_phy (void)
  114. {
  115. u16 id1, id2;
  116. /* initialize the PHY */
  117. miiphy_reset ("NPE0", CONFIG_PHY_ADDR);
  118. miiphy_read ("NPE0", CONFIG_PHY_ADDR, PHY_PHYIDR1, &id1);
  119. miiphy_read ("NPE0", CONFIG_PHY_ADDR, PHY_PHYIDR2, &id2);
  120. id2 &= 0xFFF0; /* mask out revision bits */
  121. if (id1 == 0x13 && id2 == 0x78e0) {
  122. /*
  123. * LXT971/LXT972 PHY: set LED outputs:
  124. * LED1(green) = Link/ACT,
  125. * LED2 (unused) = LINK,
  126. * LED3(red) = Coll
  127. */
  128. miiphy_write ("NPE0", CONFIG_PHY_ADDR, 20, 0xD432);
  129. } else if (id1 == 0x143 && id2 == 0xbc30) {
  130. /* BCM5241: default values are OK */
  131. } else
  132. printf ("unknown ethernet PHY ID: %x %x\n", id1, id2);
  133. }