RRvision.c 6.0 KB

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  1. /*
  2. * (C) Copyright 2001-2002
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <mpc8xx.h>
  25. /* ------------------------------------------------------------------------- */
  26. static long int dram_size (long int, long int *, long int);
  27. /* ------------------------------------------------------------------------- */
  28. #define _NOT_USED_ 0xFFFFFFFF
  29. const uint sdram_table[] =
  30. {
  31. /*
  32. * Single Read. (Offset 0 in UPMA RAM)
  33. */
  34. 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
  35. 0x1FF77C47, /* last */
  36. /*
  37. * SDRAM Initialization (offset 5 in UPMA RAM)
  38. *
  39. * This is no UPM entry point. The following definition uses
  40. * the remaining space to establish an initialization
  41. * sequence, which is executed by a RUN command.
  42. *
  43. */
  44. 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
  45. /*
  46. * Burst Read. (Offset 8 in UPMA RAM)
  47. */
  48. 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
  49. 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
  50. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  51. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  52. /*
  53. * Single Write. (Offset 18 in UPMA RAM)
  54. */
  55. 0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
  56. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  57. /*
  58. * Burst Write. (Offset 20 in UPMA RAM)
  59. */
  60. 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
  61. 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
  62. _NOT_USED_,
  63. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  64. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  65. /*
  66. * Refresh (Offset 30 in UPMA RAM)
  67. */
  68. 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
  69. 0xFFFFFC84, 0xFFFFFC07, /* last */
  70. _NOT_USED_, _NOT_USED_,
  71. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  72. /*
  73. * Exception. (Offset 3c in UPMA RAM)
  74. */
  75. 0x7FFFFC07, /* last */
  76. _NOT_USED_, _NOT_USED_, _NOT_USED_,
  77. };
  78. /* ------------------------------------------------------------------------- */
  79. /*
  80. * Check Board Identity:
  81. *
  82. * Always return 1 (no second DRAM bank).
  83. */
  84. int checkboard (void)
  85. {
  86. char *s = getenv ("serial#");
  87. puts ("Board: RRvision ");
  88. for (; s && *s; ++s) {
  89. if (*s == ' ')
  90. break;
  91. putc (*s);
  92. }
  93. putc ('\n');
  94. return (0);
  95. }
  96. /* ------------------------------------------------------------------------- */
  97. phys_size_t initdram (int board_type)
  98. {
  99. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  100. volatile memctl8xx_t *memctl = &immap->im_memctl;
  101. unsigned long reg;
  102. long int size8, size9;
  103. long int size = 0;
  104. upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table) / sizeof(uint));
  105. /*
  106. * Preliminary prescaler for refresh (depends on number of
  107. * banks): This value is selected for four cycles every 62.4 us
  108. * with two SDRAM banks or four cycles every 31.2 us with one
  109. * bank. It will be adjusted after memory sizing.
  110. */
  111. memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
  112. memctl->memc_mar = 0x00000088;
  113. /*
  114. * Map controller bank 1 the SDRAM bank 2 at physical address 0.
  115. */
  116. memctl->memc_or1 = CONFIG_SYS_OR2_PRELIM;
  117. memctl->memc_br1 = CONFIG_SYS_BR2_PRELIM;
  118. memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
  119. udelay (200);
  120. /* perform SDRAM initializsation sequence */
  121. memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
  122. udelay (1);
  123. memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */
  124. udelay (1);
  125. memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
  126. udelay (1000);
  127. /*
  128. * Check Bank 0 Memory Size
  129. *
  130. * try 8 column mode
  131. */
  132. size8 = dram_size (CONFIG_SYS_MAMR_8COL,
  133. SDRAM_BASE2_PRELIM,
  134. SDRAM_MAX_SIZE);
  135. udelay (1000);
  136. /*
  137. * try 9 column mode
  138. */
  139. size9 = dram_size (CONFIG_SYS_MAMR_9COL,
  140. SDRAM_BASE2_PRELIM,
  141. SDRAM_MAX_SIZE);
  142. if (size8 < size9) { /* leave configuration at 9 columns */
  143. size = size9;
  144. /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
  145. } else { /* back to 8 columns */
  146. size = size8;
  147. memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
  148. udelay (500);
  149. /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
  150. }
  151. udelay (1000);
  152. /*
  153. * Adjust refresh rate depending on SDRAM type
  154. * For types > 128 MBit leave it at the current (fast) rate
  155. */
  156. if (size < 0x02000000) {
  157. /* reduce to 15.6 us (62.4 us / quad) */
  158. memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
  159. udelay (1000);
  160. }
  161. /*
  162. * Final mapping
  163. */
  164. memctl->memc_or1 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
  165. memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
  166. /*
  167. * No bank 1
  168. *
  169. * invalidate bank
  170. */
  171. memctl->memc_br3 = 0;
  172. /* adjust refresh rate depending on SDRAM type, one bank */
  173. reg = memctl->memc_mptpr;
  174. reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
  175. memctl->memc_mptpr = reg;
  176. udelay (10000);
  177. return (size);
  178. }
  179. /* ------------------------------------------------------------------------- */
  180. /*
  181. * Check memory range for valid RAM. A simple memory test determines
  182. * the actually available RAM size between addresses `base' and
  183. * `base + maxsize'. Some (not all) hardware errors are detected:
  184. * - short between address lines
  185. * - short between data lines
  186. */
  187. static long int dram_size (long int mamr_value, long int *base,
  188. long int maxsize)
  189. {
  190. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  191. volatile memctl8xx_t *memctl = &immap->im_memctl;
  192. memctl->memc_mamr = mamr_value;
  193. return (get_ram_size(base, maxsize));
  194. }