RPXlite_dw.c 4.7 KB

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  1. /*
  2. * (C) Copyright 2004
  3. * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * Sam Song
  25. * U-Boot port on RPXlite DW board : RPXlite_DW or LITE_DW
  26. * Tested on working at 64MHz(CPU)/32MHz(BUS),48MHz/24MHz
  27. * with 64MB, 2 SDRAM Micron chips,MT48LC16M16A2-75.
  28. */
  29. #include <common.h>
  30. #include <mpc8xx.h>
  31. /* ------------------------------------------------------------------------- */
  32. static long int dram_size (long int, long int *, long int);
  33. /* ------------------------------------------------------------------------- */
  34. #define _NOT_USED_ 0xFFFFCC25
  35. const uint sdram_table[] =
  36. {
  37. /*
  38. * Single Read. (Offset 00h in UPMA RAM)
  39. */
  40. 0x0F03CC04, 0x00ACCC24, 0x1FF74C20, /* last */
  41. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  42. _NOT_USED_,
  43. /*
  44. * Burst Read. (Offset 08h in UPMA RAM)
  45. */
  46. 0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20,
  47. 0x01FFCC20, 0x1FF74C20, /* last */
  48. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  49. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  50. _NOT_USED_, _NOT_USED_,
  51. /*
  52. * Single Write. (Offset 18h in UPMA RAM)
  53. */
  54. 0x0F03CC02, 0x00AC0C24, 0x1FF74C25, /* last */
  55. _NOT_USED_, _NOT_USED_, 0x0FA00C34,0x0FFFCC35,
  56. _NOT_USED_,
  57. /*
  58. * Burst Write. (Offset 20h in UPMA RAM)
  59. */
  60. 0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22,
  61. 0x01FFFC24, 0x1FF74C25, /* last */
  62. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  63. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  64. _NOT_USED_, _NOT_USED_,
  65. /*
  66. * Refresh. (Offset 30h in UPMA RAM)
  67. */
  68. 0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_,
  69. _NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34,
  70. 0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34, 0x0FFFCCB4,
  71. /* INIT sequence RAM WORDS
  72. * SDRAM Initialization (offset 0x36 in UPMA RAM)
  73. * The above definition uses the remaining space
  74. * to establish an initialization sequence,
  75. * which is executed by a RUN command.
  76. * The sequence is COMMAND INHIBIT(NOP),Precharge,
  77. * Load Mode Register,NOP,Auto Refresh.
  78. */
  79. /*
  80. * Exception. (Offset 3Ch in UPMA RAM)
  81. */
  82. 0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_
  83. };
  84. /*
  85. * Check Board Identity:
  86. */
  87. int checkboard (void)
  88. {
  89. puts ("Board: RPXlite_DW\n") ;
  90. return (0) ;
  91. }
  92. /* ------------------------------------------------------------------------- */
  93. phys_size_t initdram (int board_type)
  94. {
  95. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  96. volatile memctl8xx_t *memctl = &immap->im_memctl;
  97. long int size9;
  98. upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
  99. /* Refresh clock prescalar */
  100. memctl->memc_mptpr = CONFIG_SYS_MPTPR ;
  101. memctl->memc_mar = 0x00000088;
  102. /* Map controller banks 1 to the SDRAM bank */
  103. memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
  104. memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
  105. memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
  106. /*Disable Periodic timer A. */
  107. udelay(200);
  108. /* perform SDRAM initializsation sequence */
  109. memctl->memc_mcr = 0x80002236; /* SDRAM bank 0 - refresh twice */
  110. udelay(1);
  111. memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
  112. /*Enable Periodic timer A */
  113. udelay (1000);
  114. /* Check Bank 0 Memory Size
  115. * try 9 column mode
  116. */
  117. size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
  118. /*
  119. * Final mapping:
  120. */
  121. memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
  122. udelay (1000);
  123. return (size9);
  124. }
  125. void rpxlite_init (void)
  126. {
  127. /* Enable NVRAM */
  128. *((uchar *) BCSR0) |= BCSR0_ENNVRAM;
  129. }
  130. /*
  131. * Check memory range for valid RAM. A simple memory test determines
  132. * the actually available RAM size between addresses `base' and
  133. * `base + maxsize'. Some (not all) hardware errors are detected:
  134. * - short between address lines
  135. * - short between data lines
  136. */
  137. static long int dram_size (long int mamr_value, long int *base,
  138. long int maxsize)
  139. {
  140. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  141. volatile memctl8xx_t *memctl = &immap->im_memctl;
  142. memctl->memc_mamr = mamr_value;
  143. return (get_ram_size (base, maxsize));
  144. }