RPXClassic.c 6.6 KB

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  1. /*
  2. * (C) Copyright 2001
  3. * Stäubli Faverges - <www.staubli.com>
  4. * Pierre AUBERT p.aubert@staubli.com
  5. * U-Boot port on RPXClassic LF (CLLF_BW31) board
  6. *
  7. * (C) Copyright 2000
  8. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  9. *
  10. * See file CREDITS for list of people who contributed to this
  11. * project.
  12. *
  13. * This program is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License as
  15. * published by the Free Software Foundation; either version 2 of
  16. * the License, or (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26. * MA 02111-1307 USA
  27. */
  28. #include <common.h>
  29. #include <i2c.h>
  30. #include <config.h>
  31. #include <mpc8xx.h>
  32. /* ------------------------------------------------------------------------- */
  33. static long int dram_size (long int, long int *, long int);
  34. static unsigned char aschex_to_byte (unsigned char *cp);
  35. /* ------------------------------------------------------------------------- */
  36. #define _NOT_USED_ 0xFFFFCC25
  37. const uint sdram_table[] =
  38. {
  39. /*
  40. * Single Read. (Offset 00h in UPMA RAM)
  41. */
  42. 0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08,
  43. 0x3FBFCC27, /* last */
  44. _NOT_USED_, _NOT_USED_, _NOT_USED_,
  45. /*
  46. * Burst Read. (Offset 08h in UPMA RAM)
  47. */
  48. 0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88,
  49. 0x3FBFCC27, /* last */
  50. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  51. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  52. _NOT_USED_, _NOT_USED_, _NOT_USED_,
  53. /*
  54. * Single Write. (Offset 18h in UPMA RAM)
  55. */
  56. 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00,
  57. 0x3FFFCC27, /* last */
  58. _NOT_USED_, _NOT_USED_, _NOT_USED_,
  59. /*
  60. * Burst Write. (Offset 20h in UPMA RAM)
  61. */
  62. 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C,
  63. 0x0CFFCC00, 0x33FFCC27, /* last */
  64. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  65. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  66. _NOT_USED_, _NOT_USED_,
  67. /*
  68. * Refresh. (Offset 30h in UPMA RAM)
  69. */
  70. 0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24,
  71. 0x3FFFCC27, /* last */
  72. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  73. _NOT_USED_, _NOT_USED_, _NOT_USED_,
  74. /*
  75. * Exception. (Offset 3Ch in UPMA RAM)
  76. */
  77. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
  78. };
  79. /* ------------------------------------------------------------------------- */
  80. /*
  81. * Check Board Identity:
  82. */
  83. int checkboard (void)
  84. {
  85. puts ("Board: RPXClassic\n");
  86. return (0);
  87. }
  88. /*-----------------------------------------------------------------------------
  89. * board_get_enetaddr -- Read the MAC Address in the I2C EEPROM
  90. *-----------------------------------------------------------------------------
  91. */
  92. void board_get_enetaddr (uchar * enet)
  93. {
  94. int i;
  95. char buff[256], *cp;
  96. /* Initialize I2C */
  97. i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  98. /* Read 256 bytes in EEPROM */
  99. i2c_read (0x54, 0, 1, (uchar *)buff, 128);
  100. i2c_read (0x54, 128, 1, (uchar *)buff + 128, 128);
  101. /* Retrieve MAC address in buffer (key EA) */
  102. for (cp = buff;;) {
  103. if (cp[0] == 'E' && cp[1] == 'A') {
  104. cp += 3;
  105. /* Read MAC address */
  106. for (i = 0; i < 6; i++, cp += 2) {
  107. enet[i] = aschex_to_byte ((unsigned char *)cp);
  108. }
  109. }
  110. /* Scan to the end of the record */
  111. while ((*cp != '\n') && (*cp != (char)0xff)) {
  112. cp++;
  113. }
  114. /* If the next character is a \n, 0 or ff, we are done. */
  115. cp++;
  116. if ((*cp == '\n') || (*cp == 0) || (*cp == (char)0xff))
  117. break;
  118. }
  119. #ifdef CONFIG_FEC_ENET
  120. /* The MAC address is the same as normal ethernet except the 3rd byte */
  121. /* (See the E.P. Planet Core Overview manual */
  122. enet[3] |= 0x80;
  123. #endif
  124. printf ("MAC address = %02x:%02x:%02x:%02x:%02x:%02x\n",
  125. enet[0], enet[1], enet[2], enet[3], enet[4], enet[5]);
  126. }
  127. void rpxclassic_init (void)
  128. {
  129. /* Enable NVRAM */
  130. *((uchar *) BCSR0) |= BCSR0_ENNVRAM;
  131. #ifdef CONFIG_FEC_ENET
  132. /* Validate the fast ethernet tranceiver */
  133. *((volatile uchar *) BCSR2) &= ~BCSR2_MIICTL;
  134. *((volatile uchar *) BCSR2) &= ~BCSR2_MIIPWRDWN;
  135. *((volatile uchar *) BCSR2) |= BCSR2_MIIRST;
  136. *((volatile uchar *) BCSR2) |= BCSR2_MIIPWRDWN;
  137. #endif
  138. }
  139. /* ------------------------------------------------------------------------- */
  140. phys_size_t initdram (int board_type)
  141. {
  142. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  143. volatile memctl8xx_t *memctl = &immap->im_memctl;
  144. long int size10;
  145. upmconfig (UPMA, (uint *) sdram_table,
  146. sizeof (sdram_table) / sizeof (uint));
  147. /* Refresh clock prescalar */
  148. memctl->memc_mptpr = CONFIG_SYS_MPTPR;
  149. memctl->memc_mar = 0x00000000;
  150. /* Map controller banks 1 to the SDRAM bank */
  151. memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
  152. memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
  153. memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
  154. udelay (200);
  155. /* perform SDRAM initializsation sequence */
  156. memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */
  157. udelay (1);
  158. memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
  159. udelay (1000);
  160. /* Check Bank 0 Memory Size
  161. * try 10 column mode
  162. */
  163. size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM,
  164. SDRAM_MAX_SIZE);
  165. return (size10);
  166. }
  167. /* ------------------------------------------------------------------------- */
  168. /*
  169. * Check memory range for valid RAM. A simple memory test determines
  170. * the actually available RAM size between addresses `base' and
  171. * `base + maxsize'. Some (not all) hardware errors are detected:
  172. * - short between address lines
  173. * - short between data lines
  174. */
  175. static long int dram_size (long int mamr_value, long int *base, long int maxsize)
  176. {
  177. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  178. volatile memctl8xx_t *memctl = &immap->im_memctl;
  179. memctl->memc_mamr = mamr_value;
  180. return (get_ram_size(base, maxsize));
  181. }
  182. /*-----------------------------------------------------------------------------
  183. * aschex_to_byte --
  184. *-----------------------------------------------------------------------------
  185. */
  186. static unsigned char aschex_to_byte (unsigned char *cp)
  187. {
  188. u_char byte, c;
  189. c = *cp++;
  190. if ((c >= 'A') && (c <= 'F')) {
  191. c -= 'A';
  192. c += 10;
  193. } else if ((c >= 'a') && (c <= 'f')) {
  194. c -= 'a';
  195. c += 10;
  196. } else {
  197. c -= '0';
  198. }
  199. byte = c * 16;
  200. c = *cp;
  201. if ((c >= 'A') && (c <= 'F')) {
  202. c -= 'A';
  203. c += 10;
  204. } else if ((c >= 'a') && (c <= 'f')) {
  205. c -= 'a';
  206. c += 10;
  207. } else {
  208. c -= '0';
  209. }
  210. byte += c;
  211. return (byte);
  212. }