db64460.c 27 KB

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  1. /*
  2. * (C) Copyright 2001
  3. * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. *
  23. * modifications for the DB64460 eval board based by Ingo.Assmus@keymile.com
  24. */
  25. /*
  26. * db64460.c - main board support/init for the Galileo Eval board.
  27. */
  28. #include <common.h>
  29. #include <74xx_7xx.h>
  30. #include "../include/memory.h"
  31. #include "../include/pci.h"
  32. #include "../include/mv_gen_reg.h"
  33. #include <net.h>
  34. #include <netdev.h>
  35. #include "eth.h"
  36. #include "mpsc.h"
  37. #include "i2c.h"
  38. #include "64460.h"
  39. #include "mv_regs.h"
  40. #undef DEBUG
  41. /*#define DEBUG */
  42. #define MAP_PCI
  43. #ifdef DEBUG
  44. #define DP(x) x
  45. #else
  46. #define DP(x)
  47. #endif
  48. /* ------------------------------------------------------------------------- */
  49. /* this is the current GT register space location */
  50. /* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
  51. /* Unfortunately, we cant change it while we are in flash, so we initialize it
  52. * to the "final" value. This means that any debug_led calls before
  53. * board_early_init_f wont work right (like in cpu_init_f).
  54. * See also my_remap_gt_regs below. (NTL)
  55. */
  56. void board_prebootm_init (void);
  57. unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
  58. int display_mem_map (void);
  59. /* ------------------------------------------------------------------------- */
  60. /*
  61. * This is a version of the GT register space remapping function that
  62. * doesn't touch globals (meaning, it's ok to run from flash.)
  63. *
  64. * Unfortunately, this has the side effect that a writable
  65. * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
  66. */
  67. void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
  68. {
  69. u32 temp;
  70. /* check and see if it's already moved */
  71. /* original ppcboot 1.1.6 source
  72. temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
  73. if ((temp & 0xffff) == new_loc >> 20)
  74. return;
  75. temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
  76. 0xffff0000) | (new_loc >> 20);
  77. out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
  78. while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
  79. original ppcboot 1.1.6 source end */
  80. temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
  81. if ((temp & 0xffff) == new_loc >> 16)
  82. return;
  83. temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
  84. 0xffff0000) | (new_loc >> 16);
  85. out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
  86. while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
  87. }
  88. #ifdef CONFIG_PCI
  89. static void gt_pci_config (void)
  90. {
  91. unsigned int stat;
  92. unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
  93. /* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
  94. * config registers by writing ones to the bus and device.
  95. * We then update the Virtual register with the correct value for the bus and device.
  96. */
  97. if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
  98. GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
  99. GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
  100. GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
  101. GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
  102. (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
  103. }
  104. if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
  105. GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
  106. GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
  107. GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
  108. GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
  109. (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
  110. }
  111. /* Enable master */
  112. PCI_MASTER_ENABLE (0, SELF);
  113. PCI_MASTER_ENABLE (1, SELF);
  114. /* Enable PCI0/1 Mem0 and IO 0 disable all others */
  115. GT_REG_READ (BASE_ADDR_ENABLE, &stat);
  116. stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
  117. <<
  118. 18);
  119. stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
  120. GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
  121. /* ronen- add write to pci remap registers for 64460.
  122. in 64360 when writing to pci base go and overide remap automaticaly,
  123. in 64460 it doesn't */
  124. GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_BASE >> 16);
  125. GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_BASE >> 16);
  126. GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
  127. GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
  128. GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
  129. GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
  130. GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_BASE >> 16);
  131. GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_BASE >> 16);
  132. GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
  133. GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
  134. GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
  135. GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
  136. /* PCI interface settings */
  137. /* Timeout set to retry forever */
  138. GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
  139. GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
  140. /* ronen - enable only CS0 and Internal reg!! */
  141. GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
  142. GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
  143. /*ronen update the pci internal registers base address.*/
  144. #ifdef MAP_PCI
  145. for (stat = 0; stat <= PCI_HOST1; stat++)
  146. pciWriteConfigReg (stat,
  147. PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
  148. SELF, CONFIG_SYS_GT_REGS);
  149. #endif
  150. }
  151. #endif
  152. /* Setup CPU interface paramaters */
  153. static void gt_cpu_config (void)
  154. {
  155. cpu_t cpu = get_cpu_type ();
  156. ulong tmp;
  157. /* cpu configuration register */
  158. tmp = GTREGREAD (CPU_CONFIGURATION);
  159. /* set the SINGLE_CPU bit see MV64460 P.399 */
  160. #ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
  161. tmp |= CPU_CONF_SINGLE_CPU;
  162. #endif
  163. tmp &= ~CPU_CONF_AACK_DELAY_2;
  164. tmp |= CPU_CONF_DP_VALID;
  165. tmp |= CPU_CONF_AP_VALID;
  166. tmp |= CPU_CONF_PIPELINE;
  167. GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */
  168. /* CPU master control register */
  169. tmp = GTREGREAD (CPU_MASTER_CONTROL);
  170. tmp |= CPU_MAST_CTL_ARB_EN;
  171. if ((cpu == CPU_7400) ||
  172. (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
  173. tmp |= CPU_MAST_CTL_CLEAN_BLK;
  174. tmp |= CPU_MAST_CTL_FLUSH_BLK;
  175. } else {
  176. /* cleanblock must be cleared for CPUs
  177. * that do not support this command (603e, 750)
  178. * see Res#1 */
  179. tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
  180. tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
  181. }
  182. GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
  183. }
  184. /*
  185. * board_early_init_f.
  186. *
  187. * set up gal. device mappings, etc.
  188. */
  189. int board_early_init_f (void)
  190. {
  191. uchar sram_boot = 0;
  192. /*
  193. * set up the GT the way the kernel wants it
  194. * the call to move the GT register space will obviously
  195. * fail if it has already been done, but we're going to assume
  196. * that if it's not at the power-on location, it's where we put
  197. * it last time. (huber)
  198. */
  199. my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
  200. /* No PCI in first release of Port To_do: enable it. */
  201. #ifdef CONFIG_PCI
  202. gt_pci_config ();
  203. #endif
  204. /* mask all external interrupt sources */
  205. GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
  206. GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
  207. /* new in MV6446x */
  208. GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
  209. GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
  210. /* --------------------- */
  211. GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
  212. GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
  213. GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
  214. GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
  215. /* does not exist in MV6446x
  216. GT_REG_WRITE(CPU_INT_0_MASK, 0);
  217. GT_REG_WRITE(CPU_INT_1_MASK, 0);
  218. GT_REG_WRITE(CPU_INT_2_MASK, 0);
  219. GT_REG_WRITE(CPU_INT_3_MASK, 0);
  220. --------------------- */
  221. /* ----- DEVICE BUS SETTINGS ------ */
  222. /*
  223. * EVB
  224. * 0 - SRAM ????
  225. * 1 - RTC ????
  226. * 2 - UART ????
  227. * 3 - Flash checked 32Bit Intel Strata
  228. * boot - BootCS checked 8Bit 29LV040B
  229. *
  230. * Zuma
  231. * 0 - Flash
  232. * boot - BootCS
  233. */
  234. /*
  235. * the dual 7450 module requires burst access to the boot
  236. * device, so the serial rom copies the boot device to the
  237. * on-board sram on the eval board, and updates the correct
  238. * registers to boot from the sram. (device0)
  239. */
  240. if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE)
  241. sram_boot = 1;
  242. if (!sram_boot)
  243. memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
  244. memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
  245. memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
  246. memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
  247. /* configure device timing */
  248. #ifdef CONFIG_SYS_DEV0_PAR /* set port parameters for SRAM device module access */
  249. if (!sram_boot)
  250. GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
  251. #endif
  252. #ifdef CONFIG_SYS_DEV1_PAR /* set port parameters for RTC device module access */
  253. GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
  254. #endif
  255. #ifdef CONFIG_SYS_DEV2_PAR /* set port parameters for DUART device module access */
  256. GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
  257. #endif
  258. #ifdef CONFIG_SYS_32BIT_BOOT_PAR /* set port parameters for Flash device module access */
  259. /* detect if we are booting from the 32 bit flash */
  260. if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
  261. /* 32 bit boot flash */
  262. GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
  263. GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
  264. CONFIG_SYS_32BIT_BOOT_PAR);
  265. } else {
  266. /* 8 bit boot flash */
  267. GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
  268. GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
  269. }
  270. #else
  271. /* 8 bit boot flash only */
  272. /* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
  273. #endif
  274. gt_cpu_config ();
  275. /* MPP setup */
  276. GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
  277. GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
  278. GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
  279. GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
  280. GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
  281. DEBUG_LED0_ON ();
  282. DEBUG_LED1_ON ();
  283. DEBUG_LED2_ON ();
  284. return 0;
  285. }
  286. /* various things to do after relocation */
  287. int misc_init_r ()
  288. {
  289. icache_enable ();
  290. #ifdef CONFIG_SYS_L2
  291. l2cache_enable ();
  292. #endif
  293. #ifdef CONFIG_MPSC
  294. mpsc_sdma_init ();
  295. mpsc_init2 ();
  296. #endif
  297. #if 0
  298. /* disable the dcache and MMU */
  299. dcache_lock ();
  300. #endif
  301. return 0;
  302. }
  303. void after_reloc (ulong dest_addr, gd_t * gd)
  304. {
  305. /* check to see if we booted from the sram. If so, move things
  306. * back to the way they should be. (we're running from main
  307. * memory at this point now */
  308. if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) {
  309. memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
  310. memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_DFL_BOOTCS_BASE, _8M);
  311. }
  312. display_mem_map ();
  313. /* now, jump to the main ppcboot board init code */
  314. board_init_r (gd, dest_addr);
  315. /* NOTREACHED */
  316. }
  317. /* ------------------------------------------------------------------------- */
  318. /*
  319. * Check Board Identity:
  320. *
  321. * right now, assume borad type. (there is just one...after all)
  322. */
  323. int checkboard (void)
  324. {
  325. int l_type = 0;
  326. printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
  327. return (l_type);
  328. }
  329. /* utility functions */
  330. void debug_led (int led, int mode)
  331. {
  332. volatile int *addr = 0;
  333. int dummy;
  334. if (mode == 1) {
  335. switch (led) {
  336. case 0:
  337. addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
  338. 0x08000);
  339. break;
  340. case 1:
  341. addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
  342. 0x0c000);
  343. break;
  344. case 2:
  345. addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
  346. 0x10000);
  347. break;
  348. }
  349. } else if (mode == 0) {
  350. switch (led) {
  351. case 0:
  352. addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
  353. 0x14000);
  354. break;
  355. case 1:
  356. addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
  357. 0x18000);
  358. break;
  359. case 2:
  360. addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
  361. 0x1c000);
  362. break;
  363. }
  364. }
  365. dummy = *addr;
  366. }
  367. int display_mem_map (void)
  368. {
  369. int i, j;
  370. unsigned int base, size, width;
  371. /* SDRAM */
  372. printf ("SD (DDR) RAM\n");
  373. for (i = 0; i <= BANK3; i++) {
  374. base = memoryGetBankBaseAddress (i);
  375. size = memoryGetBankSize (i);
  376. if (size != 0) {
  377. printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
  378. i, base, size >> 20);
  379. }
  380. }
  381. /* CPU's PCI windows */
  382. for (i = 0; i <= PCI_HOST1; i++) {
  383. printf ("\nCPU's PCI %d windows\n", i);
  384. base = pciGetSpaceBase (i, PCI_IO);
  385. size = pciGetSpaceSize (i, PCI_IO);
  386. printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base,
  387. size >> 20);
  388. for (j = 0;
  389. j <=
  390. PCI_REGION0
  391. /*ronen currently only first PCI MEM is used 3 */ ;
  392. j++) {
  393. base = pciGetSpaceBase (i, j);
  394. size = pciGetSpaceSize (i, j);
  395. printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
  396. }
  397. }
  398. /* Devices */
  399. printf ("\nDEVICES\n");
  400. for (i = 0; i <= DEVICE3; i++) {
  401. base = memoryGetDeviceBaseAddress (i);
  402. size = memoryGetDeviceSize (i);
  403. width = memoryGetDeviceWidth (i) * 8;
  404. printf ("DEV %d: base - 0x%08x size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
  405. if (i == 0)
  406. printf ("\t- EXT SRAM (actual - 1M)\n");
  407. else if (i == 1)
  408. printf ("\t- RTC\n");
  409. else if (i == 2)
  410. printf ("\t- UART\n");
  411. else
  412. printf ("\t- LARGE FLASH\n");
  413. }
  414. /* Bootrom */
  415. base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */
  416. size = memoryGetDeviceSize (BOOT_DEVICE);
  417. width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
  418. printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\n",
  419. base, size >> 20, width);
  420. return (0);
  421. }
  422. /* DRAM check routines copied from gw8260 */
  423. #if defined (CONFIG_SYS_DRAM_TEST)
  424. /*********************************************************************/
  425. /* NAME: move64() - moves a double word (64-bit) */
  426. /* */
  427. /* DESCRIPTION: */
  428. /* this function performs a double word move from the data at */
  429. /* the source pointer to the location at the destination pointer. */
  430. /* */
  431. /* INPUTS: */
  432. /* unsigned long long *src - pointer to data to move */
  433. /* */
  434. /* OUTPUTS: */
  435. /* unsigned long long *dest - pointer to locate to move data */
  436. /* */
  437. /* RETURNS: */
  438. /* None */
  439. /* */
  440. /* RESTRICTIONS/LIMITATIONS: */
  441. /* May cloober fr0. */
  442. /* */
  443. /*********************************************************************/
  444. static void move64 (unsigned long long *src, unsigned long long *dest)
  445. {
  446. asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
  447. "stfd 0, 0(4)" /* *dest = fpr0 */
  448. : : : "fr0"); /* Clobbers fr0 */
  449. return;
  450. }
  451. #if defined (CONFIG_SYS_DRAM_TEST_DATA)
  452. unsigned long long pattern[] = {
  453. 0xaaaaaaaaaaaaaaaaULL,
  454. 0xccccccccccccccccULL,
  455. 0xf0f0f0f0f0f0f0f0ULL,
  456. 0xff00ff00ff00ff00ULL,
  457. 0xffff0000ffff0000ULL,
  458. 0xffffffff00000000ULL,
  459. 0x00000000ffffffffULL,
  460. 0x0000ffff0000ffffULL,
  461. 0x00ff00ff00ff00ffULL,
  462. 0x0f0f0f0f0f0f0f0fULL,
  463. 0x3333333333333333ULL,
  464. 0x5555555555555555ULL,
  465. };
  466. /*********************************************************************/
  467. /* NAME: mem_test_data() - test data lines for shorts and opens */
  468. /* */
  469. /* DESCRIPTION: */
  470. /* Tests data lines for shorts and opens by forcing adjacent data */
  471. /* to opposite states. Because the data lines could be routed in */
  472. /* an arbitrary manner the must ensure test patterns ensure that */
  473. /* every case is tested. By using the following series of binary */
  474. /* patterns every combination of adjacent bits is test regardless */
  475. /* of routing. */
  476. /* */
  477. /* ...101010101010101010101010 */
  478. /* ...110011001100110011001100 */
  479. /* ...111100001111000011110000 */
  480. /* ...111111110000000011111111 */
  481. /* */
  482. /* Carrying this out, gives us six hex patterns as follows: */
  483. /* */
  484. /* 0xaaaaaaaaaaaaaaaa */
  485. /* 0xcccccccccccccccc */
  486. /* 0xf0f0f0f0f0f0f0f0 */
  487. /* 0xff00ff00ff00ff00 */
  488. /* 0xffff0000ffff0000 */
  489. /* 0xffffffff00000000 */
  490. /* */
  491. /* The number test patterns will always be given by: */
  492. /* */
  493. /* log(base 2)(number data bits) = log2 (64) = 6 */
  494. /* */
  495. /* To test for short and opens to other signals on our boards. we */
  496. /* simply */
  497. /* test with the 1's complemnt of the paterns as well. */
  498. /* */
  499. /* OUTPUTS: */
  500. /* Displays failing test pattern */
  501. /* */
  502. /* RETURNS: */
  503. /* 0 - Passed test */
  504. /* 1 - Failed test */
  505. /* */
  506. /* RESTRICTIONS/LIMITATIONS: */
  507. /* Assumes only one one SDRAM bank */
  508. /* */
  509. /*********************************************************************/
  510. int mem_test_data (void)
  511. {
  512. unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
  513. unsigned long long temp64 = 0;
  514. int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
  515. int i;
  516. unsigned int hi, lo;
  517. for (i = 0; i < num_patterns; i++) {
  518. move64 (&(pattern[i]), pmem);
  519. move64 (pmem, &temp64);
  520. /* hi = (temp64>>32) & 0xffffffff; */
  521. /* lo = temp64 & 0xffffffff; */
  522. /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
  523. hi = (pattern[i] >> 32) & 0xffffffff;
  524. lo = pattern[i] & 0xffffffff;
  525. /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
  526. if (temp64 != pattern[i]) {
  527. printf ("\n Data Test Failed, pattern 0x%08x%08x",
  528. hi, lo);
  529. return 1;
  530. }
  531. }
  532. return 0;
  533. }
  534. #endif /* CONFIG_SYS_DRAM_TEST_DATA */
  535. #if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
  536. /*********************************************************************/
  537. /* NAME: mem_test_address() - test address lines */
  538. /* */
  539. /* DESCRIPTION: */
  540. /* This function performs a test to verify that each word im */
  541. /* memory is uniquly addressable. The test sequence is as follows: */
  542. /* */
  543. /* 1) write the address of each word to each word. */
  544. /* 2) verify that each location equals its address */
  545. /* */
  546. /* OUTPUTS: */
  547. /* Displays failing test pattern and address */
  548. /* */
  549. /* RETURNS: */
  550. /* 0 - Passed test */
  551. /* 1 - Failed test */
  552. /* */
  553. /* RESTRICTIONS/LIMITATIONS: */
  554. /* */
  555. /* */
  556. /*********************************************************************/
  557. int mem_test_address (void)
  558. {
  559. volatile unsigned int *pmem =
  560. (volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
  561. const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
  562. unsigned int i;
  563. /* write address to each location */
  564. for (i = 0; i < size; i++) {
  565. pmem[i] = i;
  566. }
  567. /* verify each loaction */
  568. for (i = 0; i < size; i++) {
  569. if (pmem[i] != i) {
  570. printf ("\n Address Test Failed at 0x%x", i);
  571. return 1;
  572. }
  573. }
  574. return 0;
  575. }
  576. #endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
  577. #if defined (CONFIG_SYS_DRAM_TEST_WALK)
  578. /*********************************************************************/
  579. /* NAME: mem_march() - memory march */
  580. /* */
  581. /* DESCRIPTION: */
  582. /* Marches up through memory. At each location verifies rmask if */
  583. /* read = 1. At each location write wmask if write = 1. Displays */
  584. /* failing address and pattern. */
  585. /* */
  586. /* INPUTS: */
  587. /* volatile unsigned long long * base - start address of test */
  588. /* unsigned int size - number of dwords(64-bit) to test */
  589. /* unsigned long long rmask - read verify mask */
  590. /* unsigned long long wmask - wrtie verify mask */
  591. /* short read - verifies rmask if read = 1 */
  592. /* short write - writes wmask if write = 1 */
  593. /* */
  594. /* OUTPUTS: */
  595. /* Displays failing test pattern and address */
  596. /* */
  597. /* RETURNS: */
  598. /* 0 - Passed test */
  599. /* 1 - Failed test */
  600. /* */
  601. /* RESTRICTIONS/LIMITATIONS: */
  602. /* */
  603. /* */
  604. /*********************************************************************/
  605. int mem_march (volatile unsigned long long *base,
  606. unsigned int size,
  607. unsigned long long rmask,
  608. unsigned long long wmask, short read, short write)
  609. {
  610. unsigned int i;
  611. unsigned long long temp = 0;
  612. unsigned int hitemp, lotemp, himask, lomask;
  613. for (i = 0; i < size; i++) {
  614. if (read != 0) {
  615. /* temp = base[i]; */
  616. move64 ((unsigned long long *) &(base[i]), &temp);
  617. if (rmask != temp) {
  618. hitemp = (temp >> 32) & 0xffffffff;
  619. lotemp = temp & 0xffffffff;
  620. himask = (rmask >> 32) & 0xffffffff;
  621. lomask = rmask & 0xffffffff;
  622. printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
  623. return 1;
  624. }
  625. }
  626. if (write != 0) {
  627. /* base[i] = wmask; */
  628. move64 (&wmask, (unsigned long long *) &(base[i]));
  629. }
  630. }
  631. return 0;
  632. }
  633. #endif /* CONFIG_SYS_DRAM_TEST_WALK */
  634. /*********************************************************************/
  635. /* NAME: mem_test_walk() - a simple walking ones test */
  636. /* */
  637. /* DESCRIPTION: */
  638. /* Performs a walking ones through entire physical memory. The */
  639. /* test uses as series of memory marches, mem_march(), to verify */
  640. /* and write the test patterns to memory. The test sequence is as */
  641. /* follows: */
  642. /* 1) march writing 0000...0001 */
  643. /* 2) march verifying 0000...0001 , writing 0000...0010 */
  644. /* 3) repeat step 2 shifting masks left 1 bit each time unitl */
  645. /* the write mask equals 1000...0000 */
  646. /* 4) march verifying 1000...0000 */
  647. /* The test fails if any of the memory marches return a failure. */
  648. /* */
  649. /* OUTPUTS: */
  650. /* Displays which pass on the memory test is executing */
  651. /* */
  652. /* RETURNS: */
  653. /* 0 - Passed test */
  654. /* 1 - Failed test */
  655. /* */
  656. /* RESTRICTIONS/LIMITATIONS: */
  657. /* */
  658. /* */
  659. /*********************************************************************/
  660. int mem_test_walk (void)
  661. {
  662. unsigned long long mask;
  663. volatile unsigned long long *pmem =
  664. (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
  665. const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
  666. unsigned int i;
  667. mask = 0x01;
  668. printf ("Initial Pass");
  669. mem_march (pmem, size, 0x0, 0x1, 0, 1);
  670. printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
  671. printf (" ");
  672. printf (" ");
  673. printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
  674. for (i = 0; i < 63; i++) {
  675. printf ("Pass %2d", i + 2);
  676. if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
  677. /*printf("mask: 0x%x, pass: %d, ", mask, i); */
  678. return 1;
  679. }
  680. mask = mask << 1;
  681. printf ("\b\b\b\b\b\b\b");
  682. }
  683. printf ("Last Pass");
  684. if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
  685. /* printf("mask: 0x%x", mask); */
  686. return 1;
  687. }
  688. printf ("\b\b\b\b\b\b\b\b\b");
  689. printf (" ");
  690. printf ("\b\b\b\b\b\b\b\b\b");
  691. return 0;
  692. }
  693. /*********************************************************************/
  694. /* NAME: testdram() - calls any enabled memory tests */
  695. /* */
  696. /* DESCRIPTION: */
  697. /* Runs memory tests if the environment test variables are set to */
  698. /* 'y'. */
  699. /* */
  700. /* INPUTS: */
  701. /* testdramdata - If set to 'y', data test is run. */
  702. /* testdramaddress - If set to 'y', address test is run. */
  703. /* testdramwalk - If set to 'y', walking ones test is run */
  704. /* */
  705. /* OUTPUTS: */
  706. /* None */
  707. /* */
  708. /* RETURNS: */
  709. /* 0 - Passed test */
  710. /* 1 - Failed test */
  711. /* */
  712. /* RESTRICTIONS/LIMITATIONS: */
  713. /* */
  714. /* */
  715. /*********************************************************************/
  716. int testdram (void)
  717. {
  718. char *s;
  719. int rundata, runaddress, runwalk;
  720. s = getenv ("testdramdata");
  721. rundata = (s && (*s == 'y')) ? 1 : 0;
  722. s = getenv ("testdramaddress");
  723. runaddress = (s && (*s == 'y')) ? 1 : 0;
  724. s = getenv ("testdramwalk");
  725. runwalk = (s && (*s == 'y')) ? 1 : 0;
  726. /* rundata = 1; */
  727. /* runaddress = 0; */
  728. /* runwalk = 0; */
  729. if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
  730. printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
  731. }
  732. #ifdef CONFIG_SYS_DRAM_TEST_DATA
  733. if (rundata == 1) {
  734. printf ("Test DATA ... ");
  735. if (mem_test_data () == 1) {
  736. printf ("failed \n");
  737. return 1;
  738. } else
  739. printf ("ok \n");
  740. }
  741. #endif
  742. #ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
  743. if (runaddress == 1) {
  744. printf ("Test ADDRESS ... ");
  745. if (mem_test_address () == 1) {
  746. printf ("failed \n");
  747. return 1;
  748. } else
  749. printf ("ok \n");
  750. }
  751. #endif
  752. #ifdef CONFIG_SYS_DRAM_TEST_WALK
  753. if (runwalk == 1) {
  754. printf ("Test WALKING ONEs ... ");
  755. if (mem_test_walk () == 1) {
  756. printf ("failed \n");
  757. return 1;
  758. } else
  759. printf ("ok \n");
  760. }
  761. #endif
  762. if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
  763. printf ("passed\n");
  764. }
  765. return 0;
  766. }
  767. #endif /* CONFIG_SYS_DRAM_TEST */
  768. /* ronen - the below functions are used by the bootm function */
  769. /* - we map the base register to fbe00000 (same mapping as in the LSP) */
  770. /* - we turn off the RX gig dmas - to prevent the dma from overunning */
  771. /* the kernel data areas. */
  772. /* - we diable and invalidate the icache and dcache. */
  773. void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
  774. {
  775. u32 temp;
  776. temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
  777. if ((temp & 0xffff) == new_loc >> 16)
  778. return;
  779. temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
  780. 0xffff0000) | (new_loc >> 16);
  781. out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
  782. while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
  783. new_loc |
  784. (INTERNAL_SPACE_DECODE)))))
  785. != temp);
  786. }
  787. void board_prebootm_init ()
  788. {
  789. /* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
  790. GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
  791. /* Stop GigE Rx DMA engines */
  792. GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
  793. GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00);
  794. GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00);
  795. /* Relocate MV64460 internal regs */
  796. my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, BRIDGE_REG_BASE_BOOTM);
  797. icache_disable ();
  798. dcache_disable ();
  799. }
  800. int board_eth_init(bd_t *bis)
  801. {
  802. return pci_eth_init(bis);
  803. }