sdram_init.c 62 KB

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  1. /*
  2. * (C) Copyright 2001
  3. * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*************************************************************************
  24. * adaption for the Marvell DB64360 Board
  25. * Ingo Assmus (ingo.assmus@keymile.com)
  26. ************************************************************************/
  27. /* sdram_init.c - automatic memory sizing */
  28. #include <common.h>
  29. #include <74xx_7xx.h>
  30. #include "../include/memory.h"
  31. #include "../include/pci.h"
  32. #include "../include/mv_gen_reg.h"
  33. #include <net.h>
  34. #include "eth.h"
  35. #include "mpsc.h"
  36. #include "../common/i2c.h"
  37. #include "64360.h"
  38. #include "mv_regs.h"
  39. DECLARE_GLOBAL_DATA_PTR;
  40. #undef DEBUG
  41. #define MAP_PCI
  42. #ifdef DEBUG
  43. #define DP(x) x
  44. #else
  45. #define DP(x)
  46. #endif
  47. int set_dfcdlInit (void); /* setup delay line of Mv64360 */
  48. int mvDmaIsChannelActive (int);
  49. int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong);
  50. int mvDmaTransfer (int, ulong, ulong, ulong, ulong);
  51. /* ------------------------------------------------------------------------- */
  52. int
  53. memory_map_bank (unsigned int bankNo,
  54. unsigned int bankBase, unsigned int bankLength)
  55. {
  56. #ifdef MAP_PCI
  57. PCI_HOST host;
  58. #endif
  59. #ifdef DEBUG
  60. if (bankLength > 0) {
  61. printf ("mapping bank %d at %08x - %08x\n",
  62. bankNo, bankBase, bankBase + bankLength - 1);
  63. } else {
  64. printf ("unmapping bank %d\n", bankNo);
  65. }
  66. #endif
  67. memoryMapBank (bankNo, bankBase, bankLength);
  68. #ifdef MAP_PCI
  69. for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
  70. const int features =
  71. PREFETCH_ENABLE |
  72. DELAYED_READ_ENABLE |
  73. AGGRESSIVE_PREFETCH |
  74. READ_LINE_AGGRESSIVE_PREFETCH |
  75. READ_MULTI_AGGRESSIVE_PREFETCH |
  76. MAX_BURST_4 | PCI_NO_SWAP;
  77. pciMapMemoryBank (host, bankNo, bankBase, bankLength);
  78. pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
  79. bankLength);
  80. pciSetRegionFeatures (host, bankNo, features, bankBase,
  81. bankLength);
  82. }
  83. #endif
  84. return 0;
  85. }
  86. #define GB (1 << 30)
  87. /* much of this code is based on (or is) the code in the pip405 port */
  88. /* thanks go to the authors of said port - Josh */
  89. /* structure to store the relevant information about an sdram bank */
  90. typedef struct sdram_info {
  91. uchar drb_size;
  92. uchar registered, ecc;
  93. uchar tpar;
  94. uchar tras_clocks;
  95. uchar burst_len;
  96. uchar banks, slot;
  97. } sdram_info_t;
  98. /* Typedefs for 'gtAuxilGetDIMMinfo' function */
  99. typedef enum _memoryType { SDRAM, DDR } MEMORY_TYPE;
  100. typedef enum _voltageInterface { TTL_5V_TOLERANT, LVTTL, HSTL_1_5V,
  101. SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN,
  102. } VOLTAGE_INTERFACE;
  103. typedef enum _max_CL_supported_DDR { DDR_CL_1 = 1, DDR_CL_1_5 = 2, DDR_CL_2 =
  104. 4, DDR_CL_2_5 = 8, DDR_CL_3 = 16, DDR_CL_3_5 =
  105. 32, DDR_CL_FAULT } MAX_CL_SUPPORTED_DDR;
  106. typedef enum _max_CL_supported_SD { SD_CL_1 =
  107. 1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7,
  108. SD_FAULT } MAX_CL_SUPPORTED_SD;
  109. /* SDRAM/DDR information struct */
  110. typedef struct _gtMemoryDimmInfo {
  111. MEMORY_TYPE memoryType;
  112. unsigned int numOfRowAddresses;
  113. unsigned int numOfColAddresses;
  114. unsigned int numOfModuleBanks;
  115. unsigned int dataWidth;
  116. VOLTAGE_INTERFACE voltageInterface;
  117. unsigned int errorCheckType; /* ECC , PARITY.. */
  118. unsigned int sdramWidth; /* 4,8,16 or 32 */ ;
  119. unsigned int errorCheckDataWidth; /* 0 - no, 1 - Yes */
  120. unsigned int minClkDelay;
  121. unsigned int burstLengthSupported;
  122. unsigned int numOfBanksOnEachDevice;
  123. unsigned int suportedCasLatencies;
  124. unsigned int RefreshInterval;
  125. unsigned int maxCASlatencySupported_LoP; /* LoP left of point (measured in ns) */
  126. unsigned int maxCASlatencySupported_RoP; /* RoP right of point (measured in ns) */
  127. MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
  128. MAX_CL_SUPPORTED_SD maxClSupported_SD;
  129. unsigned int moduleBankDensity;
  130. /* module attributes (true for yes) */
  131. bool bufferedAddrAndControlInputs;
  132. bool registeredAddrAndControlInputs;
  133. bool onCardPLL;
  134. bool bufferedDQMBinputs;
  135. bool registeredDQMBinputs;
  136. bool differentialClockInput;
  137. bool redundantRowAddressing;
  138. /* module general attributes */
  139. bool suportedAutoPreCharge;
  140. bool suportedPreChargeAll;
  141. bool suportedEarlyRasPreCharge;
  142. bool suportedWrite1ReadBurst;
  143. bool suported5PercentLowVCC;
  144. bool suported5PercentUpperVCC;
  145. /* module timing parameters */
  146. unsigned int minRasToCasDelay;
  147. unsigned int minRowActiveRowActiveDelay;
  148. unsigned int minRasPulseWidth;
  149. unsigned int minRowPrechargeTime; /* measured in ns */
  150. int addrAndCommandHoldTime; /* LoP left of point (measured in ns) */
  151. int addrAndCommandSetupTime; /* (measured in ns/100) */
  152. int dataInputSetupTime; /* LoP left of point (measured in ns) */
  153. int dataInputHoldTime; /* LoP left of point (measured in ns) */
  154. /* tAC times for highest 2nd and 3rd highest CAS Latency values */
  155. unsigned int clockToDataOut_LoP; /* LoP left of point (measured in ns) */
  156. unsigned int clockToDataOut_RoP; /* RoP right of point (measured in ns) */
  157. unsigned int clockToDataOutMinus1_LoP; /* LoP left of point (measured in ns) */
  158. unsigned int clockToDataOutMinus1_RoP; /* RoP right of point (measured in ns) */
  159. unsigned int clockToDataOutMinus2_LoP; /* LoP left of point (measured in ns) */
  160. unsigned int clockToDataOutMinus2_RoP; /* RoP right of point (measured in ns) */
  161. unsigned int minimumCycleTimeAtMaxCasLatancy_LoP; /* LoP left of point (measured in ns) */
  162. unsigned int minimumCycleTimeAtMaxCasLatancy_RoP; /* RoP right of point (measured in ns) */
  163. unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */
  164. unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */
  165. unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */
  166. unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */
  167. /* Parameters calculated from
  168. the extracted DIMM information */
  169. unsigned int size;
  170. unsigned int deviceDensity; /* 16,64,128,256 or 512 Mbit */
  171. unsigned int numberOfDevices;
  172. uchar drb_size; /* DRAM size in n*64Mbit */
  173. uchar slot; /* Slot Number this module is inserted in */
  174. uchar spd_raw_data[128]; /* Content of SPD-EEPROM copied 1:1 */
  175. #ifdef DEBUG
  176. uchar manufactura[8]; /* Content of SPD-EEPROM Byte 64-71 */
  177. uchar modul_id[18]; /* Content of SPD-EEPROM Byte 73-90 */
  178. uchar vendor_data[27]; /* Content of SPD-EEPROM Byte 99-125 */
  179. unsigned long modul_serial_no; /* Content of SPD-EEPROM Byte 95-98 */
  180. unsigned int manufac_date; /* Content of SPD-EEPROM Byte 93-94 */
  181. unsigned int modul_revision; /* Content of SPD-EEPROM Byte 91-92 */
  182. uchar manufac_place; /* Content of SPD-EEPROM Byte 72 */
  183. #endif
  184. } AUX_MEM_DIMM_INFO;
  185. /*
  186. * translate ns.ns/10 coding of SPD timing values
  187. * into 10 ps unit values
  188. */
  189. static inline unsigned short NS10to10PS (unsigned char spd_byte)
  190. {
  191. unsigned short ns, ns10;
  192. /* isolate upper nibble */
  193. ns = (spd_byte >> 4) & 0x0F;
  194. /* isolate lower nibble */
  195. ns10 = (spd_byte & 0x0F);
  196. return (ns * 100 + ns10 * 10);
  197. }
  198. /*
  199. * translate ns coding of SPD timing values
  200. * into 10 ps unit values
  201. */
  202. static inline unsigned short NSto10PS (unsigned char spd_byte)
  203. {
  204. return (spd_byte * 100);
  205. }
  206. /* This code reads the SPD chip on the sdram and populates
  207. * the array which is passed in with the relevant information */
  208. /* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
  209. static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
  210. {
  211. unsigned long spd_checksum;
  212. #ifdef ZUMA_NTL
  213. /* zero all the values */
  214. memset (info, 0, sizeof (*info));
  215. /*
  216. if (!slot) {
  217. info->slot = 0;
  218. info->banks = 1;
  219. info->registered = 0;
  220. info->drb_size = 16;*/ /* 16 - 256MBit, 32 - 512MBit */
  221. /* info->tpar = 3;
  222. info->tras_clocks = 5;
  223. info->burst_len = 4;
  224. */
  225. #ifdef CONFIG_MV64360_ECC
  226. /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */
  227. dimmInfo->errorCheckType = 2;
  228. /* info->ecc = 2;*/
  229. #endif
  230. }
  231. return 0;
  232. #else
  233. uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
  234. int ret;
  235. unsigned int i, j, density = 1, devicesForErrCheck = 0;
  236. #ifdef DEBUG
  237. unsigned int k;
  238. #endif
  239. unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp;
  240. int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint;
  241. uchar supp_cal, cal_val;
  242. ulong memclk, tmemclk;
  243. ulong tmp;
  244. uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks;
  245. uchar data[128];
  246. memclk = gd->bus_clk;
  247. tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */
  248. DP (puts ("before i2c read\n"));
  249. ret = i2c_read (addr, 0, 1, data, 128);
  250. DP (puts ("after i2c read\n"));
  251. /* zero all the values */
  252. memset (dimmInfo, 0, sizeof (*dimmInfo));
  253. /* copy the SPD content 1:1 into the dimmInfo structure */
  254. for (i = 0; i <= 127; i++) {
  255. dimmInfo->spd_raw_data[i] = data[i];
  256. }
  257. if (ret) {
  258. DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret));
  259. return 0;
  260. } else
  261. dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */
  262. #ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
  263. for (i = 0; i <= 127; i++) {
  264. printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
  265. data[i]);
  266. }
  267. #endif
  268. #ifdef DEBUG
  269. /* find Manufactura of Dimm Module */
  270. for (i = 0; i < sizeof (dimmInfo->manufactura); i++) {
  271. dimmInfo->manufactura[i] = data[64 + i];
  272. }
  273. printf ("\nThis RAM-Module is produced by: %s\n",
  274. dimmInfo->manufactura);
  275. /* find Manul-ID of Dimm Module */
  276. for (i = 0; i < sizeof (dimmInfo->modul_id); i++) {
  277. dimmInfo->modul_id[i] = data[73 + i];
  278. }
  279. printf ("The Module-ID of this RAM-Module is: %s\n",
  280. dimmInfo->modul_id);
  281. /* find Vendor-Data of Dimm Module */
  282. for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) {
  283. dimmInfo->vendor_data[i] = data[99 + i];
  284. }
  285. printf ("Vendor Data of this RAM-Module is: %s\n",
  286. dimmInfo->vendor_data);
  287. /* find modul_serial_no of Dimm Module */
  288. dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95])));
  289. printf ("Serial No. of this RAM-Module is: %ld (%lx)\n",
  290. dimmInfo->modul_serial_no, dimmInfo->modul_serial_no);
  291. /* find Manufac-Data of Dimm Module */
  292. dimmInfo->manufac_date = (*((unsigned int *) (&data[93])));
  293. printf ("Manufactoring Date of this RAM-Module is: %d.%d\n", data[93], data[94]); /*dimmInfo->manufac_date */
  294. /* find modul_revision of Dimm Module */
  295. dimmInfo->modul_revision = (*((unsigned int *) (&data[91])));
  296. printf ("Module Revision of this RAM-Module is: %d.%d\n", data[91], data[92]); /* dimmInfo->modul_revision */
  297. /* find manufac_place of Dimm Module */
  298. dimmInfo->manufac_place = (*((unsigned char *) (&data[72])));
  299. printf ("manufac_place of this RAM-Module is: %d\n",
  300. dimmInfo->manufac_place);
  301. #endif
  302. /*------------------------------------------------------------------------------------------------------------------------------*/
  303. /* calculate SPD checksum */
  304. /*------------------------------------------------------------------------------------------------------------------------------*/
  305. spd_checksum = 0;
  306. for (i = 0; i <= 62; i++) {
  307. spd_checksum += data[i];
  308. }
  309. if ((spd_checksum & 0xff) != data[63]) {
  310. printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]);
  311. hang ();
  312. }
  313. else
  314. printf ("SPD Checksum ok!\n");
  315. /*------------------------------------------------------------------------------------------------------------------------------*/
  316. for (i = 2; i <= 35; i++) {
  317. switch (i) {
  318. case 2: /* Memory type (DDR / SDRAM) */
  319. dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;
  320. #ifdef DEBUG
  321. if (dimmInfo->memoryType == 0)
  322. DP (printf
  323. ("Dram_type in slot %d is: SDRAM\n",
  324. dimmInfo->slot));
  325. if (dimmInfo->memoryType == 1)
  326. DP (printf
  327. ("Dram_type in slot %d is: DDRAM\n",
  328. dimmInfo->slot));
  329. #endif
  330. break;
  331. /*------------------------------------------------------------------------------------------------------------------------------*/
  332. case 3: /* Number Of Row Addresses */
  333. dimmInfo->numOfRowAddresses = data[i];
  334. DP (printf
  335. ("Module Number of row addresses: %d\n",
  336. dimmInfo->numOfRowAddresses));
  337. break;
  338. /*------------------------------------------------------------------------------------------------------------------------------*/
  339. case 4: /* Number Of Column Addresses */
  340. dimmInfo->numOfColAddresses = data[i];
  341. DP (printf
  342. ("Module Number of col addresses: %d\n",
  343. dimmInfo->numOfColAddresses));
  344. break;
  345. /*------------------------------------------------------------------------------------------------------------------------------*/
  346. case 5: /* Number Of Module Banks */
  347. dimmInfo->numOfModuleBanks = data[i];
  348. DP (printf
  349. ("Number of Banks on Mod. : %d\n",
  350. dimmInfo->numOfModuleBanks));
  351. break;
  352. /*------------------------------------------------------------------------------------------------------------------------------*/
  353. case 6: /* Data Width */
  354. dimmInfo->dataWidth = data[i];
  355. DP (printf
  356. ("Module Data Width: %d\n",
  357. dimmInfo->dataWidth));
  358. break;
  359. /*------------------------------------------------------------------------------------------------------------------------------*/
  360. case 8: /* Voltage Interface */
  361. switch (data[i]) {
  362. case 0x0:
  363. dimmInfo->voltageInterface = TTL_5V_TOLERANT;
  364. DP (printf
  365. ("Module is TTL_5V_TOLERANT\n"));
  366. break;
  367. case 0x1:
  368. dimmInfo->voltageInterface = LVTTL;
  369. DP (printf
  370. ("Module is LVTTL\n"));
  371. break;
  372. case 0x2:
  373. dimmInfo->voltageInterface = HSTL_1_5V;
  374. DP (printf
  375. ("Module is TTL_5V_TOLERANT\n"));
  376. break;
  377. case 0x3:
  378. dimmInfo->voltageInterface = SSTL_3_3V;
  379. DP (printf
  380. ("Module is HSTL_1_5V\n"));
  381. break;
  382. case 0x4:
  383. dimmInfo->voltageInterface = SSTL_2_5V;
  384. DP (printf
  385. ("Module is SSTL_2_5V\n"));
  386. break;
  387. default:
  388. dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
  389. DP (printf
  390. ("Module is VOLTAGE_UNKNOWN\n"));
  391. break;
  392. }
  393. break;
  394. /*------------------------------------------------------------------------------------------------------------------------------*/
  395. case 9: /* Minimum Cycle Time At Max CasLatancy */
  396. shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
  397. mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
  398. maskLeftOfPoint =
  399. (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
  400. maskRightOfPoint =
  401. (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
  402. leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
  403. rightOfPoint = (data[i] & maskRightOfPoint) * mult;
  404. dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP =
  405. leftOfPoint;
  406. dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
  407. rightOfPoint;
  408. DP (printf
  409. ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n",
  410. leftOfPoint, rightOfPoint));
  411. break;
  412. /*------------------------------------------------------------------------------------------------------------------------------*/
  413. case 10: /* Clock To Data Out */
  414. div = (dimmInfo->memoryType == DDR) ? 100 : 10;
  415. time_tmp =
  416. (((data[i] & 0xf0) >> 4) * 10) +
  417. ((data[i] & 0x0f));
  418. leftOfPoint = time_tmp / div;
  419. rightOfPoint = time_tmp % div;
  420. dimmInfo->clockToDataOut_LoP = leftOfPoint;
  421. dimmInfo->clockToDataOut_RoP = rightOfPoint;
  422. DP (printf ("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->clockToDataOut */
  423. break;
  424. /*------------------------------------------------------------------------------------------------------------------------------*/
  425. /*#ifdef CONFIG_ECC */
  426. case 11: /* Error Check Type */
  427. dimmInfo->errorCheckType = data[i];
  428. DP (printf
  429. ("Error Check Type (0=NONE): %d\n",
  430. dimmInfo->errorCheckType));
  431. break;
  432. /* #endif */
  433. /*------------------------------------------------------------------------------------------------------------------------------*/
  434. case 12: /* Refresh Interval */
  435. dimmInfo->RefreshInterval = data[i];
  436. DP (printf
  437. ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
  438. dimmInfo->RefreshInterval));
  439. break;
  440. /*------------------------------------------------------------------------------------------------------------------------------*/
  441. case 13: /* Sdram Width */
  442. dimmInfo->sdramWidth = data[i];
  443. DP (printf
  444. ("Sdram Width: %d\n",
  445. dimmInfo->sdramWidth));
  446. break;
  447. /*------------------------------------------------------------------------------------------------------------------------------*/
  448. case 14: /* Error Check Data Width */
  449. dimmInfo->errorCheckDataWidth = data[i];
  450. DP (printf
  451. ("Error Check Data Width: %d\n",
  452. dimmInfo->errorCheckDataWidth));
  453. break;
  454. /*------------------------------------------------------------------------------------------------------------------------------*/
  455. case 15: /* Minimum Clock Delay */
  456. dimmInfo->minClkDelay = data[i];
  457. DP (printf
  458. ("Minimum Clock Delay: %d\n",
  459. dimmInfo->minClkDelay));
  460. break;
  461. /*------------------------------------------------------------------------------------------------------------------------------*/
  462. case 16: /* Burst Length Supported */
  463. /******-******-******-*******
  464. * bit3 | bit2 | bit1 | bit0 *
  465. *******-******-******-*******
  466. burst length = * 8 | 4 | 2 | 1 *
  467. *****************************
  468. If for example bit0 and bit2 are set, the burst
  469. length supported are 1 and 4. */
  470. dimmInfo->burstLengthSupported = data[i];
  471. #ifdef DEBUG
  472. DP (printf
  473. ("Burst Length Supported: "));
  474. if (dimmInfo->burstLengthSupported & 0x01)
  475. DP (printf ("1, "));
  476. if (dimmInfo->burstLengthSupported & 0x02)
  477. DP (printf ("2, "));
  478. if (dimmInfo->burstLengthSupported & 0x04)
  479. DP (printf ("4, "));
  480. if (dimmInfo->burstLengthSupported & 0x08)
  481. DP (printf ("8, "));
  482. DP (printf (" Bit \n"));
  483. #endif
  484. break;
  485. /*------------------------------------------------------------------------------------------------------------------------------*/
  486. case 17: /* Number Of Banks On Each Device */
  487. dimmInfo->numOfBanksOnEachDevice = data[i];
  488. DP (printf
  489. ("Number Of Banks On Each Chip: %d\n",
  490. dimmInfo->numOfBanksOnEachDevice));
  491. break;
  492. /*------------------------------------------------------------------------------------------------------------------------------*/
  493. case 18: /* Suported Cas Latencies */
  494. /* DDR:
  495. *******-******-******-******-******-******-******-*******
  496. * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
  497. *******-******-******-******-******-******-******-*******
  498. CAS = * TBD | TBD | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 *
  499. *********************************************************
  500. SDRAM:
  501. *******-******-******-******-******-******-******-*******
  502. * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
  503. *******-******-******-******-******-******-******-*******
  504. CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 *
  505. ********************************************************/
  506. dimmInfo->suportedCasLatencies = data[i];
  507. #ifdef DEBUG
  508. DP (printf
  509. ("Suported Cas Latencies: (CL) "));
  510. if (dimmInfo->memoryType == 0) { /* SDRAM */
  511. for (k = 0; k <= 7; k++) {
  512. if (dimmInfo->
  513. suportedCasLatencies & (1 << k))
  514. DP (printf
  515. ("%d, ",
  516. k + 1));
  517. }
  518. } else { /* DDR-RAM */
  519. if (dimmInfo->suportedCasLatencies & 1)
  520. DP (printf ("1, "));
  521. if (dimmInfo->suportedCasLatencies & 2)
  522. DP (printf ("1.5, "));
  523. if (dimmInfo->suportedCasLatencies & 4)
  524. DP (printf ("2, "));
  525. if (dimmInfo->suportedCasLatencies & 8)
  526. DP (printf ("2.5, "));
  527. if (dimmInfo->suportedCasLatencies & 16)
  528. DP (printf ("3, "));
  529. if (dimmInfo->suportedCasLatencies & 32)
  530. DP (printf ("3.5, "));
  531. }
  532. DP (printf ("\n"));
  533. #endif
  534. /* Calculating MAX CAS latency */
  535. for (j = 7; j > 0; j--) {
  536. if (((dimmInfo->
  537. suportedCasLatencies >> j) & 0x1) ==
  538. 1) {
  539. switch (dimmInfo->memoryType) {
  540. case DDR:
  541. /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
  542. switch (j) {
  543. case 7:
  544. DP (printf
  545. ("Max. Cas Latencies (DDR): ERROR !!!\n"));
  546. dimmInfo->
  547. maxClSupported_DDR
  548. =
  549. DDR_CL_FAULT;
  550. hang ();
  551. break;
  552. case 6:
  553. DP (printf
  554. ("Max. Cas Latencies (DDR): ERROR !!!\n"));
  555. dimmInfo->
  556. maxClSupported_DDR
  557. =
  558. DDR_CL_FAULT;
  559. hang ();
  560. break;
  561. case 5:
  562. DP (printf
  563. ("Max. Cas Latencies (DDR): 3.5 clk's\n"));
  564. dimmInfo->
  565. maxClSupported_DDR
  566. = DDR_CL_3_5;
  567. break;
  568. case 4:
  569. DP (printf
  570. ("Max. Cas Latencies (DDR): 3 clk's \n"));
  571. dimmInfo->
  572. maxClSupported_DDR
  573. = DDR_CL_3;
  574. break;
  575. case 3:
  576. DP (printf
  577. ("Max. Cas Latencies (DDR): 2.5 clk's \n"));
  578. dimmInfo->
  579. maxClSupported_DDR
  580. = DDR_CL_2_5;
  581. break;
  582. case 2:
  583. DP (printf
  584. ("Max. Cas Latencies (DDR): 2 clk's \n"));
  585. dimmInfo->
  586. maxClSupported_DDR
  587. = DDR_CL_2;
  588. break;
  589. case 1:
  590. DP (printf
  591. ("Max. Cas Latencies (DDR): 1.5 clk's \n"));
  592. dimmInfo->
  593. maxClSupported_DDR
  594. = DDR_CL_1_5;
  595. break;
  596. }
  597. /* ronen - in case we have a DIMM with minimumCycleTimeAtMaxCasLatancy
  598. lower then our SDRAM cycle count, we won't be able to support this CAL
  599. and we will have to use lower CAL. (minus - means from 3.0 to 2.5) */
  600. if ((dimmInfo->
  601. minimumCycleTimeAtMaxCasLatancy_LoP
  602. <
  603. CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
  604. ||
  605. ((dimmInfo->
  606. minimumCycleTimeAtMaxCasLatancy_LoP
  607. ==
  608. CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
  609. && (dimmInfo->
  610. minimumCycleTimeAtMaxCasLatancy_RoP
  611. <
  612. CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
  613. {
  614. dimmInfo->
  615. maxClSupported_DDR
  616. =
  617. dimmInfo->
  618. maxClSupported_DDR
  619. >> 1;
  620. DP (printf
  621. ("*** Change actual Cas Latencies cause of minimumCycleTime n"));
  622. }
  623. /* ronen - checkif the Dimm frequency compared to the Sysclock. */
  624. if ((dimmInfo->
  625. minimumCycleTimeAtMaxCasLatancy_LoP
  626. >
  627. CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
  628. ||
  629. ((dimmInfo->
  630. minimumCycleTimeAtMaxCasLatancy_LoP
  631. ==
  632. CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
  633. && (dimmInfo->
  634. minimumCycleTimeAtMaxCasLatancy_RoP
  635. >
  636. CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
  637. {
  638. printf ("*********************************************************\n");
  639. printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n");
  640. printf ("*********************************************************\n");
  641. hang ();
  642. }
  643. dimmInfo->
  644. maxCASlatencySupported_LoP
  645. =
  646. 1 +
  647. (int) (5 * j / 10);
  648. if (((5 * j) % 10) != 0)
  649. dimmInfo->
  650. maxCASlatencySupported_RoP
  651. = 5;
  652. else
  653. dimmInfo->
  654. maxCASlatencySupported_RoP
  655. = 0;
  656. DP (printf
  657. ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
  658. dimmInfo->
  659. maxCASlatencySupported_LoP,
  660. dimmInfo->
  661. maxCASlatencySupported_RoP));
  662. break;
  663. case SDRAM:
  664. /* CAS latency 1, 2, 3, 4, 5, 6, 7 */
  665. dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */
  666. DP (printf
  667. ("Max. Cas Latencies (SD): %d\n",
  668. dimmInfo->
  669. maxClSupported_SD));
  670. dimmInfo->
  671. maxCASlatencySupported_LoP
  672. = j;
  673. dimmInfo->
  674. maxCASlatencySupported_RoP
  675. = 0;
  676. DP (printf
  677. ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
  678. dimmInfo->
  679. maxCASlatencySupported_LoP,
  680. dimmInfo->
  681. maxCASlatencySupported_RoP));
  682. break;
  683. }
  684. break;
  685. }
  686. }
  687. break;
  688. /*------------------------------------------------------------------------------------------------------------------------------*/
  689. case 21: /* Buffered Address And Control Inputs */
  690. DP (printf ("\nModul Attributes (SPD Byte 21): \n"));
  691. dimmInfo->bufferedAddrAndControlInputs =
  692. data[i] & BIT0;
  693. dimmInfo->registeredAddrAndControlInputs =
  694. (data[i] & BIT1) >> 1;
  695. dimmInfo->onCardPLL = (data[i] & BIT2) >> 2;
  696. dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3;
  697. dimmInfo->registeredDQMBinputs =
  698. (data[i] & BIT4) >> 4;
  699. dimmInfo->differentialClockInput =
  700. (data[i] & BIT5) >> 5;
  701. dimmInfo->redundantRowAddressing =
  702. (data[i] & BIT6) >> 6;
  703. #ifdef DEBUG
  704. if (dimmInfo->bufferedAddrAndControlInputs == 1)
  705. DP (printf
  706. (" - Buffered Address/Control Input: Yes \n"));
  707. else
  708. DP (printf
  709. (" - Buffered Address/Control Input: No \n"));
  710. if (dimmInfo->registeredAddrAndControlInputs == 1)
  711. DP (printf
  712. (" - Registered Address/Control Input: Yes \n"));
  713. else
  714. DP (printf
  715. (" - Registered Address/Control Input: No \n"));
  716. if (dimmInfo->onCardPLL == 1)
  717. DP (printf
  718. (" - On-Card PLL (clock): Yes \n"));
  719. else
  720. DP (printf
  721. (" - On-Card PLL (clock): No \n"));
  722. if (dimmInfo->bufferedDQMBinputs == 1)
  723. DP (printf
  724. (" - Bufferd DQMB Inputs: Yes \n"));
  725. else
  726. DP (printf
  727. (" - Bufferd DQMB Inputs: No \n"));
  728. if (dimmInfo->registeredDQMBinputs == 1)
  729. DP (printf
  730. (" - Registered DQMB Inputs: Yes \n"));
  731. else
  732. DP (printf
  733. (" - Registered DQMB Inputs: No \n"));
  734. if (dimmInfo->differentialClockInput == 1)
  735. DP (printf
  736. (" - Differential Clock Input: Yes \n"));
  737. else
  738. DP (printf
  739. (" - Differential Clock Input: No \n"));
  740. if (dimmInfo->redundantRowAddressing == 1)
  741. DP (printf
  742. (" - redundant Row Addressing: Yes \n"));
  743. else
  744. DP (printf
  745. (" - redundant Row Addressing: No \n"));
  746. #endif
  747. break;
  748. /*------------------------------------------------------------------------------------------------------------------------------*/
  749. case 22: /* Suported AutoPreCharge */
  750. DP (printf ("\nModul Attributes (SPD Byte 22): \n"));
  751. dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
  752. dimmInfo->suportedAutoPreCharge =
  753. (data[i] & BIT1) >> 1;
  754. dimmInfo->suportedPreChargeAll =
  755. (data[i] & BIT2) >> 2;
  756. dimmInfo->suportedWrite1ReadBurst =
  757. (data[i] & BIT3) >> 3;
  758. dimmInfo->suported5PercentLowVCC =
  759. (data[i] & BIT4) >> 4;
  760. dimmInfo->suported5PercentUpperVCC =
  761. (data[i] & BIT5) >> 5;
  762. #ifdef DEBUG
  763. if (dimmInfo->suportedEarlyRasPreCharge == 1)
  764. DP (printf
  765. (" - Early Ras Precharge: Yes \n"));
  766. else
  767. DP (printf
  768. (" - Early Ras Precharge: No \n"));
  769. if (dimmInfo->suportedAutoPreCharge == 1)
  770. DP (printf
  771. (" - AutoPreCharge: Yes \n"));
  772. else
  773. DP (printf
  774. (" - AutoPreCharge: No \n"));
  775. if (dimmInfo->suportedPreChargeAll == 1)
  776. DP (printf
  777. (" - Precharge All: Yes \n"));
  778. else
  779. DP (printf
  780. (" - Precharge All: No \n"));
  781. if (dimmInfo->suportedWrite1ReadBurst == 1)
  782. DP (printf
  783. (" - Write 1/ReadBurst: Yes \n"));
  784. else
  785. DP (printf
  786. (" - Write 1/ReadBurst: No \n"));
  787. if (dimmInfo->suported5PercentLowVCC == 1)
  788. DP (printf
  789. (" - lower VCC tolerance: 5 Percent \n"));
  790. else
  791. DP (printf
  792. (" - lower VCC tolerance: 10 Percent \n"));
  793. if (dimmInfo->suported5PercentUpperVCC == 1)
  794. DP (printf
  795. (" - upper VCC tolerance: 5 Percent \n"));
  796. else
  797. DP (printf
  798. (" - upper VCC tolerance: 10 Percent \n"));
  799. #endif
  800. break;
  801. /*------------------------------------------------------------------------------------------------------------------------------*/
  802. case 23: /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
  803. shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
  804. mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
  805. maskLeftOfPoint =
  806. (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
  807. maskRightOfPoint =
  808. (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
  809. leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
  810. rightOfPoint = (data[i] & maskRightOfPoint) * mult;
  811. dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP =
  812. leftOfPoint;
  813. dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
  814. rightOfPoint;
  815. DP (printf ("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
  816. break;
  817. /*------------------------------------------------------------------------------------------------------------------------------*/
  818. case 24: /* Clock To Data Out 2nd highest Cas Latency Value */
  819. div = (dimmInfo->memoryType == DDR) ? 100 : 10;
  820. time_tmp =
  821. (((data[i] & 0xf0) >> 4) * 10) +
  822. ((data[i] & 0x0f));
  823. leftOfPoint = time_tmp / div;
  824. rightOfPoint = time_tmp % div;
  825. dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
  826. dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
  827. DP (printf
  828. ("Clock To Data Out (2nd CL value): %d.%2d [ns]\n",
  829. leftOfPoint, rightOfPoint));
  830. break;
  831. /*------------------------------------------------------------------------------------------------------------------------------*/
  832. case 25: /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
  833. shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
  834. mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
  835. maskLeftOfPoint =
  836. (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
  837. maskRightOfPoint =
  838. (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
  839. leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
  840. rightOfPoint = (data[i] & maskRightOfPoint) * mult;
  841. dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP =
  842. leftOfPoint;
  843. dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
  844. rightOfPoint;
  845. DP (printf ("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
  846. break;
  847. /*------------------------------------------------------------------------------------------------------------------------------*/
  848. case 26: /* Clock To Data Out 3rd highest Cas Latency Value */
  849. div = (dimmInfo->memoryType == DDR) ? 100 : 10;
  850. time_tmp =
  851. (((data[i] & 0xf0) >> 4) * 10) +
  852. ((data[i] & 0x0f));
  853. leftOfPoint = time_tmp / div;
  854. rightOfPoint = time_tmp % div;
  855. dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
  856. dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
  857. DP (printf
  858. ("Clock To Data Out (3rd CL value): %d.%2d [ns]\n",
  859. leftOfPoint, rightOfPoint));
  860. break;
  861. /*------------------------------------------------------------------------------------------------------------------------------*/
  862. case 27: /* Minimum Row Precharge Time */
  863. shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
  864. maskLeftOfPoint =
  865. (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
  866. maskRightOfPoint =
  867. (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
  868. leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
  869. rightOfPoint = (data[i] & maskRightOfPoint) * 25;
  870. dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint); /* measured in n times 10ps Intervals */
  871. trp_clocks =
  872. (dimmInfo->minRowPrechargeTime +
  873. (tmemclk - 1)) / tmemclk;
  874. DP (printf
  875. ("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n",
  876. tmemclk, tmemclk / 100, tmemclk % 100));
  877. DP (printf
  878. ("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n",
  879. leftOfPoint, rightOfPoint, trp_clocks));
  880. break;
  881. /*------------------------------------------------------------------------------------------------------------------------------*/
  882. case 28: /* Minimum Row Active to Row Active Time */
  883. shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
  884. maskLeftOfPoint =
  885. (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
  886. maskRightOfPoint =
  887. (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
  888. leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
  889. rightOfPoint = (data[i] & maskRightOfPoint) * 25;
  890. dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */
  891. trrd_clocks =
  892. (dimmInfo->minRowActiveRowActiveDelay +
  893. (tmemclk - 1)) / tmemclk;
  894. DP (printf
  895. ("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n",
  896. leftOfPoint, rightOfPoint, trp_clocks));
  897. break;
  898. /*------------------------------------------------------------------------------------------------------------------------------*/
  899. case 29: /* Minimum Ras-To-Cas Delay */
  900. shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
  901. maskLeftOfPoint =
  902. (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
  903. maskRightOfPoint =
  904. (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
  905. leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
  906. rightOfPoint = (data[i] & maskRightOfPoint) * 25;
  907. dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */
  908. trcd_clocks =
  909. (dimmInfo->minRowActiveRowActiveDelay +
  910. (tmemclk - 1)) / tmemclk;
  911. DP (printf
  912. ("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n",
  913. leftOfPoint, rightOfPoint, trp_clocks));
  914. break;
  915. /*------------------------------------------------------------------------------------------------------------------------------*/
  916. case 30: /* Minimum Ras Pulse Width */
  917. dimmInfo->minRasPulseWidth = data[i];
  918. tras_clocks =
  919. (NSto10PS (data[i]) +
  920. (tmemclk - 1)) / tmemclk;
  921. DP (printf
  922. ("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n",
  923. dimmInfo->minRasPulseWidth, tras_clocks));
  924. break;
  925. /*------------------------------------------------------------------------------------------------------------------------------*/
  926. case 31: /* Module Bank Density */
  927. dimmInfo->moduleBankDensity = data[i];
  928. DP (printf
  929. ("Module Bank Density: %d\n",
  930. dimmInfo->moduleBankDensity));
  931. #ifdef DEBUG
  932. DP (printf
  933. ("*** Offered Densities (more than 1 = Multisize-Module): "));
  934. {
  935. if (dimmInfo->moduleBankDensity & 1)
  936. DP (printf ("4MB, "));
  937. if (dimmInfo->moduleBankDensity & 2)
  938. DP (printf ("8MB, "));
  939. if (dimmInfo->moduleBankDensity & 4)
  940. DP (printf ("16MB, "));
  941. if (dimmInfo->moduleBankDensity & 8)
  942. DP (printf ("32MB, "));
  943. if (dimmInfo->moduleBankDensity & 16)
  944. DP (printf ("64MB, "));
  945. if (dimmInfo->moduleBankDensity & 32)
  946. DP (printf ("128MB, "));
  947. if ((dimmInfo->moduleBankDensity & 64)
  948. || (dimmInfo->moduleBankDensity & 128)) {
  949. DP (printf ("ERROR, "));
  950. hang ();
  951. }
  952. }
  953. DP (printf ("\n"));
  954. #endif
  955. break;
  956. /*------------------------------------------------------------------------------------------------------------------------------*/
  957. case 32: /* Address And Command Setup Time (measured in ns/1000) */
  958. sign = 1;
  959. switch (dimmInfo->memoryType) {
  960. case DDR:
  961. time_tmp =
  962. (((data[i] & 0xf0) >> 4) * 10) +
  963. ((data[i] & 0x0f));
  964. leftOfPoint = time_tmp / 100;
  965. rightOfPoint = time_tmp % 100;
  966. break;
  967. case SDRAM:
  968. leftOfPoint = (data[i] & 0xf0) >> 4;
  969. if (leftOfPoint > 7) {
  970. leftOfPoint = data[i] & 0x70 >> 4;
  971. sign = -1;
  972. }
  973. rightOfPoint = (data[i] & 0x0f);
  974. break;
  975. }
  976. dimmInfo->addrAndCommandSetupTime =
  977. (leftOfPoint * 100 + rightOfPoint) * sign;
  978. DP (printf
  979. ("Address And Command Setup Time [ns]: %d.%d\n",
  980. sign * leftOfPoint, rightOfPoint));
  981. break;
  982. /*------------------------------------------------------------------------------------------------------------------------------*/
  983. case 33: /* Address And Command Hold Time */
  984. sign = 1;
  985. switch (dimmInfo->memoryType) {
  986. case DDR:
  987. time_tmp =
  988. (((data[i] & 0xf0) >> 4) * 10) +
  989. ((data[i] & 0x0f));
  990. leftOfPoint = time_tmp / 100;
  991. rightOfPoint = time_tmp % 100;
  992. break;
  993. case SDRAM:
  994. leftOfPoint = (data[i] & 0xf0) >> 4;
  995. if (leftOfPoint > 7) {
  996. leftOfPoint = data[i] & 0x70 >> 4;
  997. sign = -1;
  998. }
  999. rightOfPoint = (data[i] & 0x0f);
  1000. break;
  1001. }
  1002. dimmInfo->addrAndCommandHoldTime =
  1003. (leftOfPoint * 100 + rightOfPoint) * sign;
  1004. DP (printf
  1005. ("Address And Command Hold Time [ns]: %d.%d\n",
  1006. sign * leftOfPoint, rightOfPoint));
  1007. break;
  1008. /*------------------------------------------------------------------------------------------------------------------------------*/
  1009. case 34: /* Data Input Setup Time */
  1010. sign = 1;
  1011. switch (dimmInfo->memoryType) {
  1012. case DDR:
  1013. time_tmp =
  1014. (((data[i] & 0xf0) >> 4) * 10) +
  1015. ((data[i] & 0x0f));
  1016. leftOfPoint = time_tmp / 100;
  1017. rightOfPoint = time_tmp % 100;
  1018. break;
  1019. case SDRAM:
  1020. leftOfPoint = (data[i] & 0xf0) >> 4;
  1021. if (leftOfPoint > 7) {
  1022. leftOfPoint = data[i] & 0x70 >> 4;
  1023. sign = -1;
  1024. }
  1025. rightOfPoint = (data[i] & 0x0f);
  1026. break;
  1027. }
  1028. dimmInfo->dataInputSetupTime =
  1029. (leftOfPoint * 100 + rightOfPoint) * sign;
  1030. DP (printf
  1031. ("Data Input Setup Time [ns]: %d.%d\n",
  1032. sign * leftOfPoint, rightOfPoint));
  1033. break;
  1034. /*------------------------------------------------------------------------------------------------------------------------------*/
  1035. case 35: /* Data Input Hold Time */
  1036. sign = 1;
  1037. switch (dimmInfo->memoryType) {
  1038. case DDR:
  1039. time_tmp =
  1040. (((data[i] & 0xf0) >> 4) * 10) +
  1041. ((data[i] & 0x0f));
  1042. leftOfPoint = time_tmp / 100;
  1043. rightOfPoint = time_tmp % 100;
  1044. break;
  1045. case SDRAM:
  1046. leftOfPoint = (data[i] & 0xf0) >> 4;
  1047. if (leftOfPoint > 7) {
  1048. leftOfPoint = data[i] & 0x70 >> 4;
  1049. sign = -1;
  1050. }
  1051. rightOfPoint = (data[i] & 0x0f);
  1052. break;
  1053. }
  1054. dimmInfo->dataInputHoldTime =
  1055. (leftOfPoint * 100 + rightOfPoint) * sign;
  1056. DP (printf
  1057. ("Data Input Hold Time [ns]: %d.%d\n\n",
  1058. sign * leftOfPoint, rightOfPoint));
  1059. break;
  1060. /*------------------------------------------------------------------------------------------------------------------------------*/
  1061. }
  1062. }
  1063. /* calculating the sdram density */
  1064. for (i = 0;
  1065. i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses;
  1066. i++) {
  1067. density = density * 2;
  1068. }
  1069. dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice *
  1070. dimmInfo->sdramWidth;
  1071. dimmInfo->numberOfDevices =
  1072. (dimmInfo->dataWidth / dimmInfo->sdramWidth) *
  1073. dimmInfo->numOfModuleBanks;
  1074. devicesForErrCheck =
  1075. (dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth;
  1076. if ((dimmInfo->errorCheckType == 0x1)
  1077. || (dimmInfo->errorCheckType == 0x2)
  1078. || (dimmInfo->errorCheckType == 0x3)) {
  1079. dimmInfo->size =
  1080. (dimmInfo->deviceDensity / 8) *
  1081. (dimmInfo->numberOfDevices -
  1082. /* ronen on the 1G dimm we get wrong value. (was devicesForErrCheck) */
  1083. dimmInfo->numberOfDevices / 8);
  1084. } else {
  1085. dimmInfo->size =
  1086. (dimmInfo->deviceDensity / 8) *
  1087. dimmInfo->numberOfDevices;
  1088. }
  1089. /* compute the module DRB size */
  1090. tmp = (1 <<
  1091. (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
  1092. tmp *= dimmInfo->numOfModuleBanks;
  1093. tmp *= dimmInfo->sdramWidth;
  1094. tmp = tmp >> 24; /* div by 0x4000000 (64M) */
  1095. dimmInfo->drb_size = (uchar) tmp;
  1096. DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size));
  1097. /* try a CAS latency of 3 first... */
  1098. /* bit 1 is CL2, bit 2 is CL3 */
  1099. supp_cal = (dimmInfo->suportedCasLatencies & 0x6) >> 1;
  1100. cal_val = 0;
  1101. if (supp_cal & 3) {
  1102. if (NS10to10PS (data[9]) <= tmemclk)
  1103. cal_val = 3;
  1104. }
  1105. /* then 2... */
  1106. if (supp_cal & 2) {
  1107. if (NS10to10PS (data[23]) <= tmemclk)
  1108. cal_val = 2;
  1109. }
  1110. DP (printf ("cal_val = %d\n", cal_val));
  1111. /* bummer, did't work... */
  1112. if (cal_val == 0) {
  1113. DP (printf ("Couldn't find a good CAS latency\n"));
  1114. hang ();
  1115. return 0;
  1116. }
  1117. return true;
  1118. #endif
  1119. }
  1120. /* sets up the GT properly with information passed in */
  1121. int setup_sdram (AUX_MEM_DIMM_INFO * info)
  1122. {
  1123. ulong tmp, check;
  1124. ulong tmp_sdram_mode = 0; /* 0x141c */
  1125. ulong tmp_dunit_control_low = 0; /* 0x1404 */
  1126. int i;
  1127. /* added 8/21/2003 P. Marchese */
  1128. unsigned int sdram_config_reg;
  1129. /* added 10/10/2003 P. Marchese */
  1130. ulong sdram_chip_size;
  1131. /* sanity checking */
  1132. if (!info->numOfModuleBanks) {
  1133. printf ("setup_sdram called with 0 banks\n");
  1134. return 1;
  1135. }
  1136. /* delay line */
  1137. set_dfcdlInit (); /* may be its not needed */
  1138. DP (printf ("Delay line set done\n"));
  1139. /* set SDRAM mode NOP */ /* To_do check it */
  1140. GT_REG_WRITE (SDRAM_OPERATION, 0x5);
  1141. while (GTREGREAD (SDRAM_OPERATION) != 0) {
  1142. DP (printf
  1143. ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"));
  1144. }
  1145. /* SDRAM configuration */
  1146. /* added 8/21/2003 P. Marchese */
  1147. /* code allows usage of registered DIMMS */
  1148. /* figure out the memory refresh internal */
  1149. switch (info->RefreshInterval) {
  1150. case 0x0:
  1151. case 0x80: /* refresh period is 15.625 usec */
  1152. sdram_config_reg =
  1153. (unsigned int) (((float) 15.625 * (float) CONFIG_SYS_BUS_HZ)
  1154. / (float) 1000000.0);
  1155. break;
  1156. case 0x1:
  1157. case 0x81: /* refresh period is 3.9 usec */
  1158. sdram_config_reg =
  1159. (unsigned int) (((float) 3.9 * (float) CONFIG_SYS_BUS_HZ) /
  1160. (float) 1000000.0);
  1161. break;
  1162. case 0x2:
  1163. case 0x82: /* refresh period is 7.8 usec */
  1164. sdram_config_reg =
  1165. (unsigned int) (((float) 7.8 * (float) CONFIG_SYS_BUS_HZ) /
  1166. (float) 1000000.0);
  1167. break;
  1168. case 0x3:
  1169. case 0x83: /* refresh period is 31.3 usec */
  1170. sdram_config_reg =
  1171. (unsigned int) (((float) 31.3 * (float) CONFIG_SYS_BUS_HZ) /
  1172. (float) 1000000.0);
  1173. break;
  1174. case 0x4:
  1175. case 0x84: /* refresh period is 62.5 usec */
  1176. sdram_config_reg =
  1177. (unsigned int) (((float) 62.5 * (float) CONFIG_SYS_BUS_HZ) /
  1178. (float) 1000000.0);
  1179. break;
  1180. case 0x5:
  1181. case 0x85: /* refresh period is 125 usec */
  1182. sdram_config_reg =
  1183. (unsigned int) (((float) 125 * (float) CONFIG_SYS_BUS_HZ) /
  1184. (float) 1000000.0);
  1185. break;
  1186. default: /* refresh period undefined */
  1187. printf ("DRAM refresh period is unknown!\n");
  1188. printf ("Aborting DRAM setup with an error\n");
  1189. hang ();
  1190. break;
  1191. }
  1192. DP (printf ("calculated refresh interval %0x\n", sdram_config_reg));
  1193. /* make sure the refresh value is only 14 bits */
  1194. if (sdram_config_reg > 0x1fff)
  1195. sdram_config_reg = 0x1fff;
  1196. DP (printf ("adjusted refresh interval %0x\n", sdram_config_reg));
  1197. /* we want physical bank interleaving and */
  1198. /* virtual bank interleaving enabled so do nothing */
  1199. /* since these bits need to be zero to enable the interleaving */
  1200. /* registered DRAM ? */
  1201. if (info->registeredAddrAndControlInputs == 1) {
  1202. /* it's registered DRAM, so set the reg. DRAM bit */
  1203. sdram_config_reg = sdram_config_reg | BIT17;
  1204. DP (printf ("Enabling registered DRAM bit\n"));
  1205. }
  1206. /* turn on DRAM ECC? */
  1207. #ifdef CONFIG_MV64360_ECC
  1208. if (info->errorCheckType == 0x2) {
  1209. /* DRAM has ECC, so turn it on */
  1210. sdram_config_reg = sdram_config_reg | BIT18;
  1211. DP (printf ("Enabling ECC\n"));
  1212. }
  1213. #endif
  1214. /* set the data DQS pin configuration */
  1215. switch (info->sdramWidth) {
  1216. case 0x4: /* memory is x4 */
  1217. sdram_config_reg = sdram_config_reg | BIT20 | BIT21;
  1218. DP (printf ("Data DQS pins set for 16 pins\n"));
  1219. break;
  1220. case 0x8: /* memory is x8 or x16 */
  1221. case 0x10:
  1222. sdram_config_reg = sdram_config_reg | BIT21;
  1223. DP (printf ("Data DQS pins set for 8 pins\n"));
  1224. break;
  1225. case 0x20: /* memory is x32 */
  1226. /* both bits are cleared for x32 so nothing to do */
  1227. DP (printf ("Data DQS pins set for 2 pins\n"));
  1228. break;
  1229. default: /* memory width unsupported */
  1230. printf ("DRAM chip width is unknown!\n");
  1231. printf ("Aborting DRAM setup with an error\n");
  1232. hang ();
  1233. break;
  1234. }
  1235. /* perform read buffer assignments */
  1236. /* we are going to use the Power-up defaults */
  1237. /* bit 26 = CPU = buffer 1 */
  1238. /* bit 27 = PCI bus #0 = buffer 0 */
  1239. /* bit 28 = PCI bus #1 = buffer 0 */
  1240. /* bit 29 = MPSC = buffer 0 */
  1241. /* bit 30 = IDMA = buffer 0 */
  1242. /* bit 31 = Gigabit = buffer 0 */
  1243. sdram_config_reg = sdram_config_reg | BIT26;
  1244. /* sdram_config_reg = sdram_config_reg | 0x58000000; */
  1245. /* sdram_config_reg = sdram_config_reg & 0xffffff00; */
  1246. /* write the value into the SDRAM configuration register */
  1247. GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg);
  1248. DP (printf
  1249. ("OOOOOOOOO sdram_conf 0x1400: %08x\n",
  1250. GTREGREAD (SDRAM_CONFIG)));
  1251. /* SDRAM open pages control keep open as much as I can */
  1252. GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0);
  1253. DP (printf
  1254. ("sdram_open_pages_controll 0x1414: %08x\n",
  1255. GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)));
  1256. /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
  1257. tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */
  1258. if (tmp == 0)
  1259. DP (printf ("Core Signals are sync (by HW-Setting)!!!\n"));
  1260. else
  1261. DP (printf
  1262. ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"));
  1263. /* SDRAM set CAS Latency according to SPD information */
  1264. switch (info->memoryType) {
  1265. case SDRAM:
  1266. printf ("### SD-RAM not supported !!!\n");
  1267. printf ("Aborting!!!\n");
  1268. hang ();
  1269. /* ToDo fill SD-RAM if needed !!!!! */
  1270. break;
  1271. /* Calculate the settings for SDRAM mode and Dunit control low registers */
  1272. /* Values set according to technical bulletin TB-92 rev. c */
  1273. case DDR:
  1274. DP (printf ("### SET-CL for DDR-RAM\n"));
  1275. switch (info->maxClSupported_DDR) {
  1276. case DDR_CL_3:
  1277. tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */
  1278. if (tmp == 1) { /* clocks sync */
  1279. if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */
  1280. tmp_dunit_control_low = 0x05110051;
  1281. else
  1282. tmp_dunit_control_low = 0x24110051;
  1283. DP (printf
  1284. ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
  1285. tmp_sdram_mode, tmp_dunit_control_low));
  1286. } else { /* clk sync. bypassed */
  1287. if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */
  1288. tmp_dunit_control_low = 0x2C1107F2;
  1289. else
  1290. tmp_dunit_control_low = 0x3C1107d2;
  1291. DP (printf
  1292. ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
  1293. tmp_sdram_mode, tmp_dunit_control_low));
  1294. }
  1295. break;
  1296. case DDR_CL_2_5:
  1297. tmp_sdram_mode = 0x62; /* CL=2.5 Burstlength = 4 */
  1298. if (tmp == 1) { /* clocks sync */
  1299. if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */
  1300. tmp_dunit_control_low = 0x25110051;
  1301. else
  1302. tmp_dunit_control_low = 0x24110051;
  1303. DP (printf
  1304. ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
  1305. tmp_sdram_mode, tmp_dunit_control_low));
  1306. } else { /* clk sync. bypassed */
  1307. if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */
  1308. printf ("CL = 2.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");
  1309. printf ("Aborting!!!\n");
  1310. hang ();
  1311. } else
  1312. tmp_dunit_control_low = 0x1B1107d2;
  1313. DP (printf
  1314. ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
  1315. tmp_sdram_mode, tmp_dunit_control_low));
  1316. }
  1317. break;
  1318. case DDR_CL_2:
  1319. tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */
  1320. if (tmp == 1) { /* clocks sync */
  1321. if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */
  1322. tmp_dunit_control_low = 0x04110051;
  1323. else
  1324. tmp_dunit_control_low = 0x03110051;
  1325. DP (printf
  1326. ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
  1327. tmp_sdram_mode, tmp_dunit_control_low));
  1328. } else { /* clk sync. bypassed */
  1329. if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */
  1330. printf ("CL = 2, Clock Unsync'ed, Dunit Control Low register setting undefined\n");
  1331. printf ("Aborting!!!\n");
  1332. hang ();
  1333. } else
  1334. tmp_dunit_control_low = 0x3B1107d2;
  1335. DP (printf
  1336. ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
  1337. tmp_sdram_mode, tmp_dunit_control_low));
  1338. }
  1339. break;
  1340. case DDR_CL_1_5:
  1341. tmp_sdram_mode = 0x52; /* CL=1.5 Burstlength = 4 */
  1342. if (tmp == 1) { /* clocks sync */
  1343. if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */
  1344. tmp_dunit_control_low = 0x24110051;
  1345. else
  1346. tmp_dunit_control_low = 0x23110051;
  1347. DP (printf
  1348. ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
  1349. tmp_sdram_mode, tmp_dunit_control_low));
  1350. } else { /* clk sync. bypassed */
  1351. if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */
  1352. printf ("CL = 1.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");
  1353. printf ("Aborting!!!\n");
  1354. hang ();
  1355. } else
  1356. tmp_dunit_control_low = 0x1A1107d2;
  1357. DP (printf
  1358. ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
  1359. tmp_sdram_mode, tmp_dunit_control_low));
  1360. }
  1361. break;
  1362. default:
  1363. printf ("Max. CL is out of range %d\n",
  1364. info->maxClSupported_DDR);
  1365. hang ();
  1366. break;
  1367. } /* end DDR switch */
  1368. break;
  1369. } /* end CL switch */
  1370. /* Write results of CL detection procedure */
  1371. /* set SDRAM mode reg. 0x141c */
  1372. GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode);
  1373. /* set SDRAM mode SetCommand 0x1418 */
  1374. GT_REG_WRITE (SDRAM_OPERATION, 0x3);
  1375. while (GTREGREAD (SDRAM_OPERATION) != 0) {
  1376. DP (printf
  1377. ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
  1378. }
  1379. /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
  1380. GT_REG_WRITE (D_UNIT_CONTROL_LOW, tmp_dunit_control_low);
  1381. /* set SDRAM mode SetCommand 0x1418 */
  1382. GT_REG_WRITE (SDRAM_OPERATION, 0x3);
  1383. while (GTREGREAD (SDRAM_OPERATION) != 0) {
  1384. DP (printf
  1385. ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"));
  1386. }
  1387. /*------------------------------------------------------------------------------ */
  1388. /* bank parameters */
  1389. /* SDRAM address decode register 0x1410 */
  1390. /* program this with the default value */
  1391. tmp = 0x02; /* power-up default address select decoding value */
  1392. DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size));
  1393. /* figure out the DRAM chip size */
  1394. sdram_chip_size =
  1395. (1 << (info->numOfRowAddresses + info->numOfColAddresses));
  1396. sdram_chip_size *= info->sdramWidth;
  1397. sdram_chip_size *= 4;
  1398. DP (printf ("computed sdram chip size is %#lx\n", sdram_chip_size));
  1399. /* divide sdram chip size by 64 Mbits */
  1400. sdram_chip_size = sdram_chip_size / 0x4000000;
  1401. switch (sdram_chip_size) {
  1402. case 1: /* 64 Mbit */
  1403. case 2: /* 128 Mbit */
  1404. DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n"));
  1405. tmp |= (0x00 << 4);
  1406. break;
  1407. case 4: /* 256 Mbit */
  1408. case 8: /* 512 Mbit */
  1409. DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n"));
  1410. tmp |= (0x01 << 4);
  1411. break;
  1412. case 16: /* 1 Gbit */
  1413. case 32: /* 2 Gbit */
  1414. DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n"));
  1415. tmp |= (0x02 << 4);
  1416. break;
  1417. default:
  1418. printf ("Error in dram size calculation\n");
  1419. printf ("RAM-Device_size is unsupported\n");
  1420. hang ();
  1421. }
  1422. /* SDRAM address control */
  1423. GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp);
  1424. DP (printf
  1425. ("setting up sdram address control (0x1410) with: %08lx \n",
  1426. tmp));
  1427. /* ------------------------------------------------------------------------------ */
  1428. /* same settings for registerd & non-registerd DDR SDRAM */
  1429. DP (printf
  1430. ("setting up sdram_timing_control_low (0x1408) with: %08x \n",
  1431. 0x11511220));
  1432. GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220);
  1433. /* ------------------------------------------------------------------------------ */
  1434. /* SDRAM configuration */
  1435. tmp = GTREGREAD (SDRAM_CONFIG);
  1436. if (info->registeredAddrAndControlInputs
  1437. || info->registeredDQMBinputs) {
  1438. tmp |= (1 << 17);
  1439. DP (printf
  1440. ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
  1441. info->registeredAddrAndControlInputs,
  1442. info->registeredDQMBinputs));
  1443. }
  1444. /* Use buffer 1 to return read data to the CPU
  1445. * Page 426 MV64360 */
  1446. tmp |= (1 << 26);
  1447. DP (printf
  1448. ("Before Buffer assignment - sdram_conf (0x1400): %08x\n",
  1449. GTREGREAD (SDRAM_CONFIG)));
  1450. DP (printf
  1451. ("After Buffer assignment - sdram_conf (0x1400): %08x\n",
  1452. GTREGREAD (SDRAM_CONFIG)));
  1453. /* SDRAM timing To_do: */
  1454. /* ------------------------------------------------------------------------------ */
  1455. DP (printf
  1456. ("setting up sdram_timing_control_high (0x140c) with: %08x \n",
  1457. 0x9));
  1458. GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0x9);
  1459. DP (printf
  1460. ("setting up sdram address pads control (0x14c0) with: %08x \n",
  1461. 0x7d5014a));
  1462. GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a);
  1463. DP (printf
  1464. indent: Standard input:1450: Warning:old style assignment ambiguity in "=*". Assuming "= *"
  1465. indent: Standard input:1451: Warning:old style assignment ambiguity in "=*". Assuming "= *"
  1466. ("setting up sdram data pads control (0x14c4) with: %08x \n",
  1467. 0x7d5014a));
  1468. GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a);
  1469. /* ------------------------------------------------------------------------------ */
  1470. /* set the SDRAM configuration for each bank */
  1471. /* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
  1472. {
  1473. i = info->slot;
  1474. DP (printf
  1475. ("\n*** Running a MRS cycle for bank %d ***\n", i));
  1476. /* map the bank */
  1477. memory_map_bank (i, 0, GB / 4);
  1478. /* set SDRAM mode */ /* To_do check it */
  1479. GT_REG_WRITE (SDRAM_OPERATION, 0x3);
  1480. check = GTREGREAD (SDRAM_OPERATION);
  1481. DP (printf
  1482. ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
  1483. check));
  1484. /* switch back to normal operation mode */
  1485. GT_REG_WRITE (SDRAM_OPERATION, 0);
  1486. check = GTREGREAD (SDRAM_OPERATION);
  1487. DP (printf
  1488. ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
  1489. check));
  1490. /* unmap the bank */
  1491. memory_map_bank (i, 0, 0);
  1492. }
  1493. return 0;
  1494. }
  1495. /*
  1496. * Check memory range for valid RAM. A simple memory test determines
  1497. * the actually available RAM size between addresses `base' and
  1498. * `base + maxsize'. Some (not all) hardware errors are detected:
  1499. * - short between address lines
  1500. * - short between data lines
  1501. */
  1502. long int dram_size (long int *base, long int maxsize)
  1503. {
  1504. volatile long int *addr, *b = base;
  1505. long int cnt, val, save1, save2;
  1506. #define STARTVAL (1<<20) /* start test at 1M */
  1507. for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
  1508. cnt <<= 1) {
  1509. addr = base + cnt; /* pointer arith! */
  1510. save1 = *addr; /* save contents of addr */
  1511. save2 = *b; /* save contents of base */
  1512. *addr = cnt; /* write cnt to addr */
  1513. *b = 0; /* put null at base */
  1514. /* check at base address */
  1515. if ((*b) != 0) {
  1516. *addr = save1; /* restore *addr */
  1517. *b = save2; /* restore *b */
  1518. return (0);
  1519. }
  1520. val = *addr; /* read *addr */
  1521. val = *addr; /* read *addr */
  1522. *addr = save1;
  1523. *b = save2;
  1524. if (val != cnt) {
  1525. DP (printf
  1526. ("Found %08x at Address %08x (failure)\n",
  1527. (unsigned int) val, (unsigned int) addr));
  1528. /* fix boundary condition.. STARTVAL means zero */
  1529. if (cnt == STARTVAL / sizeof (long))
  1530. cnt = 0;
  1531. return (cnt * sizeof (long));
  1532. }
  1533. }
  1534. return maxsize;
  1535. }
  1536. /* ------------------------------------------------------------------------- */
  1537. /* ppcboot interface function to SDRAM init - this is where all the
  1538. * controlling logic happens */
  1539. phys_size_t initdram (int board_type)
  1540. {
  1541. int s0 = 0, s1 = 0;
  1542. int checkbank[4] = {[0 ... 3] = 0 };
  1543. ulong realsize, total, check;
  1544. AUX_MEM_DIMM_INFO dimmInfo1;
  1545. AUX_MEM_DIMM_INFO dimmInfo2;
  1546. int nhr, bank_no;
  1547. ulong dest, memSpaceAttr;
  1548. /* first, use the SPD to get info about the SDRAM/ DDRRAM */
  1549. /* check the NHR bit and skip mem init if it's already done */
  1550. nhr = get_hid0 () & (1 << 16);
  1551. if (nhr) {
  1552. printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n");
  1553. } else {
  1554. /* DIMM0 */
  1555. s0 = check_dimm (0, &dimmInfo1);
  1556. /* DIMM1 */
  1557. s1 = check_dimm (1, &dimmInfo2);
  1558. memory_map_bank (0, 0, 0);
  1559. memory_map_bank (1, 0, 0);
  1560. memory_map_bank (2, 0, 0);
  1561. memory_map_bank (3, 0, 0);
  1562. /* ronen check correct set of DIMMS */
  1563. if (dimmInfo1.numOfModuleBanks && dimmInfo2.numOfModuleBanks) {
  1564. if (dimmInfo1.errorCheckType !=
  1565. dimmInfo2.errorCheckType)
  1566. printf ("***WARNNING***!!!! different ECC support of the DIMMS\n");
  1567. if (dimmInfo1.maxClSupported_DDR !=
  1568. dimmInfo2.maxClSupported_DDR)
  1569. printf ("***WARNNING***!!!! different CAL setting of the DIMMS\n");
  1570. if (dimmInfo1.registeredAddrAndControlInputs !=
  1571. dimmInfo2.registeredAddrAndControlInputs)
  1572. printf ("***WARNNING***!!!! different Registration setting of the DIMMS\n");
  1573. }
  1574. if (dimmInfo1.numOfModuleBanks && setup_sdram (&dimmInfo1)) {
  1575. printf ("Setup for DIMM1 failed.\n");
  1576. }
  1577. if (dimmInfo2.numOfModuleBanks && setup_sdram (&dimmInfo2)) {
  1578. printf ("Setup for DIMM2 failed.\n");
  1579. }
  1580. /* set the NHR bit */
  1581. set_hid0 (get_hid0 () | (1 << 16));
  1582. }
  1583. /* next, size the SDRAM banks */
  1584. realsize = total = 0;
  1585. check = GB / 4;
  1586. if (dimmInfo1.numOfModuleBanks > 0) {
  1587. checkbank[0] = 1;
  1588. }
  1589. if (dimmInfo1.numOfModuleBanks > 1) {
  1590. checkbank[1] = 1;
  1591. }
  1592. if (dimmInfo1.numOfModuleBanks > 2)
  1593. printf ("Error, SPD claims DIMM1 has >2 banks\n");
  1594. printf ("-- DIMM1 has %d banks\n", dimmInfo1.numOfModuleBanks);
  1595. if (dimmInfo2.numOfModuleBanks > 0) {
  1596. checkbank[2] = 1;
  1597. }
  1598. if (dimmInfo2.numOfModuleBanks > 1) {
  1599. checkbank[3] = 1;
  1600. }
  1601. if (dimmInfo2.numOfModuleBanks > 2)
  1602. printf ("Error, SPD claims DIMM2 has >2 banks\n");
  1603. printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks);
  1604. for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
  1605. /* skip over banks that are not populated */
  1606. if (!checkbank[bank_no])
  1607. continue;
  1608. /* ronen - realsize = dram_size((long int *)total, check); */
  1609. if (bank_no == 0 || bank_no == 1) {
  1610. if (checkbank[1] == 1)
  1611. realsize = dimmInfo1.size / 2;
  1612. else
  1613. realsize = dimmInfo1.size;
  1614. }
  1615. if (bank_no == 2 || bank_no == 3) {
  1616. if (checkbank[3] == 1)
  1617. realsize = dimmInfo2.size / 2;
  1618. else
  1619. realsize = dimmInfo2.size;
  1620. }
  1621. memory_map_bank (bank_no, total, realsize);
  1622. /* ronen - initialize the DRAM for ECC */
  1623. #ifdef CONFIG_MV64360_ECC
  1624. if ((dimmInfo1.errorCheckType != 0) &&
  1625. ((dimmInfo2.errorCheckType != 0)
  1626. || (dimmInfo2.numOfModuleBanks == 0))) {
  1627. printf ("ECC Initialization of Bank %d:", bank_no);
  1628. memSpaceAttr = ((~(BIT0 << bank_no)) & 0xf) << 8;
  1629. mvDmaSetMemorySpace (0, 0, memSpaceAttr, total,
  1630. realsize);
  1631. for (dest = total; dest < total + realsize;
  1632. dest += _8M) {
  1633. mvDmaTransfer (0, total, dest, _8M,
  1634. BIT8 /*DMA_DTL_128BYTES */ |
  1635. BIT3 /*DMA_HOLD_SOURCE_ADDR */
  1636. |
  1637. BIT11
  1638. /*DMA_BLOCK_TRANSFER_MODE */ );
  1639. while (mvDmaIsChannelActive (0));
  1640. }
  1641. printf (" PASS\n");
  1642. }
  1643. #endif
  1644. total += realsize;
  1645. }
  1646. /* ronen- add DRAM conf prints */
  1647. switch ((GTREGREAD (0x141c) >> 4) & 0x7) {
  1648. case 0x2:
  1649. printf ("CAS Latency = 2");
  1650. break;
  1651. case 0x3:
  1652. printf ("CAS Latency = 3");
  1653. break;
  1654. case 0x5:
  1655. printf ("CAS Latency = 1.5");
  1656. break;
  1657. case 0x6:
  1658. printf ("CAS Latency = 2.5");
  1659. break;
  1660. }
  1661. printf (" tRP = %d tRAS = %d tRCD=%d\n",
  1662. ((GTREGREAD (0x1408) >> 8) & 0xf) + 1,
  1663. ((GTREGREAD (0x1408) >> 20) & 0xf) + 1,
  1664. ((GTREGREAD (0x1408) >> 4) & 0xf) + 1);
  1665. /* Setup Ethernet DMA Adress window to DRAM Area */
  1666. if (total > _256M)
  1667. printf ("*** ONLY the first 256MB DRAM memory are used out of the ");
  1668. else
  1669. printf ("Total SDRAM memory is ");
  1670. /* (cause all the 4 BATS are taken) */
  1671. return (total);
  1672. }
  1673. /* ronen- add Idma functions for usage of the ecc dram init. */
  1674. /*******************************************************************************
  1675. * mvDmaIsChannelActive - Checks if a engine is busy.
  1676. ********************************************************************************/
  1677. int mvDmaIsChannelActive (int engine)
  1678. {
  1679. ulong data;
  1680. data = GTREGREAD (MV64360_DMA_CHANNEL0_CONTROL + 4 * engine);
  1681. if (data & BIT14 /*activity status */ ) {
  1682. return 1;
  1683. }
  1684. return 0;
  1685. }
  1686. /*******************************************************************************
  1687. * mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding
  1688. * map.
  1689. *******************************************************************************/
  1690. int mvDmaSetMemorySpace (ulong memSpace,
  1691. ulong memSpaceTarget,
  1692. ulong memSpaceAttr, ulong baseAddress, ulong size)
  1693. {
  1694. ulong temp;
  1695. /* The base address must be aligned to the size. */
  1696. if (baseAddress % size != 0) {
  1697. return 0;
  1698. }
  1699. if (size >= 0x10000 /*64K */ ) {
  1700. size &= 0xffff0000;
  1701. baseAddress = (baseAddress & 0xffff0000);
  1702. /* Set the new attributes */
  1703. GT_REG_WRITE (MV64360_DMA_BASE_ADDR_REG0 + memSpace * 8,
  1704. (baseAddress | memSpaceTarget | memSpaceAttr));
  1705. GT_REG_WRITE ((MV64360_DMA_SIZE_REG0 + memSpace * 8),
  1706. (size - 1) & 0xffff0000);
  1707. temp = GTREGREAD (MV64360_DMA_BASE_ADDR_ENABLE_REG);
  1708. GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG,
  1709. (temp & ~(BIT0 << memSpace)));
  1710. return 1;
  1711. }
  1712. return 0;
  1713. }
  1714. /*******************************************************************************
  1715. * mvDmaTransfer - Transfer data from sourceAddr to destAddr on one of the 4
  1716. * DMA channels.
  1717. ********************************************************************************/
  1718. int mvDmaTransfer (int engine, ulong sourceAddr,
  1719. ulong destAddr, ulong numOfBytes, ulong command)
  1720. {
  1721. ulong engOffReg = 0; /* Engine Offset Register */
  1722. if (numOfBytes > 0xffff) {
  1723. command = command | BIT31 /*DMA_16M_DESCRIPTOR_MODE */ ;
  1724. }
  1725. command = command | ((command >> 6) & 0x7);
  1726. engOffReg = engine * 4;
  1727. GT_REG_WRITE (MV64360_DMA_CHANNEL0_BYTE_COUNT + engOffReg,
  1728. numOfBytes);
  1729. GT_REG_WRITE (MV64360_DMA_CHANNEL0_SOURCE_ADDR + engOffReg,
  1730. sourceAddr);
  1731. GT_REG_WRITE (MV64360_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg,
  1732. destAddr);
  1733. command =
  1734. command | BIT12 /*DMA_CHANNEL_ENABLE */ | BIT9
  1735. /*DMA_NON_CHAIN_MODE */ ;
  1736. /* Activate DMA engine By writting to mvDmaControlRegister */
  1737. GT_REG_WRITE (MV64360_DMA_CHANNEL0_CONTROL + engOffReg, command);
  1738. return 1;
  1739. }
  1740. /****************************************************************************************
  1741. * SDRAM INIT *
  1742. * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb *
  1743. * This procedure fits only the Atlantis *
  1744. * *
  1745. ***************************************************************************************/
  1746. /****************************************************************************************
  1747. * DFCDL initialize MV643xx Design Considerations *
  1748. * *
  1749. ***************************************************************************************/
  1750. int set_dfcdlInit (void)
  1751. {
  1752. int i;
  1753. unsigned int dfcdl_word = 0x391; /* 0x14f; ronen new dfcdl */
  1754. for (i = 0; i < 64; i++) {
  1755. GT_REG_WRITE (SRAM_DATA0, dfcdl_word);
  1756. /* dfcdl_word += 0x41; - ronen new dfcdl */
  1757. }
  1758. GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000); /* enable dynamic delay line updating */
  1759. return (0);
  1760. }