mpsc.c 26 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017
  1. /*
  2. * (C) Copyright 2001
  3. * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*************************************************************************
  24. * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
  25. *
  26. ************************************************************************/
  27. /*
  28. * mpsc.c - driver for console over the MPSC.
  29. */
  30. #include <common.h>
  31. #include <config.h>
  32. #include <asm/cache.h>
  33. #include <malloc.h>
  34. #include "mpsc.h"
  35. #include "mv_regs.h"
  36. #include "../include/memory.h"
  37. DECLARE_GLOBAL_DATA_PTR;
  38. /* Define this if you wish to use the MPSC as a register based UART.
  39. * This will force the serial port to not use the SDMA engine at all.
  40. */
  41. #undef CONFIG_MPSC_DEBUG_PORT
  42. int (*mpsc_putchar) (char ch) = mpsc_putchar_early;
  43. char (*mpsc_getchar) (void) = mpsc_getchar_debug;
  44. int (*mpsc_test_char) (void) = mpsc_test_char_debug;
  45. static volatile unsigned int *rx_desc_base = NULL;
  46. static unsigned int rx_desc_index = 0;
  47. static volatile unsigned int *tx_desc_base = NULL;
  48. static unsigned int tx_desc_index = 0;
  49. /* local function declarations */
  50. static int galmpsc_connect (int channel, int connect);
  51. static int galmpsc_route_rx_clock (int channel, int brg);
  52. static int galmpsc_route_tx_clock (int channel, int brg);
  53. static int galmpsc_write_config_regs (int mpsc, int mode);
  54. static int galmpsc_config_channel_regs (int mpsc);
  55. static int galmpsc_set_char_length (int mpsc, int value);
  56. static int galmpsc_set_stop_bit_length (int mpsc, int value);
  57. static int galmpsc_set_parity (int mpsc, int value);
  58. static int galmpsc_enter_hunt (int mpsc);
  59. static int galmpsc_set_brkcnt (int mpsc, int value);
  60. static int galmpsc_set_tcschar (int mpsc, int value);
  61. static int galmpsc_set_snoop (int mpsc, int value);
  62. static int galmpsc_shutdown (int mpsc);
  63. static int galsdma_set_RFT (int channel);
  64. static int galsdma_set_SFM (int channel);
  65. static int galsdma_set_rxle (int channel);
  66. static int galsdma_set_txle (int channel);
  67. static int galsdma_set_burstsize (int channel, unsigned int value);
  68. static int galsdma_set_RC (int channel, unsigned int value);
  69. static int galbrg_set_CDV (int channel, int value);
  70. static int galbrg_enable (int channel);
  71. static int galbrg_disable (int channel);
  72. static int galbrg_set_clksrc (int channel, int value);
  73. static int galbrg_set_CUV (int channel, int value);
  74. static void galsdma_enable_rx (void);
  75. static int galsdma_set_mem_space (unsigned int memSpace,
  76. unsigned int memSpaceTarget,
  77. unsigned int memSpaceAttr,
  78. unsigned int baseAddress,
  79. unsigned int size);
  80. #define SOFTWARE_CACHE_MANAGEMENT
  81. #ifdef SOFTWARE_CACHE_MANAGEMENT
  82. #define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
  83. #define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
  84. #define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
  85. #else
  86. #define FLUSH_DCACHE(a,b)
  87. #define FLUSH_AND_INVALIDATE_DCACHE(a,b)
  88. #define INVALIDATE_DCACHE(a,b)
  89. #endif
  90. #ifdef CONFIG_MPSC_DEBUG_PORT
  91. static void mpsc_debug_init (void)
  92. {
  93. volatile unsigned int temp;
  94. /* Clear the CFR (CHR4) */
  95. /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
  96. temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP));
  97. temp &= 0xffffff00;
  98. temp |= BIT29;
  99. GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP),
  100. temp);
  101. /* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */
  102. temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP));
  103. temp |= (BIT12 | BIT15);
  104. GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP),
  105. temp);
  106. /* Set int mask */
  107. temp = GTREGREAD (GALMPSC_0_INT_MASK);
  108. temp |= BIT6;
  109. GT_REG_WRITE (GALMPSC_0_INT_MASK, temp);
  110. }
  111. #endif
  112. char mpsc_getchar_debug (void)
  113. {
  114. volatile int temp;
  115. volatile unsigned int cause;
  116. cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
  117. while ((cause & BIT6) == 0) {
  118. cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
  119. }
  120. temp = GTREGREAD (GALMPSC_CHANNELREG_10 +
  121. (CHANNEL * GALMPSC_REG_GAP));
  122. /* By writing 1's to the set bits, the register is cleared */
  123. GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP),
  124. temp);
  125. GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6);
  126. return (temp >> 16) & 0xff;
  127. }
  128. /* special function for running out of flash. doesn't modify any
  129. * global variables [josh] */
  130. int mpsc_putchar_early (char ch)
  131. {
  132. int mpsc = CHANNEL;
  133. int temp =
  134. GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
  135. galmpsc_set_tcschar (mpsc, ch);
  136. GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP),
  137. temp | 0x200);
  138. #define MAGIC_FACTOR (10*1000000)
  139. udelay (MAGIC_FACTOR / gd->baudrate);
  140. return 0;
  141. }
  142. /* This is used after relocation, see serial.c and mpsc_init2 */
  143. static int mpsc_putchar_sdma (char ch)
  144. {
  145. volatile unsigned int *p;
  146. unsigned int temp;
  147. /* align the descriptor */
  148. p = tx_desc_base;
  149. memset ((void *) p, 0, 8 * sizeof (unsigned int));
  150. /* fill one 64 bit buffer */
  151. /* word swap, pad with 0 */
  152. p[4] = 0; /* x */
  153. p[5] = (unsigned int) ch; /* x */
  154. /* CHANGED completely according to GT64260A dox - NTL */
  155. p[0] = 0x00010001; /* 0 */
  156. p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* 4 */
  157. p[2] = 0; /* 8 */
  158. p[3] = (unsigned int) &p[4]; /* c */
  159. #if 0
  160. p[9] = DESC_FIRST | DESC_LAST;
  161. p[10] = (unsigned int) &p[0];
  162. p[11] = (unsigned int) &p[12];
  163. #endif
  164. FLUSH_DCACHE (&p[0], &p[8]);
  165. GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
  166. (unsigned int) &p[0]);
  167. GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
  168. (unsigned int) &p[0]);
  169. temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
  170. temp |= (TX_DEMAND | TX_STOP);
  171. GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
  172. INVALIDATE_DCACHE (&p[1], &p[2]);
  173. while (p[1] & DESC_OWNER_BIT) {
  174. udelay (100);
  175. INVALIDATE_DCACHE (&p[1], &p[2]);
  176. }
  177. return 0;
  178. }
  179. char mpsc_getchar_sdma (void)
  180. {
  181. static unsigned int done = 0;
  182. volatile char ch;
  183. unsigned int len = 0, idx = 0, temp;
  184. volatile unsigned int *p;
  185. do {
  186. p = &rx_desc_base[rx_desc_index * 8];
  187. INVALIDATE_DCACHE (&p[0], &p[1]);
  188. /* Wait for character */
  189. while (p[1] & DESC_OWNER_BIT) {
  190. udelay (100);
  191. INVALIDATE_DCACHE (&p[0], &p[1]);
  192. }
  193. /* Handle error case */
  194. if (p[1] & (1 << 15)) {
  195. printf ("oops, error: %08x\n", p[1]);
  196. temp = GTREGREAD (GALMPSC_CHANNELREG_2 +
  197. (CHANNEL * GALMPSC_REG_GAP));
  198. temp |= (1 << 23);
  199. GT_REG_WRITE (GALMPSC_CHANNELREG_2 +
  200. (CHANNEL * GALMPSC_REG_GAP), temp);
  201. /* Can't poll on abort bit, so we just wait. */
  202. udelay (100);
  203. galsdma_enable_rx ();
  204. }
  205. /* Number of bytes left in this descriptor */
  206. len = p[0] & 0xffff;
  207. if (len) {
  208. /* Where to look */
  209. idx = 5;
  210. if (done > 3)
  211. idx = 4;
  212. if (done > 7)
  213. idx = 7;
  214. if (done > 11)
  215. idx = 6;
  216. INVALIDATE_DCACHE (&p[idx], &p[idx + 1]);
  217. ch = p[idx] & 0xff;
  218. done++;
  219. }
  220. if (done < len) {
  221. /* this descriptor has more bytes still
  222. * shift down the char we just read, and leave the
  223. * buffer in place for the next time around
  224. */
  225. p[idx] = p[idx] >> 8;
  226. FLUSH_DCACHE (&p[idx], &p[idx + 1]);
  227. }
  228. if (done == len) {
  229. /* nothing left in this descriptor.
  230. * go to next one
  231. */
  232. p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
  233. p[0] = 0x00100000;
  234. FLUSH_DCACHE (&p[0], &p[1]);
  235. /* Next descriptor */
  236. rx_desc_index = (rx_desc_index + 1) % RX_DESC;
  237. done = 0;
  238. }
  239. } while (len == 0); /* galileo bug.. len might be zero */
  240. return ch;
  241. }
  242. int mpsc_test_char_debug (void)
  243. {
  244. if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0)
  245. return 0;
  246. else {
  247. return 1;
  248. }
  249. }
  250. int mpsc_test_char_sdma (void)
  251. {
  252. volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8];
  253. INVALIDATE_DCACHE (&p[1], &p[2]);
  254. if (p[1] & DESC_OWNER_BIT)
  255. return 0;
  256. else
  257. return 1;
  258. }
  259. int mpsc_init (int baud)
  260. {
  261. /* BRG CONFIG */
  262. galbrg_set_baudrate (CHANNEL, baud);
  263. galbrg_set_clksrc (CHANNEL, 8); /* set source=Tclk */
  264. galbrg_set_CUV (CHANNEL, 0); /* set up CountUpValue */
  265. galbrg_enable (CHANNEL); /* Enable BRG */
  266. /* Set up clock routing */
  267. galmpsc_connect (CHANNEL, GALMPSC_CONNECT); /* connect it */
  268. galmpsc_route_rx_clock (CHANNEL, CHANNEL); /* chosse BRG0 for Rx */
  269. galmpsc_route_tx_clock (CHANNEL, CHANNEL); /* chose BRG0 for Tx */
  270. /* reset MPSC state */
  271. galmpsc_shutdown (CHANNEL);
  272. /* SDMA CONFIG */
  273. galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8); /* in 64 bit words (8 bytes) */
  274. galsdma_set_txle (CHANNEL);
  275. galsdma_set_rxle (CHANNEL);
  276. galsdma_set_RC (CHANNEL, 0xf);
  277. galsdma_set_SFM (CHANNEL);
  278. galsdma_set_RFT (CHANNEL);
  279. /* MPSC CONFIG */
  280. galmpsc_write_config_regs (CHANNEL, GALMPSC_UART);
  281. galmpsc_config_channel_regs (CHANNEL);
  282. galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */
  283. galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE); /* N */
  284. galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */
  285. #ifdef CONFIG_MPSC_DEBUG_PORT
  286. mpsc_debug_init ();
  287. #endif
  288. /* COMM_MPSC CONFIG */
  289. #ifdef SOFTWARE_CACHE_MANAGEMENT
  290. galmpsc_set_snoop (CHANNEL, 0); /* disable snoop */
  291. #else
  292. galmpsc_set_snoop (CHANNEL, 1); /* enable snoop */
  293. #endif
  294. return 0;
  295. }
  296. void mpsc_sdma_init (void)
  297. {
  298. /* Setup SDMA channel0 SDMA_CONFIG_REG*/
  299. GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff);
  300. /* Enable MPSC-Window0 for DRAM Bank0 */
  301. if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT,
  302. MV64360_SDMA_DRAM_CS_0_TARGET,
  303. 0,
  304. memoryGetBankBaseAddress
  305. (CS_0_LOW_DECODE_ADDRESS),
  306. memoryGetBankSize (BANK0)) != true)
  307. printf ("%s: SDMA_Window0 memory setup failed !!! \n",
  308. __FUNCTION__);
  309. /* Disable MPSC-Window1 */
  310. if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_1_BIT,
  311. MV64360_SDMA_DRAM_CS_0_TARGET,
  312. 0,
  313. memoryGetBankBaseAddress
  314. (CS_1_LOW_DECODE_ADDRESS),
  315. memoryGetBankSize (BANK3)) != true)
  316. printf ("%s: SDMA_Window1 memory setup failed !!! \n",
  317. __FUNCTION__);
  318. /* Disable MPSC-Window2 */
  319. if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_2_BIT,
  320. MV64360_SDMA_DRAM_CS_0_TARGET,
  321. 0,
  322. memoryGetBankBaseAddress
  323. (CS_2_LOW_DECODE_ADDRESS),
  324. memoryGetBankSize (BANK3)) != true)
  325. printf ("%s: SDMA_Window2 memory setup failed !!! \n",
  326. __FUNCTION__);
  327. /* Disable MPSC-Window3 */
  328. if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_3_BIT,
  329. MV64360_SDMA_DRAM_CS_0_TARGET,
  330. 0,
  331. memoryGetBankBaseAddress
  332. (CS_3_LOW_DECODE_ADDRESS),
  333. memoryGetBankSize (BANK3)) != true)
  334. printf ("%s: SDMA_Window3 memory setup failed !!! \n",
  335. __FUNCTION__);
  336. /* Setup MPSC0 access mode Window0 full access */
  337. GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG,
  338. (MV64360_SDMA_WIN_ACCESS_FULL <<
  339. (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
  340. /* Setup MPSC1 access mode Window1 full access */
  341. GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG,
  342. (MV64360_SDMA_WIN_ACCESS_FULL <<
  343. (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
  344. /* Setup MPSC internal address space base address */
  345. GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
  346. /* no high address remap*/
  347. GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
  348. GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00);
  349. /* clear interrupt cause register for MPSC (fault register)*/
  350. GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00);
  351. }
  352. void mpsc_init2 (void)
  353. {
  354. int i;
  355. #ifndef CONFIG_MPSC_DEBUG_PORT
  356. mpsc_putchar = mpsc_putchar_sdma;
  357. mpsc_getchar = mpsc_getchar_sdma;
  358. mpsc_test_char = mpsc_test_char_sdma;
  359. #endif
  360. /* RX descriptors */
  361. rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) *
  362. sizeof (unsigned int));
  363. /* align descriptors */
  364. rx_desc_base = (unsigned int *)
  365. (((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0);
  366. rx_desc_index = 0;
  367. memset ((void *) rx_desc_base, 0,
  368. (RX_DESC * 8) * sizeof (unsigned int));
  369. for (i = 0; i < RX_DESC; i++) {
  370. rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4]; /* Buffer */
  371. rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8]; /* Next descriptor */
  372. rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* Command & control */
  373. rx_desc_base[i * 8] = 0x00100000;
  374. }
  375. rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0];
  376. FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]);
  377. GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
  378. (unsigned int) &rx_desc_base[0]);
  379. /* TX descriptors */
  380. tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) *
  381. sizeof (unsigned int));
  382. /* align descriptors */
  383. tx_desc_base = (unsigned int *)
  384. (((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0);
  385. tx_desc_index = -1;
  386. memset ((void *) tx_desc_base, 0,
  387. (TX_DESC * 8) * sizeof (unsigned int));
  388. for (i = 0; i < TX_DESC; i++) {
  389. tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323;
  390. tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323;
  391. tx_desc_base[i * 8 + 3] =
  392. (unsigned int) &tx_desc_base[i * 8 + 4];
  393. tx_desc_base[i * 8 + 2] =
  394. (unsigned int) &tx_desc_base[(i + 1) * 8];
  395. tx_desc_base[i * 8 + 1] =
  396. DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
  397. /* set sbytecnt and shadow byte cnt to 1 */
  398. tx_desc_base[i * 8] = 0x00010001;
  399. }
  400. tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0];
  401. FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]);
  402. udelay (100);
  403. galsdma_enable_rx ();
  404. return;
  405. }
  406. int galbrg_set_baudrate (int channel, int rate)
  407. {
  408. int clock;
  409. galbrg_disable (channel); /*ok */
  410. #ifdef ZUMA_NTL
  411. /* from tclk */
  412. clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
  413. #else
  414. clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
  415. #endif
  416. galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */
  417. galbrg_enable (channel);
  418. gd->baudrate = rate;
  419. return 0;
  420. }
  421. /* ------------------------------------------------------------------ */
  422. /* Below are all the private functions that no one else needs */
  423. static int galbrg_set_CDV (int channel, int value)
  424. {
  425. unsigned int temp;
  426. temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
  427. temp &= 0xFFFF0000;
  428. temp |= (value & 0x0000FFFF);
  429. GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
  430. return 0;
  431. }
  432. static int galbrg_enable (int channel)
  433. {
  434. unsigned int temp;
  435. temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
  436. temp |= 0x00010000;
  437. GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
  438. return 0;
  439. }
  440. static int galbrg_disable (int channel)
  441. {
  442. unsigned int temp;
  443. temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
  444. temp &= 0xFFFEFFFF;
  445. GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
  446. return 0;
  447. }
  448. static int galbrg_set_clksrc (int channel, int value)
  449. {
  450. unsigned int temp;
  451. temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
  452. temp &= 0xFFC3FFFF; /* Bit 18 - 21 (MV 64260 18-22) */
  453. temp |= (value << 18);
  454. GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
  455. return 0;
  456. }
  457. static int galbrg_set_CUV (int channel, int value)
  458. {
  459. /* set CountUpValue */
  460. GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value);
  461. return 0;
  462. }
  463. #if 0
  464. static int galbrg_reset (int channel)
  465. {
  466. unsigned int temp;
  467. temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
  468. temp |= 0x20000;
  469. GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
  470. return 0;
  471. }
  472. #endif
  473. static int galsdma_set_RFT (int channel)
  474. {
  475. unsigned int temp;
  476. temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
  477. temp |= 0x00000001;
  478. GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
  479. temp);
  480. return 0;
  481. }
  482. static int galsdma_set_SFM (int channel)
  483. {
  484. unsigned int temp;
  485. temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
  486. temp |= 0x00000002;
  487. GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
  488. temp);
  489. return 0;
  490. }
  491. static int galsdma_set_rxle (int channel)
  492. {
  493. unsigned int temp;
  494. temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
  495. temp |= 0x00000040;
  496. GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
  497. temp);
  498. return 0;
  499. }
  500. static int galsdma_set_txle (int channel)
  501. {
  502. unsigned int temp;
  503. temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
  504. temp |= 0x00000080;
  505. GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
  506. temp);
  507. return 0;
  508. }
  509. static int galsdma_set_RC (int channel, unsigned int value)
  510. {
  511. unsigned int temp;
  512. temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
  513. temp &= ~0x0000003c;
  514. temp |= (value << 2);
  515. GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
  516. temp);
  517. return 0;
  518. }
  519. static int galsdma_set_burstsize (int channel, unsigned int value)
  520. {
  521. unsigned int temp;
  522. temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
  523. temp &= 0xFFFFCFFF;
  524. switch (value) {
  525. case 8:
  526. GT_REG_WRITE (GALSDMA_0_CONF_REG +
  527. (channel * GALSDMA_REG_DIFF),
  528. (temp | (0x3 << 12)));
  529. break;
  530. case 4:
  531. GT_REG_WRITE (GALSDMA_0_CONF_REG +
  532. (channel * GALSDMA_REG_DIFF),
  533. (temp | (0x2 << 12)));
  534. break;
  535. case 2:
  536. GT_REG_WRITE (GALSDMA_0_CONF_REG +
  537. (channel * GALSDMA_REG_DIFF),
  538. (temp | (0x1 << 12)));
  539. break;
  540. case 1:
  541. GT_REG_WRITE (GALSDMA_0_CONF_REG +
  542. (channel * GALSDMA_REG_DIFF),
  543. (temp | (0x0 << 12)));
  544. break;
  545. default:
  546. return -1;
  547. break;
  548. }
  549. return 0;
  550. }
  551. static int galmpsc_connect (int channel, int connect)
  552. {
  553. unsigned int temp;
  554. temp = GTREGREAD (GALMPSC_ROUTING_REGISTER);
  555. if ((channel == 0) && connect)
  556. temp &= ~0x00000007;
  557. else if ((channel == 1) && connect)
  558. temp &= ~(0x00000007 << 6);
  559. else if ((channel == 0) && !connect)
  560. temp |= 0x00000007;
  561. else
  562. temp |= (0x00000007 << 6);
  563. /* Just in case... */
  564. temp &= 0x3fffffff;
  565. GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp);
  566. return 0;
  567. }
  568. static int galmpsc_route_rx_clock (int channel, int brg)
  569. {
  570. unsigned int temp;
  571. temp = GTREGREAD (GALMPSC_RxC_ROUTE);
  572. if (channel == 0) {
  573. temp &= ~0x0000000F;
  574. temp |= brg;
  575. } else {
  576. temp &= ~0x00000F00;
  577. temp |= (brg << 8);
  578. }
  579. GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp);
  580. return 0;
  581. }
  582. static int galmpsc_route_tx_clock (int channel, int brg)
  583. {
  584. unsigned int temp;
  585. temp = GTREGREAD (GALMPSC_TxC_ROUTE);
  586. if (channel == 0) {
  587. temp &= ~0x0000000F;
  588. temp |= brg;
  589. } else {
  590. temp &= ~0x00000F00;
  591. temp |= (brg << 8);
  592. }
  593. GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp);
  594. return 0;
  595. }
  596. static int galmpsc_write_config_regs (int mpsc, int mode)
  597. {
  598. if (mode == GALMPSC_UART) {
  599. /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
  600. GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP),
  601. 0x000004c4);
  602. /* Main config reg High (32x Rx/Tx clock mode, width=8bits */
  603. GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP),
  604. 0x024003f8);
  605. /* 22 2222 1111 */
  606. /* 54 3210 9876 */
  607. /* 0000 0010 0000 0000 */
  608. /* 1 */
  609. /* 098 7654 3210 */
  610. /* 0000 0011 1111 1000 */
  611. } else
  612. return -1;
  613. return 0;
  614. }
  615. static int galmpsc_config_channel_regs (int mpsc)
  616. {
  617. GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0);
  618. GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0);
  619. GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1);
  620. GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0);
  621. GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0);
  622. GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0);
  623. GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0);
  624. GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0);
  625. GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0);
  626. GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0);
  627. galmpsc_set_brkcnt (mpsc, 0x3);
  628. galmpsc_set_tcschar (mpsc, 0xab);
  629. return 0;
  630. }
  631. static int galmpsc_set_brkcnt (int mpsc, int value)
  632. {
  633. unsigned int temp;
  634. temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
  635. temp &= 0x0000FFFF;
  636. temp |= (value << 16);
  637. GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
  638. return 0;
  639. }
  640. static int galmpsc_set_tcschar (int mpsc, int value)
  641. {
  642. unsigned int temp;
  643. temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
  644. temp &= 0xFFFF0000;
  645. temp |= value;
  646. GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
  647. return 0;
  648. }
  649. static int galmpsc_set_char_length (int mpsc, int value)
  650. {
  651. unsigned int temp;
  652. temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
  653. temp &= 0xFFFFCFFF;
  654. temp |= (value << 12);
  655. GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
  656. return 0;
  657. }
  658. static int galmpsc_set_stop_bit_length (int mpsc, int value)
  659. {
  660. unsigned int temp;
  661. temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
  662. temp &= 0xFFFFBFFF;
  663. temp |= (value << 14);
  664. GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
  665. return 0;
  666. }
  667. static int galmpsc_set_parity (int mpsc, int value)
  668. {
  669. unsigned int temp;
  670. temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
  671. if (value != -1) {
  672. temp &= 0xFFF3FFF3;
  673. temp |= ((value << 18) | (value << 2));
  674. temp |= ((value << 17) | (value << 1));
  675. } else {
  676. temp &= 0xFFF1FFF1;
  677. }
  678. GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
  679. return 0;
  680. }
  681. static int galmpsc_enter_hunt (int mpsc)
  682. {
  683. int temp;
  684. temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
  685. temp |= 0x80000000;
  686. GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
  687. while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) &
  688. MPSC_ENTER_HUNT) {
  689. udelay (1);
  690. }
  691. return 0;
  692. }
  693. static int galmpsc_shutdown (int mpsc)
  694. {
  695. unsigned int temp;
  696. /* cause RX abort (clears RX) */
  697. temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
  698. temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;
  699. temp &= ~MPSC_ENTER_HUNT;
  700. GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
  701. GT_REG_WRITE (GALSDMA_0_COM_REG, 0);
  702. GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT);
  703. /* shut down the MPSC */
  704. GT_REG_WRITE (GALMPSC_MCONF_LOW, 0);
  705. GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0);
  706. GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0);
  707. udelay (100);
  708. /* shut down the sdma engines. */
  709. /* reset config to default */
  710. GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc);
  711. udelay (100);
  712. /* clear the SDMA current and first TX and RX pointers */
  713. GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0);
  714. GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0);
  715. GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0);
  716. udelay (100);
  717. return 0;
  718. }
  719. static void galsdma_enable_rx (void)
  720. {
  721. int temp;
  722. /* Enable RX processing */
  723. temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
  724. temp |= RX_ENABLE;
  725. GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
  726. galmpsc_enter_hunt (CHANNEL);
  727. }
  728. static int galmpsc_set_snoop (int mpsc, int value)
  729. {
  730. int reg =
  731. mpsc ? MPSC_1_ADDRESS_CONTROL_LOW :
  732. MPSC_0_ADDRESS_CONTROL_LOW;
  733. int temp = GTREGREAD (reg);
  734. if (value)
  735. temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30);
  736. else
  737. temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30));
  738. GT_REG_WRITE (reg, temp);
  739. return 0;
  740. }
  741. /*******************************************************************************
  742. * galsdma_set_mem_space - Set MV64360 IDMA memory decoding map.
  743. *
  744. * DESCRIPTION:
  745. * the MV64360 SDMA has its own address decoding map that is de-coupled
  746. * from the CPU interface address decoding windows. The SDMA channels
  747. * share four address windows. Each region can be individually configured
  748. * by this function by associating it to a target interface and setting
  749. * base and size values.
  750. *
  751. * NOTE!!!
  752. * The size must be in 64Kbyte granularity.
  753. * The base address must be aligned to the size.
  754. * The size must be a series of 1s followed by a series of zeros
  755. *
  756. * OUTPUT:
  757. * None.
  758. *
  759. * RETURN:
  760. * True for success, false otherwise.
  761. *
  762. *******************************************************************************/
  763. static int galsdma_set_mem_space (unsigned int memSpace,
  764. unsigned int memSpaceTarget,
  765. unsigned int memSpaceAttr,
  766. unsigned int baseAddress, unsigned int size)
  767. {
  768. unsigned int temp;
  769. if (size == 0) {
  770. GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,
  771. 1 << memSpace);
  772. return true;
  773. }
  774. /* The base address must be aligned to the size. */
  775. if (baseAddress % size != 0) {
  776. return false;
  777. }
  778. if (size < 0x10000) {
  779. return false;
  780. }
  781. /* Align size and base to 64K */
  782. baseAddress &= 0xffff0000;
  783. size &= 0xffff0000;
  784. temp = size >> 16;
  785. /* Checking that the size is a sequence of '1' followed by a
  786. sequence of '0' starting from LSB to MSB. */
  787. while ((temp > 0) && (temp & 0x1)) {
  788. temp = temp >> 1;
  789. }
  790. if (temp != 0) {
  791. GT_REG_WRITE (MV64360_CUNIT_BASE_ADDR_REG0 + memSpace * 8,
  792. (baseAddress | memSpaceTarget | memSpaceAttr));
  793. GT_REG_WRITE ((MV64360_CUNIT_SIZE0 + memSpace * 8),
  794. (size - 1) & 0xffff0000);
  795. GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,
  796. 1 << memSpace);
  797. } else {
  798. /* An invalid size was specified */
  799. return false;
  800. }
  801. return true;
  802. }