turris_omnia.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
  4. * Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz>
  5. *
  6. * Derived from the code for
  7. * Marvell/db-88f6820-gp by Stefan Roese <sr@denx.de>
  8. */
  9. #include <common.h>
  10. #include <env.h>
  11. #include <i2c.h>
  12. #include <init.h>
  13. #include <log.h>
  14. #include <miiphy.h>
  15. #include <net.h>
  16. #include <netdev.h>
  17. #include <asm/global_data.h>
  18. #include <asm/io.h>
  19. #include <asm/arch/cpu.h>
  20. #include <asm/arch/soc.h>
  21. #include <dm/uclass.h>
  22. #include <fdt_support.h>
  23. #include <time.h>
  24. #include <linux/bitops.h>
  25. #include <u-boot/crc.h>
  26. # include <atsha204a-i2c.h>
  27. #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
  28. #include <../serdes/a38x/high_speed_env_spec.h>
  29. DECLARE_GLOBAL_DATA_PTR;
  30. #define OMNIA_I2C_BUS_NAME "i2c@11000->i2cmux@70->i2c@0"
  31. #define OMNIA_I2C_MCU_CHIP_ADDR 0x2a
  32. #define OMNIA_I2C_MCU_CHIP_LEN 1
  33. #define OMNIA_I2C_EEPROM_CHIP_ADDR 0x54
  34. #define OMNIA_I2C_EEPROM_CHIP_LEN 2
  35. #define OMNIA_I2C_EEPROM_MAGIC 0x0341a034
  36. enum mcu_commands {
  37. CMD_GET_STATUS_WORD = 0x01,
  38. CMD_GET_RESET = 0x09,
  39. CMD_WATCHDOG_STATE = 0x0b,
  40. };
  41. enum status_word_bits {
  42. CARD_DET_STSBIT = 0x0010,
  43. MSATA_IND_STSBIT = 0x0020,
  44. };
  45. #define OMNIA_ATSHA204_OTP_VERSION 0
  46. #define OMNIA_ATSHA204_OTP_SERIAL 1
  47. #define OMNIA_ATSHA204_OTP_MAC0 3
  48. #define OMNIA_ATSHA204_OTP_MAC1 4
  49. /*
  50. * Those values and defines are taken from the Marvell U-Boot version
  51. * "u-boot-2013.01-2014_T3.0"
  52. */
  53. #define OMNIA_GPP_OUT_ENA_LOW \
  54. (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
  55. BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \
  56. BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
  57. #define OMNIA_GPP_OUT_ENA_MID \
  58. (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
  59. BIT(16) | BIT(17) | BIT(18)))
  60. #define OMNIA_GPP_OUT_VAL_LOW 0x0
  61. #define OMNIA_GPP_OUT_VAL_MID 0x0
  62. #define OMNIA_GPP_POL_LOW 0x0
  63. #define OMNIA_GPP_POL_MID 0x0
  64. static struct serdes_map board_serdes_map_pex[] = {
  65. {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  66. {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  67. {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  68. {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  69. {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  70. {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
  71. };
  72. static struct serdes_map board_serdes_map_sata[] = {
  73. {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  74. {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  75. {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  76. {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  77. {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  78. {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
  79. };
  80. static struct udevice *omnia_get_i2c_chip(const char *name, uint addr,
  81. uint offset_len)
  82. {
  83. struct udevice *bus, *dev;
  84. int ret;
  85. ret = uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_BUS_NAME, &bus);
  86. if (ret) {
  87. printf("Cannot get I2C bus %s: uclass_get_device_by_name failed: %i\n",
  88. OMNIA_I2C_BUS_NAME, ret);
  89. return NULL;
  90. }
  91. ret = i2c_get_chip(bus, addr, offset_len, &dev);
  92. if (ret) {
  93. printf("Cannot get %s I2C chip: i2c_get_chip failed: %i\n",
  94. name, ret);
  95. return NULL;
  96. }
  97. return dev;
  98. }
  99. static int omnia_mcu_read(u8 cmd, void *buf, int len)
  100. {
  101. struct udevice *chip;
  102. chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
  103. OMNIA_I2C_MCU_CHIP_LEN);
  104. if (!chip)
  105. return -ENODEV;
  106. return dm_i2c_read(chip, cmd, buf, len);
  107. }
  108. #ifndef CONFIG_SPL_BUILD
  109. static int omnia_mcu_write(u8 cmd, const void *buf, int len)
  110. {
  111. struct udevice *chip;
  112. chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
  113. OMNIA_I2C_MCU_CHIP_LEN);
  114. if (!chip)
  115. return -ENODEV;
  116. return dm_i2c_write(chip, cmd, buf, len);
  117. }
  118. static bool disable_mcu_watchdog(void)
  119. {
  120. int ret;
  121. puts("Disabling MCU watchdog... ");
  122. ret = omnia_mcu_write(CMD_WATCHDOG_STATE, "\x00", 1);
  123. if (ret) {
  124. printf("omnia_mcu_write failed: %i\n", ret);
  125. return false;
  126. }
  127. puts("disabled\n");
  128. return true;
  129. }
  130. #endif
  131. static bool omnia_detect_sata(void)
  132. {
  133. int ret;
  134. u16 stsword;
  135. puts("MiniPCIe/mSATA card detection... ");
  136. ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword));
  137. if (ret) {
  138. printf("omnia_mcu_read failed: %i, defaulting to MiniPCIe card\n",
  139. ret);
  140. return false;
  141. }
  142. if (!(stsword & CARD_DET_STSBIT)) {
  143. puts("none\n");
  144. return false;
  145. }
  146. if (stsword & MSATA_IND_STSBIT)
  147. puts("mSATA\n");
  148. else
  149. puts("MiniPCIe\n");
  150. return stsword & MSATA_IND_STSBIT ? true : false;
  151. }
  152. int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
  153. {
  154. if (omnia_detect_sata()) {
  155. *serdes_map_array = board_serdes_map_sata;
  156. *count = ARRAY_SIZE(board_serdes_map_sata);
  157. } else {
  158. *serdes_map_array = board_serdes_map_pex;
  159. *count = ARRAY_SIZE(board_serdes_map_pex);
  160. }
  161. return 0;
  162. }
  163. struct omnia_eeprom {
  164. u32 magic;
  165. u32 ramsize;
  166. char region[4];
  167. u32 crc;
  168. };
  169. static bool omnia_read_eeprom(struct omnia_eeprom *oep)
  170. {
  171. struct udevice *chip;
  172. u32 crc;
  173. int ret;
  174. chip = omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR,
  175. OMNIA_I2C_EEPROM_CHIP_LEN);
  176. if (!chip)
  177. return false;
  178. ret = dm_i2c_read(chip, 0, (void *)oep, sizeof(*oep));
  179. if (ret) {
  180. printf("dm_i2c_read failed: %i, cannot read EEPROM\n", ret);
  181. return false;
  182. }
  183. if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) {
  184. printf("bad EEPROM magic number (%08x, should be %08x)\n",
  185. oep->magic, OMNIA_I2C_EEPROM_MAGIC);
  186. return false;
  187. }
  188. crc = crc32(0, (void *)oep, sizeof(*oep) - 4);
  189. if (crc != oep->crc) {
  190. printf("bad EEPROM CRC (stored %08x, computed %08x)\n",
  191. oep->crc, crc);
  192. return false;
  193. }
  194. return true;
  195. }
  196. static int omnia_get_ram_size_gb(void)
  197. {
  198. static int ram_size;
  199. struct omnia_eeprom oep;
  200. if (!ram_size) {
  201. /* Get the board config from EEPROM */
  202. if (omnia_read_eeprom(&oep)) {
  203. debug("Memory config in EEPROM: 0x%02x\n", oep.ramsize);
  204. if (oep.ramsize == 0x2)
  205. ram_size = 2;
  206. else
  207. ram_size = 1;
  208. } else {
  209. /* Hardcoded fallback */
  210. puts("Memory config from EEPROM read failed!\n");
  211. puts("Falling back to default 1 GiB!\n");
  212. ram_size = 1;
  213. }
  214. }
  215. return ram_size;
  216. }
  217. /*
  218. * Define the DDR layout / topology here in the board file. This will
  219. * be used by the DDR3 init code in the SPL U-Boot version to configure
  220. * the DDR3 controller.
  221. */
  222. static struct mv_ddr_topology_map board_topology_map_1g = {
  223. DEBUG_LEVEL_ERROR,
  224. 0x1, /* active interfaces */
  225. /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
  226. { { { {0x1, 0, 0, 0},
  227. {0x1, 0, 0, 0},
  228. {0x1, 0, 0, 0},
  229. {0x1, 0, 0, 0},
  230. {0x1, 0, 0, 0} },
  231. SPEED_BIN_DDR_1600K, /* speed_bin */
  232. MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
  233. MV_DDR_DIE_CAP_4GBIT, /* mem_size */
  234. MV_DDR_FREQ_800, /* frequency */
  235. 0, 0, /* cas_wl cas_l */
  236. MV_DDR_TEMP_NORMAL, /* temperature */
  237. MV_DDR_TIM_2T} }, /* timing */
  238. BUS_MASK_32BIT, /* Busses mask */
  239. MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
  240. NOT_COMBINED, /* ddr twin-die combined */
  241. { {0} }, /* raw spd data */
  242. {0} /* timing parameters */
  243. };
  244. static struct mv_ddr_topology_map board_topology_map_2g = {
  245. DEBUG_LEVEL_ERROR,
  246. 0x1, /* active interfaces */
  247. /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
  248. { { { {0x1, 0, 0, 0},
  249. {0x1, 0, 0, 0},
  250. {0x1, 0, 0, 0},
  251. {0x1, 0, 0, 0},
  252. {0x1, 0, 0, 0} },
  253. SPEED_BIN_DDR_1600K, /* speed_bin */
  254. MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
  255. MV_DDR_DIE_CAP_8GBIT, /* mem_size */
  256. MV_DDR_FREQ_800, /* frequency */
  257. 0, 0, /* cas_wl cas_l */
  258. MV_DDR_TEMP_NORMAL, /* temperature */
  259. MV_DDR_TIM_2T} }, /* timing */
  260. BUS_MASK_32BIT, /* Busses mask */
  261. MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
  262. NOT_COMBINED, /* ddr twin-die combined */
  263. { {0} }, /* raw spd data */
  264. {0} /* timing parameters */
  265. };
  266. struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
  267. {
  268. if (omnia_get_ram_size_gb() == 2)
  269. return &board_topology_map_2g;
  270. else
  271. return &board_topology_map_1g;
  272. }
  273. #ifndef CONFIG_SPL_BUILD
  274. static int set_regdomain(void)
  275. {
  276. struct omnia_eeprom oep;
  277. char rd[3] = {' ', ' ', 0};
  278. if (omnia_read_eeprom(&oep))
  279. memcpy(rd, &oep.region, 2);
  280. else
  281. puts("EEPROM regdomain read failed.\n");
  282. printf("Regdomain set to %s\n", rd);
  283. return env_set("regdomain", rd);
  284. }
  285. static void handle_reset_button(void)
  286. {
  287. const char * const vars[1] = { "bootcmd_rescue", };
  288. int ret;
  289. u8 reset_status;
  290. /*
  291. * Ensure that bootcmd_rescue has always stock value, so that running
  292. * run bootcmd_rescue
  293. * always works correctly.
  294. */
  295. env_set_default_vars(1, (char * const *)vars, 0);
  296. ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1);
  297. if (ret) {
  298. printf("omnia_mcu_read failed: %i, reset status unknown!\n",
  299. ret);
  300. return;
  301. }
  302. env_set_ulong("omnia_reset", reset_status);
  303. if (reset_status) {
  304. const char * const vars[2] = {
  305. "bootcmd",
  306. "distro_bootcmd",
  307. };
  308. /*
  309. * Set the above envs to their default values, in case the user
  310. * managed to break them.
  311. */
  312. env_set_default_vars(2, (char * const *)vars, 0);
  313. /* Ensure bootcmd_rescue is used by distroboot */
  314. env_set("boot_targets", "rescue");
  315. printf("RESET button was pressed, overwriting bootcmd!\n");
  316. } else {
  317. /*
  318. * In case the user somehow managed to save environment with
  319. * boot_targets=rescue, reset boot_targets to default value.
  320. * This could happen in subsequent commands if bootcmd_rescue
  321. * failed.
  322. */
  323. if (!strcmp(env_get("boot_targets"), "rescue")) {
  324. const char * const vars[1] = {
  325. "boot_targets",
  326. };
  327. env_set_default_vars(1, (char * const *)vars, 0);
  328. }
  329. }
  330. }
  331. #endif
  332. int board_early_init_f(void)
  333. {
  334. /* Configure MPP */
  335. writel(0x11111111, MVEBU_MPP_BASE + 0x00);
  336. writel(0x11111111, MVEBU_MPP_BASE + 0x04);
  337. writel(0x11244011, MVEBU_MPP_BASE + 0x08);
  338. writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
  339. writel(0x22200002, MVEBU_MPP_BASE + 0x10);
  340. writel(0x30042022, MVEBU_MPP_BASE + 0x14);
  341. writel(0x55550555, MVEBU_MPP_BASE + 0x18);
  342. writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
  343. /* Set GPP Out value */
  344. writel(OMNIA_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
  345. writel(OMNIA_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
  346. /* Set GPP Polarity */
  347. writel(OMNIA_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
  348. writel(OMNIA_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
  349. /* Set GPP Out Enable */
  350. writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
  351. writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
  352. return 0;
  353. }
  354. int board_init(void)
  355. {
  356. /* address of boot parameters */
  357. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  358. #ifndef CONFIG_SPL_BUILD
  359. disable_mcu_watchdog();
  360. #endif
  361. return 0;
  362. }
  363. int board_late_init(void)
  364. {
  365. #ifndef CONFIG_SPL_BUILD
  366. set_regdomain();
  367. handle_reset_button();
  368. #endif
  369. pci_init();
  370. return 0;
  371. }
  372. static struct udevice *get_atsha204a_dev(void)
  373. {
  374. static struct udevice *dev;
  375. if (dev)
  376. return dev;
  377. if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) {
  378. puts("Cannot find ATSHA204A on I2C bus!\n");
  379. dev = NULL;
  380. }
  381. return dev;
  382. }
  383. int checkboard(void)
  384. {
  385. u32 version_num, serial_num;
  386. int err = 1;
  387. struct udevice *dev = get_atsha204a_dev();
  388. if (dev) {
  389. err = atsha204a_wakeup(dev);
  390. if (err)
  391. goto out;
  392. err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
  393. OMNIA_ATSHA204_OTP_VERSION,
  394. (u8 *)&version_num);
  395. if (err)
  396. goto out;
  397. err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
  398. OMNIA_ATSHA204_OTP_SERIAL,
  399. (u8 *)&serial_num);
  400. if (err)
  401. goto out;
  402. atsha204a_sleep(dev);
  403. }
  404. out:
  405. printf("Turris Omnia:\n");
  406. printf(" RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024);
  407. if (err)
  408. printf(" Serial Number: unknown\n");
  409. else
  410. printf(" Serial Number: %08X%08X\n", be32_to_cpu(version_num),
  411. be32_to_cpu(serial_num));
  412. return 0;
  413. }
  414. static void increment_mac(u8 *mac)
  415. {
  416. int i;
  417. for (i = 5; i >= 3; i--) {
  418. mac[i] += 1;
  419. if (mac[i])
  420. break;
  421. }
  422. }
  423. int misc_init_r(void)
  424. {
  425. int err;
  426. struct udevice *dev = get_atsha204a_dev();
  427. u8 mac0[4], mac1[4], mac[6];
  428. if (!dev)
  429. goto out;
  430. err = atsha204a_wakeup(dev);
  431. if (err)
  432. goto out;
  433. err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
  434. OMNIA_ATSHA204_OTP_MAC0, mac0);
  435. if (err)
  436. goto out;
  437. err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
  438. OMNIA_ATSHA204_OTP_MAC1, mac1);
  439. if (err)
  440. goto out;
  441. atsha204a_sleep(dev);
  442. mac[0] = mac0[1];
  443. mac[1] = mac0[2];
  444. mac[2] = mac0[3];
  445. mac[3] = mac1[1];
  446. mac[4] = mac1[2];
  447. mac[5] = mac1[3];
  448. if (is_valid_ethaddr(mac))
  449. eth_env_set_enetaddr("eth1addr", mac);
  450. increment_mac(mac);
  451. if (is_valid_ethaddr(mac))
  452. eth_env_set_enetaddr("eth2addr", mac);
  453. increment_mac(mac);
  454. if (is_valid_ethaddr(mac))
  455. eth_env_set_enetaddr("ethaddr", mac);
  456. out:
  457. return 0;
  458. }