ae350_64.dts 7.1 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /dts-v1/;
  3. #include "binman.dtsi"
  4. #include "ae350-u-boot.dtsi"
  5. / {
  6. #address-cells = <2>;
  7. #size-cells = <2>;
  8. compatible = "andestech,ax25";
  9. model = "andestech,ax25";
  10. aliases {
  11. uart0 = &serial0;
  12. spi0 = &spi;
  13. };
  14. chosen {
  15. bootargs = "console=ttyS0,38400n8 debug loglevel=7";
  16. stdout-path = "uart0:38400n8";
  17. };
  18. cpus {
  19. #address-cells = <1>;
  20. #size-cells = <0>;
  21. timebase-frequency = <60000000>;
  22. CPU0: cpu@0 {
  23. device_type = "cpu";
  24. reg = <0>;
  25. status = "okay";
  26. compatible = "riscv";
  27. riscv,isa = "rv64imafdc";
  28. riscv,priv-major = <1>;
  29. riscv,priv-minor = <10>;
  30. mmu-type = "riscv,sv39";
  31. clock-frequency = <60000000>;
  32. i-cache-size = <0x8000>;
  33. i-cache-line-size = <32>;
  34. d-cache-size = <0x8000>;
  35. d-cache-line-size = <32>;
  36. next-level-cache = <&L2>;
  37. CPU0_intc: interrupt-controller {
  38. #interrupt-cells = <1>;
  39. interrupt-controller;
  40. compatible = "riscv,cpu-intc";
  41. };
  42. };
  43. CPU1: cpu@1 {
  44. device_type = "cpu";
  45. reg = <1>;
  46. status = "okay";
  47. compatible = "riscv";
  48. riscv,isa = "rv64imafdc";
  49. riscv,priv-major = <1>;
  50. riscv,priv-minor = <10>;
  51. mmu-type = "riscv,sv39";
  52. clock-frequency = <60000000>;
  53. i-cache-size = <0x8000>;
  54. i-cache-line-size = <32>;
  55. d-cache-size = <0x8000>;
  56. d-cache-line-size = <32>;
  57. next-level-cache = <&L2>;
  58. CPU1_intc: interrupt-controller {
  59. #interrupt-cells = <1>;
  60. interrupt-controller;
  61. compatible = "riscv,cpu-intc";
  62. };
  63. };
  64. CPU2: cpu@2 {
  65. device_type = "cpu";
  66. reg = <2>;
  67. status = "okay";
  68. compatible = "riscv";
  69. riscv,isa = "rv64imafdc";
  70. riscv,priv-major = <1>;
  71. riscv,priv-minor = <10>;
  72. mmu-type = "riscv,sv39";
  73. clock-frequency = <60000000>;
  74. i-cache-size = <0x8000>;
  75. i-cache-line-size = <32>;
  76. d-cache-size = <0x8000>;
  77. d-cache-line-size = <32>;
  78. next-level-cache = <&L2>;
  79. CPU2_intc: interrupt-controller {
  80. #interrupt-cells = <1>;
  81. interrupt-controller;
  82. compatible = "riscv,cpu-intc";
  83. };
  84. };
  85. CPU3: cpu@3 {
  86. device_type = "cpu";
  87. reg = <3>;
  88. status = "okay";
  89. compatible = "riscv";
  90. riscv,isa = "rv64imafdc";
  91. riscv,priv-major = <1>;
  92. riscv,priv-minor = <10>;
  93. mmu-type = "riscv,sv39";
  94. clock-frequency = <60000000>;
  95. i-cache-size = <0x8000>;
  96. i-cache-line-size = <32>;
  97. d-cache-size = <0x8000>;
  98. d-cache-line-size = <32>;
  99. next-level-cache = <&L2>;
  100. CPU3_intc: interrupt-controller {
  101. #interrupt-cells = <1>;
  102. interrupt-controller;
  103. compatible = "riscv,cpu-intc";
  104. };
  105. };
  106. };
  107. L2: l2-cache@e0500000 {
  108. compatible = "v5l2cache";
  109. cache-level = <2>;
  110. cache-size = <0x40000>;
  111. reg = <0x0 0xe0500000 0x0 0x40000>;
  112. andes,inst-prefetch = <3>;
  113. andes,data-prefetch = <3>;
  114. /* The value format is <XRAMOCTL XRAMICTL> */
  115. andes,tag-ram-ctl = <0 0>;
  116. andes,data-ram-ctl = <0 0>;
  117. };
  118. memory@0 {
  119. device_type = "memory";
  120. reg = <0x0 0x00000000 0x0 0x40000000>;
  121. };
  122. soc {
  123. #address-cells = <2>;
  124. #size-cells = <2>;
  125. compatible = "simple-bus";
  126. ranges;
  127. plic0: interrupt-controller@e4000000 {
  128. compatible = "riscv,plic0";
  129. #interrupt-cells = <2>;
  130. interrupt-controller;
  131. reg = <0x0 0xe4000000 0x0 0x2000000>;
  132. riscv,ndev=<71>;
  133. interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9
  134. &CPU1_intc 11 &CPU1_intc 9
  135. &CPU2_intc 11 &CPU2_intc 9
  136. &CPU3_intc 11 &CPU3_intc 9>;
  137. };
  138. plic1: interrupt-controller@e6400000 {
  139. compatible = "riscv,plic1";
  140. #interrupt-cells = <2>;
  141. interrupt-controller;
  142. reg = <0x0 0xe6400000 0x0 0x400000>;
  143. riscv,ndev=<2>;
  144. interrupts-extended = <&CPU0_intc 3
  145. &CPU1_intc 3
  146. &CPU2_intc 3
  147. &CPU3_intc 3>;
  148. };
  149. plmt0@e6000000 {
  150. compatible = "riscv,plmt0";
  151. interrupts-extended = <&CPU0_intc 7
  152. &CPU1_intc 7
  153. &CPU2_intc 7
  154. &CPU3_intc 7>;
  155. reg = <0x0 0xe6000000 0x0 0x100000>;
  156. };
  157. };
  158. spiclk: virt_100mhz {
  159. #clock-cells = <0>;
  160. compatible = "fixed-clock";
  161. clock-frequency = <100000000>;
  162. };
  163. timer0: timer@f0400000 {
  164. compatible = "andestech,atcpit100";
  165. reg = <0x0 0xf0400000 0x0 0x1000>;
  166. clock-frequency = <60000000>;
  167. interrupts = <3 4>;
  168. interrupt-parent = <&plic0>;
  169. };
  170. serial0: serial@f0300000 {
  171. compatible = "andestech,uart16550", "ns16550a";
  172. reg = <0x0 0xf0300000 0x0 0x1000>;
  173. interrupts = <9 4>;
  174. clock-frequency = <19660800>;
  175. reg-shift = <2>;
  176. reg-offset = <32>;
  177. no-loopback-test = <1>;
  178. interrupt-parent = <&plic0>;
  179. };
  180. mac0: mac@e0100000 {
  181. compatible = "andestech,atmac100";
  182. reg = <0x0 0xe0100000 0x0 0x1000>;
  183. interrupts = <19 4>;
  184. interrupt-parent = <&plic0>;
  185. };
  186. mmc0: mmc@f0e00000 {
  187. compatible = "andestech,atfsdc010";
  188. max-frequency = <100000000>;
  189. clock-freq-min-max = <400000 100000000>;
  190. fifo-depth = <0x10>;
  191. reg = <0x0 0xf0e00000 0x0 0x1000>;
  192. interrupts = <18 4>;
  193. cap-sd-highspeed;
  194. interrupt-parent = <&plic0>;
  195. };
  196. dma0: dma@f0c00000 {
  197. compatible = "andestech,atcdmac300";
  198. reg = <0x0 0xf0c00000 0x0 0x1000>;
  199. interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>;
  200. dma-channels = <8>;
  201. interrupt-parent = <&plic0>;
  202. };
  203. lcd0: lcd@e0200000 {
  204. compatible = "andestech,atflcdc100";
  205. reg = <0x0 0xe0200000 0x0 0x1000>;
  206. interrupts = <20 4>;
  207. interrupt-parent = <&plic0>;
  208. };
  209. smc0: smc@e0400000 {
  210. compatible = "andestech,atfsmc020";
  211. reg = <0x0 0xe0400000 0x0 0x1000>;
  212. };
  213. snd0: snd@f0d00000 {
  214. compatible = "andestech,atfac97";
  215. reg = <0x0 0xf0d00000 0x0 0x1000>;
  216. interrupts = <17 4>;
  217. interrupt-parent = <&plic0>;
  218. };
  219. pmu {
  220. compatible = "riscv,base-pmu";
  221. };
  222. virtio_mmio@fe007000 {
  223. interrupts = <0x17 0x4>;
  224. interrupt-parent = <0x2>;
  225. reg = <0x0 0xfe007000 0x0 0x1000>;
  226. compatible = "virtio,mmio";
  227. };
  228. virtio_mmio@fe006000 {
  229. interrupts = <0x16 0x4>;
  230. interrupt-parent = <0x2>;
  231. reg = <0x0 0xfe006000 0x0 0x1000>;
  232. compatible = "virtio,mmio";
  233. };
  234. virtio_mmio@fe005000 {
  235. interrupts = <0x15 0x4>;
  236. interrupt-parent = <0x2>;
  237. reg = <0x0 0xfe005000 0x0 0x1000>;
  238. compatible = "virtio,mmio";
  239. };
  240. virtio_mmio@fe004000 {
  241. interrupts = <0x14 0x4>;
  242. interrupt-parent = <0x2>;
  243. reg = <0x0 0xfe004000 0x0 0x1000>;
  244. compatible = "virtio,mmio";
  245. };
  246. virtio_mmio@fe003000 {
  247. interrupts = <0x13 0x4>;
  248. interrupt-parent = <0x2>;
  249. reg = <0x0 0xfe003000 0x0 0x1000>;
  250. compatible = "virtio,mmio";
  251. };
  252. virtio_mmio@fe002000 {
  253. interrupts = <0x12 0x4>;
  254. interrupt-parent = <0x2>;
  255. reg = <0x0 0xfe002000 0x0 0x1000>;
  256. compatible = "virtio,mmio";
  257. };
  258. virtio_mmio@fe001000 {
  259. interrupts = <0x11 0x4>;
  260. interrupt-parent = <0x2>;
  261. reg = <0x0 0xfe001000 0x0 0x1000>;
  262. compatible = "virtio,mmio";
  263. };
  264. virtio_mmio@fe000000 {
  265. interrupts = <0x10 0x4>;
  266. interrupt-parent = <0x2>;
  267. reg = <0x0 0xfe000000 0x0 0x1000>;
  268. compatible = "virtio,mmio";
  269. };
  270. nor@0,0 {
  271. #address-cells = <2>;
  272. #size-cells = <2>;
  273. compatible = "cfi-flash";
  274. reg = <0x0 0x88000000 0x0 0x4000000>;
  275. bank-width = <2>;
  276. device-width = <1>;
  277. };
  278. spi: spi@f0b00000 {
  279. compatible = "andestech,atcspi200";
  280. reg = <0x0 0xf0b00000 0x0 0x1000>;
  281. #address-cells = <1>;
  282. #size-cells = <0>;
  283. num-cs = <1>;
  284. clocks = <&spiclk>;
  285. interrupts = <4 4>;
  286. interrupt-parent = <&plic0>;
  287. flash@0 {
  288. compatible = "jedec,spi-nor";
  289. spi-max-frequency = <50000000>;
  290. reg = <0>;
  291. spi-cpol;
  292. spi-cpha;
  293. };
  294. };
  295. };