imxrt1050.dtsi 4.5 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
  2. /*
  3. * Copyright (C) 2019
  4. * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
  5. */
  6. #include "armv7-m.dtsi"
  7. #include <dt-bindings/interrupt-controller/arm-gic.h>
  8. #include <dt-bindings/clock/imxrt1050-clock.h>
  9. #include <dt-bindings/gpio/gpio.h>
  10. #include <dt-bindings/memory/imxrt-sdram.h>
  11. / {
  12. #address-cells = <1>;
  13. #size-cells = <1>;
  14. aliases {
  15. display0 = &lcdif;
  16. gpio0 = &gpio1;
  17. gpio1 = &gpio2;
  18. gpio2 = &gpio3;
  19. gpio3 = &gpio4;
  20. gpio4 = &gpio5;
  21. mmc0 = &usdhc1;
  22. serial0 = &lpuart1;
  23. usbphy0 = &usbphy1;
  24. };
  25. clocks {
  26. osc: osc {
  27. compatible = "fsl,imx-osc", "fixed-clock";
  28. #clock-cells = <0>;
  29. clock-frequency = <24000000>;
  30. };
  31. };
  32. soc {
  33. semc: semc@402f0000 {
  34. compatible = "fsl,imxrt-semc";
  35. reg = <0x402f0000 0x4000>;
  36. clocks = <&clks IMXRT1050_CLK_SEMC>;
  37. pinctrl-0 = <&pinctrl_semc>;
  38. pinctrl-names = "default";
  39. status = "okay";
  40. };
  41. lpuart1: serial@40184000 {
  42. compatible = "fsl,imxrt-lpuart";
  43. reg = <0x40184000 0x4000>;
  44. interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  45. clocks = <&clks IMXRT1050_CLK_LPUART1>;
  46. clock-names = "per";
  47. status = "disabled";
  48. };
  49. iomuxc: iomuxc@401f8000 {
  50. compatible = "fsl,imxrt-iomuxc";
  51. reg = <0x401f8000 0x4000>;
  52. fsl,mux_mask = <0x7>;
  53. };
  54. clks: ccm@400fc000 {
  55. compatible = "fsl,imxrt1050-ccm";
  56. reg = <0x400fc000 0x4000>;
  57. interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
  58. <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
  59. #clock-cells = <1>;
  60. };
  61. usdhc1: usdhc@402c0000 {
  62. compatible = "fsl,imxrt-usdhc";
  63. reg = <0x402c0000 0x10000>;
  64. interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
  65. clocks = <&clks IMXRT1050_CLK_USDHC1>;
  66. clock-names = "per";
  67. bus-width = <4>;
  68. fsl,tuning-start-tap = <20>;
  69. fsl,tuning-step= <2>;
  70. status = "disabled";
  71. };
  72. gpio1: gpio@401b8000 {
  73. compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
  74. reg = <0x401b8000 0x4000>;
  75. interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
  76. <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
  77. gpio-controller;
  78. #gpio-cells = <2>;
  79. interrupt-controller;
  80. #interrupt-cells = <2>;
  81. };
  82. gpio2: gpio@401bc000 {
  83. compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
  84. reg = <0x401bc000 0x4000>;
  85. interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
  86. <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
  87. gpio-controller;
  88. #gpio-cells = <2>;
  89. interrupt-controller;
  90. #interrupt-cells = <2>;
  91. };
  92. gpio3: gpio@401c0000 {
  93. compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
  94. reg = <0x401c0000 0x4000>;
  95. interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
  96. <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
  97. gpio-controller;
  98. #gpio-cells = <2>;
  99. interrupt-controller;
  100. #interrupt-cells = <2>;
  101. };
  102. gpio4: gpio@401c4000 {
  103. compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
  104. reg = <0x401c4000 0x4000>;
  105. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
  106. <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
  107. gpio-controller;
  108. #gpio-cells = <2>;
  109. interrupt-controller;
  110. #interrupt-cells = <2>;
  111. };
  112. gpio5: gpio@400c0000 {
  113. compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
  114. reg = <0x400c0000 0x4000>;
  115. interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
  116. <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
  117. gpio-controller;
  118. #gpio-cells = <2>;
  119. interrupt-controller;
  120. #interrupt-cells = <2>;
  121. };
  122. lcdif: lcdif@402b8000 {
  123. compatible = "fsl,imxrt-lcdif";
  124. reg = <0x402b8000 0x4000>;
  125. interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
  126. clocks = <&clks IMXRT1050_CLK_LCDIF_PIX>,
  127. <&clks IMXRT1050_CLK_LCDIF_APB>;
  128. clock-names = "pix", "axi";
  129. assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>;
  130. assigned-clock-parents = <&clks IMXRT1050_CLK_PLL5_VIDEO>;
  131. status = "disabled";
  132. };
  133. gpt1: gpt1@401ec000 {
  134. compatible = "fsl,imxrt-gpt";
  135. reg = <0x401ec000 0x4000>;
  136. interrupts = <100>;
  137. clocks = <&osc>;
  138. status = "disabled";
  139. };
  140. usbphy1: usbphy@400d9000 {
  141. compatible = "fsl,imxrt-usbphy";
  142. reg = <0x400d9000 0x1000>;
  143. interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  144. };
  145. usbmisc: usbmisc@402e0800 {
  146. #index-cells = <1>;
  147. compatible = "fsl,imxrt-usbmisc";
  148. reg = <0x402e0800 0x200>;
  149. clocks = <&clks IMXRT1050_CLK_USBOH3>;
  150. };
  151. usbotg1: usb@402e0000 {
  152. compatible = "fsl,imxrt-usb", "fsl,imx27-usb";
  153. reg = <0x402e0000 0x200>;
  154. interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
  155. clocks = <&clks IMXRT1050_CLK_USBOH3>;
  156. fsl,usbphy = <&usbphy1>;
  157. fsl,usbmisc = <&usbmisc 0>;
  158. ahb-burst-config = <0x0>;
  159. tx-burst-size-dword = <0x10>;
  160. rx-burst-size-dword = <0x10>;
  161. status = "disabled";
  162. };
  163. };
  164. };