imx6qdl-gw5912.dtsi 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2019 Gateworks Corporation
  4. */
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include <dt-bindings/input/linux-event-codes.h>
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. / {
  9. /* these are used by bootloader for disabling nodes */
  10. aliases {
  11. led0 = &led0;
  12. led1 = &led1;
  13. led2 = &led2;
  14. mmc0 = &usdhc3;
  15. nand = &gpmi;
  16. usb0 = &usbh1;
  17. usb1 = &usbotg;
  18. };
  19. chosen {
  20. stdout-path = &uart2;
  21. };
  22. gpio-keys {
  23. compatible = "gpio-keys";
  24. #address-cells = <1>;
  25. #size-cells = <0>;
  26. user-pb {
  27. label = "user_pb";
  28. gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  29. linux,code = <BTN_0>;
  30. };
  31. user-pb1x {
  32. label = "user_pb1x";
  33. linux,code = <BTN_1>;
  34. interrupt-parent = <&gsc>;
  35. interrupts = <0>;
  36. };
  37. key-erased {
  38. label = "key-erased";
  39. linux,code = <BTN_2>;
  40. interrupt-parent = <&gsc>;
  41. interrupts = <1>;
  42. };
  43. eeprom-wp {
  44. label = "eeprom_wp";
  45. linux,code = <BTN_3>;
  46. interrupt-parent = <&gsc>;
  47. interrupts = <2>;
  48. };
  49. tamper {
  50. label = "tamper";
  51. linux,code = <BTN_4>;
  52. interrupt-parent = <&gsc>;
  53. interrupts = <5>;
  54. };
  55. switch-hold {
  56. label = "switch_hold";
  57. linux,code = <BTN_5>;
  58. interrupt-parent = <&gsc>;
  59. interrupts = <7>;
  60. };
  61. };
  62. leds {
  63. compatible = "gpio-leds";
  64. pinctrl-names = "default";
  65. pinctrl-0 = <&pinctrl_gpio_leds>;
  66. led0: user1 {
  67. label = "user1";
  68. gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  69. default-state = "on";
  70. linux,default-trigger = "heartbeat";
  71. };
  72. led1: user2 {
  73. label = "user2";
  74. gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  75. default-state = "off";
  76. };
  77. led2: user3 {
  78. label = "user3";
  79. gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  80. default-state = "off";
  81. };
  82. };
  83. memory@10000000 {
  84. device_type = "memory";
  85. reg = <0x10000000 0x40000000>;
  86. };
  87. pps {
  88. compatible = "pps-gpio";
  89. pinctrl-names = "default";
  90. pinctrl-0 = <&pinctrl_pps>;
  91. gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  92. };
  93. reg_3p3v: regulator-3p3v {
  94. compatible = "regulator-fixed";
  95. regulator-name = "3P3V";
  96. regulator-min-microvolt = <3300000>;
  97. regulator-max-microvolt = <3300000>;
  98. regulator-always-on;
  99. };
  100. reg_usb_vbus: regulator-5p0v {
  101. compatible = "regulator-fixed";
  102. regulator-name = "usb_vbus";
  103. regulator-min-microvolt = <5000000>;
  104. regulator-max-microvolt = <5000000>;
  105. regulator-always-on;
  106. };
  107. };
  108. &can1 {
  109. pinctrl-names = "default";
  110. pinctrl-0 = <&pinctrl_flexcan1>;
  111. status = "okay";
  112. };
  113. &ecspi2 {
  114. cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
  115. pinctrl-names = "default";
  116. pinctrl-0 = <&pinctrl_ecspi2>;
  117. status = "okay";
  118. };
  119. &fec {
  120. pinctrl-names = "default";
  121. pinctrl-0 = <&pinctrl_enet>;
  122. phy-mode = "rgmii-id";
  123. phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
  124. phy-reset-duration = <10>;
  125. phy-reset-post-delay = <100>;
  126. status = "okay";
  127. };
  128. &gpmi {
  129. pinctrl-names = "default";
  130. pinctrl-0 = <&pinctrl_gpmi_nand>;
  131. status = "okay";
  132. };
  133. &i2c1 {
  134. clock-frequency = <100000>;
  135. pinctrl-names = "default";
  136. pinctrl-0 = <&pinctrl_i2c1>;
  137. status = "okay";
  138. gsc: gsc@20 {
  139. compatible = "gw,gsc";
  140. reg = <0x20>;
  141. interrupt-parent = <&gpio1>;
  142. interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
  143. interrupt-controller;
  144. #interrupt-cells = <1>;
  145. #address-cells = <1>;
  146. #size-cells = <0>;
  147. adc {
  148. compatible = "gw,gsc-adc";
  149. #address-cells = <1>;
  150. #size-cells = <0>;
  151. channel@0 {
  152. gw,mode = <0>;
  153. reg = <0x00>;
  154. label = "temp";
  155. };
  156. channel@2 {
  157. gw,mode = <1>;
  158. reg = <0x02>;
  159. label = "vdd_vin";
  160. };
  161. channel@5 {
  162. gw,mode = <1>;
  163. reg = <0x05>;
  164. label = "vdd_3p3";
  165. };
  166. channel@8 {
  167. gw,mode = <1>;
  168. reg = <0x08>;
  169. label = "vdd_bat";
  170. };
  171. channel@b {
  172. gw,mode = <1>;
  173. reg = <0x0b>;
  174. label = "vdd_5p0";
  175. };
  176. channel@e {
  177. gw,mode = <1>;
  178. reg = <0xe>;
  179. label = "vdd_arm";
  180. };
  181. channel@11 {
  182. gw,mode = <1>;
  183. reg = <0x11>;
  184. label = "vdd_soc";
  185. };
  186. channel@14 {
  187. gw,mode = <1>;
  188. reg = <0x14>;
  189. label = "vdd_3p0";
  190. };
  191. channel@17 {
  192. gw,mode = <1>;
  193. reg = <0x17>;
  194. label = "vdd_1p5";
  195. };
  196. channel@1d {
  197. gw,mode = <1>;
  198. reg = <0x1d>;
  199. label = "vdd_1p8";
  200. };
  201. channel@20 {
  202. gw,mode = <1>;
  203. reg = <0x20>;
  204. label = "vdd_1p0";
  205. };
  206. channel@23 {
  207. gw,mode = <1>;
  208. reg = <0x23>;
  209. label = "vdd_2p5";
  210. };
  211. };
  212. fan-controller@a {
  213. compatible = "gw,gsc-fan";
  214. #address-cells = <1>;
  215. #size-cells = <0>;
  216. reg = <0x0a>;
  217. };
  218. };
  219. gsc_gpio: gpio@23 {
  220. compatible = "nxp,pca9555";
  221. reg = <0x23>;
  222. gpio-controller;
  223. #gpio-cells = <2>;
  224. interrupt-parent = <&gsc>;
  225. interrupts = <4>;
  226. };
  227. eeprom@50 {
  228. compatible = "atmel,24c02";
  229. reg = <0x50>;
  230. pagesize = <16>;
  231. };
  232. eeprom@51 {
  233. compatible = "atmel,24c02";
  234. reg = <0x51>;
  235. pagesize = <16>;
  236. };
  237. eeprom@52 {
  238. compatible = "atmel,24c02";
  239. reg = <0x52>;
  240. pagesize = <16>;
  241. };
  242. eeprom@53 {
  243. compatible = "atmel,24c02";
  244. reg = <0x53>;
  245. pagesize = <16>;
  246. };
  247. rtc@68 {
  248. compatible = "dallas,ds1672";
  249. reg = <0x68>;
  250. };
  251. };
  252. &i2c2 {
  253. clock-frequency = <100000>;
  254. pinctrl-names = "default";
  255. pinctrl-0 = <&pinctrl_i2c2>;
  256. status = "okay";
  257. };
  258. &i2c3 {
  259. clock-frequency = <100000>;
  260. pinctrl-names = "default";
  261. pinctrl-0 = <&pinctrl_i2c3>;
  262. status = "okay";
  263. accel@19 {
  264. pinctrl-names = "default";
  265. pinctrl-0 = <&pinctrl_accel>;
  266. compatible = "st,lis2de12";
  267. reg = <0x19>;
  268. st,drdy-int-pin = <1>;
  269. interrupt-parent = <&gpio7>;
  270. interrupts = <13 0>;
  271. interrupt-names = "INT1";
  272. };
  273. };
  274. &pcie {
  275. pinctrl-names = "default";
  276. pinctrl-0 = <&pinctrl_pcie>;
  277. reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
  278. status = "okay";
  279. };
  280. &pwm1 {
  281. pinctrl-names = "default";
  282. pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
  283. status = "disabled";
  284. };
  285. &pwm2 {
  286. pinctrl-names = "default";
  287. pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  288. status = "disabled";
  289. };
  290. &pwm3 {
  291. pinctrl-names = "default";
  292. pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  293. status = "disabled";
  294. };
  295. &pwm4 {
  296. pinctrl-names = "default";
  297. pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
  298. status = "disabled";
  299. };
  300. &uart1 {
  301. pinctrl-names = "default";
  302. pinctrl-0 = <&pinctrl_uart1>;
  303. rts-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
  304. status = "okay";
  305. };
  306. &uart2 {
  307. pinctrl-names = "default";
  308. pinctrl-0 = <&pinctrl_uart2>;
  309. status = "okay";
  310. };
  311. &uart5 {
  312. pinctrl-names = "default";
  313. pinctrl-0 = <&pinctrl_uart5>;
  314. status = "okay";
  315. };
  316. &usbotg {
  317. vbus-supply = <&reg_usb_vbus>;
  318. pinctrl-names = "default";
  319. pinctrl-0 = <&pinctrl_usbotg>;
  320. disable-over-current;
  321. dr_mode = "host";
  322. status = "okay";
  323. };
  324. &usbh1 {
  325. vbus-supply = <&reg_usb_vbus>;
  326. status = "okay";
  327. };
  328. &usdhc3 {
  329. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  330. pinctrl-0 = <&pinctrl_usdhc3>;
  331. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  332. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  333. cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
  334. vmmc-supply = <&reg_3p3v>;
  335. no-1-8-v; /* firmware will remove if board revision supports */
  336. status = "okay";
  337. };
  338. &wdog1 {
  339. status = "disabled";
  340. };
  341. &wdog2 {
  342. pinctrl-names = "default";
  343. pinctrl-0 = <&pinctrl_wdog>;
  344. fsl,ext-reset-output;
  345. status = "okay";
  346. };
  347. &iomuxc {
  348. pinctrl_accel: accelmuxgrp {
  349. fsl,pins = <
  350. MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
  351. >;
  352. };
  353. pinctrl_enet: enetgrp {
  354. fsl,pins = <
  355. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  356. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  357. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  358. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  359. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  360. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  361. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  362. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  363. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  364. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  365. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  366. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  367. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  368. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  369. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  370. MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
  371. >;
  372. };
  373. pinctrl_ecspi2: escpi2grp {
  374. fsl,pins = <
  375. MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
  376. MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
  377. MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
  378. MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1
  379. >;
  380. };
  381. pinctrl_flexcan1: flexcan1grp {
  382. fsl,pins = <
  383. MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
  384. MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
  385. MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0
  386. >;
  387. };
  388. pinctrl_gpio_leds: gpioledsgrp {
  389. fsl,pins = <
  390. MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
  391. MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
  392. MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
  393. >;
  394. };
  395. pinctrl_gpmi_nand: gpminandgrp {
  396. fsl,pins = <
  397. MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
  398. MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
  399. MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
  400. MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  401. MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
  402. MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
  403. MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
  404. MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
  405. MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
  406. MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
  407. MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
  408. MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
  409. MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
  410. MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
  411. MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
  412. >;
  413. };
  414. pinctrl_i2c1: i2c1grp {
  415. fsl,pins = <
  416. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  417. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  418. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
  419. >;
  420. };
  421. pinctrl_i2c2: i2c2grp {
  422. fsl,pins = <
  423. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  424. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  425. >;
  426. };
  427. pinctrl_i2c3: i2c3grp {
  428. fsl,pins = <
  429. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  430. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  431. >;
  432. };
  433. pinctrl_pcie: pciegrp {
  434. fsl,pins = <
  435. MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
  436. MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
  437. >;
  438. };
  439. pinctrl_pps: ppsgrp {
  440. fsl,pins = <
  441. MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
  442. >;
  443. };
  444. pinctrl_pwm1: pwm1grp {
  445. fsl,pins = <
  446. MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
  447. >;
  448. };
  449. pinctrl_pwm2: pwm2grp {
  450. fsl,pins = <
  451. MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  452. >;
  453. };
  454. pinctrl_pwm3: pwm3grp {
  455. fsl,pins = <
  456. MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
  457. >;
  458. };
  459. pinctrl_pwm4: pwm4grp {
  460. fsl,pins = <
  461. MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
  462. >;
  463. };
  464. pinctrl_uart1: uart1grp {
  465. fsl,pins = <
  466. MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
  467. MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
  468. MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b1
  469. >;
  470. };
  471. pinctrl_uart2: uart2grp {
  472. fsl,pins = <
  473. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  474. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  475. MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b1
  476. >;
  477. };
  478. pinctrl_uart5: uart5grp {
  479. fsl,pins = <
  480. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  481. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  482. >;
  483. };
  484. pinctrl_usbotg: usbotggrp {
  485. fsl,pins = <
  486. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
  487. >;
  488. };
  489. pinctrl_usdhc3: usdhc3grp {
  490. fsl,pins = <
  491. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  492. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  493. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  494. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  495. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  496. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  497. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
  498. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
  499. >;
  500. };
  501. pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
  502. fsl,pins = <
  503. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
  504. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
  505. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
  506. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
  507. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
  508. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
  509. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
  510. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
  511. >;
  512. };
  513. pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
  514. fsl,pins = <
  515. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
  516. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
  517. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
  518. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
  519. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
  520. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
  521. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
  522. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
  523. >;
  524. };
  525. pinctrl_wdog: wdoggrp {
  526. fsl,pins = <
  527. MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0
  528. >;
  529. };
  530. };