imx6qdl-gw5907.dtsi 9.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2019 Gateworks Corporation
  4. */
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include <dt-bindings/input/linux-event-codes.h>
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. / {
  9. /* these are used by bootloader for disabling nodes */
  10. aliases {
  11. led0 = &led0;
  12. led1 = &led1;
  13. nand = &gpmi;
  14. usb0 = &usbh1;
  15. usb1 = &usbotg;
  16. };
  17. chosen {
  18. stdout-path = &uart2;
  19. };
  20. gpio-keys {
  21. compatible = "gpio-keys";
  22. #address-cells = <1>;
  23. #size-cells = <0>;
  24. user-pb {
  25. label = "user_pb";
  26. gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  27. linux,code = <BTN_0>;
  28. };
  29. user-pb1x {
  30. label = "user_pb1x";
  31. linux,code = <BTN_1>;
  32. interrupt-parent = <&gsc>;
  33. interrupts = <0>;
  34. };
  35. key-erased {
  36. label = "key-erased";
  37. linux,code = <BTN_2>;
  38. interrupt-parent = <&gsc>;
  39. interrupts = <1>;
  40. };
  41. eeprom-wp {
  42. label = "eeprom_wp";
  43. linux,code = <BTN_3>;
  44. interrupt-parent = <&gsc>;
  45. interrupts = <2>;
  46. };
  47. tamper {
  48. label = "tamper";
  49. linux,code = <BTN_4>;
  50. interrupt-parent = <&gsc>;
  51. interrupts = <5>;
  52. };
  53. switch-hold {
  54. label = "switch_hold";
  55. linux,code = <BTN_5>;
  56. interrupt-parent = <&gsc>;
  57. interrupts = <7>;
  58. };
  59. };
  60. leds {
  61. compatible = "gpio-leds";
  62. pinctrl-names = "default";
  63. pinctrl-0 = <&pinctrl_gpio_leds>;
  64. led0: user1 {
  65. label = "user1";
  66. gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  67. default-state = "on";
  68. linux,default-trigger = "heartbeat";
  69. };
  70. led1: user2 {
  71. label = "user2";
  72. gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  73. default-state = "off";
  74. };
  75. };
  76. memory@10000000 {
  77. device_type = "memory";
  78. reg = <0x10000000 0x20000000>;
  79. };
  80. pps {
  81. compatible = "pps-gpio";
  82. pinctrl-names = "default";
  83. pinctrl-0 = <&pinctrl_pps>;
  84. gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  85. status = "okay";
  86. };
  87. reg_3p3v: regulator-3p3v {
  88. compatible = "regulator-fixed";
  89. regulator-name = "3P3V";
  90. regulator-min-microvolt = <3300000>;
  91. regulator-max-microvolt = <3300000>;
  92. regulator-always-on;
  93. };
  94. reg_5p0v: regulator-5p0v {
  95. compatible = "regulator-fixed";
  96. regulator-name = "5P0V";
  97. regulator-min-microvolt = <5000000>;
  98. regulator-max-microvolt = <5000000>;
  99. regulator-always-on;
  100. };
  101. reg_usb_otg_vbus: regulator-usb-otg-vbus {
  102. compatible = "regulator-fixed";
  103. regulator-name = "usb_otg_vbus";
  104. regulator-min-microvolt = <5000000>;
  105. regulator-max-microvolt = <5000000>;
  106. gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  107. enable-active-high;
  108. };
  109. };
  110. &fec {
  111. pinctrl-names = "default";
  112. pinctrl-0 = <&pinctrl_enet>;
  113. phy-mode = "rgmii-id";
  114. phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
  115. phy-reset-duration = <10>;
  116. phy-reset-post-delay = <100>;
  117. status = "okay";
  118. };
  119. &gpmi {
  120. pinctrl-names = "default";
  121. pinctrl-0 = <&pinctrl_gpmi_nand>;
  122. status = "okay";
  123. };
  124. &hdmi {
  125. ddc-i2c-bus = <&i2c3>;
  126. status = "okay";
  127. };
  128. &i2c1 {
  129. clock-frequency = <100000>;
  130. pinctrl-names = "default";
  131. pinctrl-0 = <&pinctrl_i2c1>;
  132. status = "okay";
  133. gsc: gsc@20 {
  134. compatible = "gw,gsc";
  135. reg = <0x20>;
  136. interrupt-parent = <&gpio1>;
  137. interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
  138. interrupt-controller;
  139. #interrupt-cells = <1>;
  140. #size-cells = <0>;
  141. adc {
  142. compatible = "gw,gsc-adc";
  143. #address-cells = <1>;
  144. #size-cells = <0>;
  145. channel@0 {
  146. gw,mode = <0>;
  147. reg = <0x00>;
  148. label = "temp";
  149. };
  150. channel@2 {
  151. gw,mode = <1>;
  152. reg = <0x02>;
  153. label = "vdd_vin";
  154. };
  155. channel@5 {
  156. gw,mode = <1>;
  157. reg = <0x05>;
  158. label = "vdd_3p3";
  159. };
  160. channel@8 {
  161. gw,mode = <1>;
  162. reg = <0x08>;
  163. label = "vdd_bat";
  164. };
  165. channel@b {
  166. gw,mode = <1>;
  167. reg = <0x0b>;
  168. label = "vdd_5p0";
  169. };
  170. channel@e {
  171. gw,mode = <1>;
  172. reg = <0xe>;
  173. label = "vdd_arm";
  174. };
  175. channel@11 {
  176. gw,mode = <1>;
  177. reg = <0x11>;
  178. label = "vdd_soc";
  179. };
  180. channel@14 {
  181. gw,mode = <1>;
  182. reg = <0x14>;
  183. label = "vdd_3p0";
  184. };
  185. channel@17 {
  186. gw,mode = <1>;
  187. reg = <0x17>;
  188. label = "vdd_1p5";
  189. };
  190. channel@1d {
  191. gw,mode = <1>;
  192. reg = <0x1d>;
  193. label = "vdd_1p8";
  194. };
  195. channel@20 {
  196. gw,mode = <1>;
  197. reg = <0x20>;
  198. label = "vdd_an1";
  199. };
  200. channel@23 {
  201. gw,mode = <1>;
  202. reg = <0x23>;
  203. label = "vdd_2p5";
  204. };
  205. };
  206. };
  207. gsc_gpio: gpio@23 {
  208. compatible = "nxp,pca9555";
  209. reg = <0x23>;
  210. gpio-controller;
  211. #gpio-cells = <2>;
  212. interrupt-parent = <&gsc>;
  213. interrupts = <4>;
  214. };
  215. eeprom@50 {
  216. compatible = "atmel,24c02";
  217. reg = <0x50>;
  218. pagesize = <16>;
  219. };
  220. eeprom@51 {
  221. compatible = "atmel,24c02";
  222. reg = <0x51>;
  223. pagesize = <16>;
  224. };
  225. eeprom@52 {
  226. compatible = "atmel,24c02";
  227. reg = <0x52>;
  228. pagesize = <16>;
  229. };
  230. eeprom@53 {
  231. compatible = "atmel,24c02";
  232. reg = <0x53>;
  233. pagesize = <16>;
  234. };
  235. ds1672@68 {
  236. compatible = "dallas,ds1672";
  237. reg = <0x68>;
  238. };
  239. };
  240. &i2c2 {
  241. clock-frequency = <100000>;
  242. pinctrl-names = "default";
  243. pinctrl-0 = <&pinctrl_i2c2>;
  244. status = "okay";
  245. };
  246. &i2c3 {
  247. clock-frequency = <100000>;
  248. pinctrl-names = "default";
  249. pinctrl-0 = <&pinctrl_i2c3>;
  250. status = "okay";
  251. gpio@20 {
  252. compatible = "nxp,pca9555";
  253. reg = <0x20>;
  254. gpio-controller;
  255. #gpio-cells = <2>;
  256. };
  257. adc@48 {
  258. compatible = "ti,ads1015";
  259. reg = <0x48>;
  260. #address-cells = <1>;
  261. #size-cells = <0>;
  262. channel@4 {
  263. reg = <4>;
  264. ti,gain = <0>;
  265. ti,datarate = <5>;
  266. };
  267. channel@5 {
  268. reg = <5>;
  269. ti,gain = <0>;
  270. ti,datarate = <5>;
  271. };
  272. channel@6 {
  273. reg = <6>;
  274. ti,gain = <0>;
  275. ti,datarate = <5>;
  276. };
  277. };
  278. };
  279. &pcie {
  280. pinctrl-names = "default";
  281. pinctrl-0 = <&pinctrl_pcie>;
  282. reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
  283. status = "okay";
  284. };
  285. &pwm2 {
  286. pinctrl-names = "default";
  287. pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  288. status = "disabled";
  289. };
  290. &pwm3 {
  291. pinctrl-names = "default";
  292. pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  293. status = "disabled";
  294. };
  295. &pwm4 {
  296. pinctrl-names = "default";
  297. pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
  298. status = "disabled";
  299. };
  300. &uart1 {
  301. pinctrl-names = "default";
  302. pinctrl-0 = <&pinctrl_uart1>;
  303. status = "okay";
  304. };
  305. &uart2 {
  306. pinctrl-names = "default";
  307. pinctrl-0 = <&pinctrl_uart2>;
  308. status = "okay";
  309. };
  310. &uart3 {
  311. pinctrl-names = "default";
  312. pinctrl-0 = <&pinctrl_uart3>;
  313. status = "okay";
  314. };
  315. &uart5 {
  316. pinctrl-names = "default";
  317. pinctrl-0 = <&pinctrl_uart5>;
  318. status = "okay";
  319. };
  320. &usbotg {
  321. vbus-supply = <&reg_usb_otg_vbus>;
  322. pinctrl-names = "default";
  323. pinctrl-0 = <&pinctrl_usbotg>;
  324. disable-over-current;
  325. dr_mode = "otg";
  326. status = "okay";
  327. };
  328. &usbh1 {
  329. status = "okay";
  330. };
  331. &wdog1 {
  332. pinctrl-names = "default";
  333. pinctrl-0 = <&pinctrl_wdog>;
  334. fsl,ext-reset-output;
  335. };
  336. &iomuxc {
  337. pinctrl_enet: enetgrp {
  338. fsl,pins = <
  339. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
  340. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
  341. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
  342. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
  343. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
  344. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
  345. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
  346. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
  347. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
  348. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
  349. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
  350. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
  351. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  352. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  353. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  354. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  355. MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
  356. >;
  357. };
  358. pinctrl_gpio_leds: gpioledsgrp {
  359. fsl,pins = <
  360. MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
  361. MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
  362. >;
  363. };
  364. pinctrl_gpmi_nand: gpminandgrp {
  365. fsl,pins = <
  366. MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
  367. MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
  368. MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
  369. MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  370. MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
  371. MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
  372. MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
  373. MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
  374. MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
  375. MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
  376. MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
  377. MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
  378. MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
  379. MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
  380. MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
  381. >;
  382. };
  383. pinctrl_i2c1: i2c1grp {
  384. fsl,pins = <
  385. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  386. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  387. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
  388. >;
  389. };
  390. pinctrl_i2c2: i2c2grp {
  391. fsl,pins = <
  392. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  393. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  394. >;
  395. };
  396. pinctrl_i2c3: i2c3grp {
  397. fsl,pins = <
  398. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  399. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  400. MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
  401. MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
  402. >;
  403. };
  404. pinctrl_pcie: pciegrp {
  405. fsl,pins = <
  406. MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
  407. >;
  408. };
  409. pinctrl_pps: ppsgrp {
  410. fsl,pins = <
  411. MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
  412. >;
  413. };
  414. pinctrl_pwm2: pwm2grp {
  415. fsl,pins = <
  416. MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  417. >;
  418. };
  419. pinctrl_pwm3: pwm3grp {
  420. fsl,pins = <
  421. MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
  422. >;
  423. };
  424. pinctrl_pwm4: pwm4grp {
  425. fsl,pins = <
  426. MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
  427. >;
  428. };
  429. pinctrl_uart1: uart1grp {
  430. fsl,pins = <
  431. MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
  432. MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
  433. >;
  434. };
  435. pinctrl_uart2: uart2grp {
  436. fsl,pins = <
  437. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  438. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  439. >;
  440. };
  441. pinctrl_uart3: uart3grp {
  442. fsl,pins = <
  443. MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
  444. MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
  445. >;
  446. };
  447. pinctrl_uart5: uart5grp {
  448. fsl,pins = <
  449. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  450. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  451. >;
  452. };
  453. pinctrl_usbotg: usbotggrp {
  454. fsl,pins = <
  455. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
  456. MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
  457. >;
  458. };
  459. pinctrl_wdog: wdoggrp {
  460. fsl,pins = <
  461. MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
  462. >;
  463. };
  464. };