imx6qdl-gw560x.dtsi 21 KB

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  1. /*
  2. * Copyright 2017 Gateworks Corporation
  3. *
  4. * This file is dual-licensed: you can use it either under the terms
  5. * of the GPL or the X11 license, at your option. Note that this dual
  6. * licensing only applies to this file, and not this project as a
  7. * whole.
  8. *
  9. * a) This file is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This file is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public
  20. * License along with this file; if not, write to the Free
  21. * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22. * MA 02110-1301 USA
  23. *
  24. * Or, alternatively,
  25. *
  26. * b) Permission is hereby granted, free of charge, to any person
  27. * obtaining a copy of this software and associated documentation
  28. * files (the "Software"), to deal in the Software without
  29. * restriction, including without limitation the rights to use,
  30. * copy, modify, merge, publish, distribute, sublicense, and/or
  31. * sell copies of the Software, and to permit persons to whom the
  32. * Software is furnished to do so, subject to the following
  33. * conditions:
  34. *
  35. * The above copyright notice and this permission notice shall be
  36. * included in all copies or substantial portions of the Software.
  37. *
  38. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45. * OTHER DEALINGS IN THE SOFTWARE.
  46. */
  47. #include <dt-bindings/gpio/gpio.h>
  48. #include <dt-bindings/input/input.h>
  49. #include <dt-bindings/interrupt-controller/irq.h>
  50. / {
  51. /* these are used by bootloader for disabling nodes */
  52. aliases {
  53. led0 = &led0;
  54. led1 = &led1;
  55. led2 = &led2;
  56. mmc0 = &usdhc2;
  57. mmc1 = &usdhc3;
  58. ssi0 = &ssi1;
  59. usb0 = &usbh1;
  60. usb1 = &usbotg;
  61. };
  62. chosen {
  63. stdout-path = &uart2;
  64. };
  65. backlight-display {
  66. compatible = "pwm-backlight";
  67. pwms = <&pwm4 0 5000000>;
  68. brightness-levels = <
  69. 0 1 2 3 4 5 6 7 8 9
  70. 10 11 12 13 14 15 16 17 18 19
  71. 20 21 22 23 24 25 26 27 28 29
  72. 30 31 32 33 34 35 36 37 38 39
  73. 40 41 42 43 44 45 46 47 48 49
  74. 50 51 52 53 54 55 56 57 58 59
  75. 60 61 62 63 64 65 66 67 68 69
  76. 70 71 72 73 74 75 76 77 78 79
  77. 80 81 82 83 84 85 86 87 88 89
  78. 90 91 92 93 94 95 96 97 98 99
  79. 100
  80. >;
  81. default-brightness-level = <100>;
  82. };
  83. backlight-keypad {
  84. compatible = "gpio-backlight";
  85. gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
  86. default-on;
  87. };
  88. gpio-keys {
  89. compatible = "gpio-keys";
  90. #address-cells = <1>;
  91. #size-cells = <0>;
  92. user-pb {
  93. label = "user_pb";
  94. gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  95. linux,code = <BTN_0>;
  96. };
  97. user-pb1x {
  98. label = "user_pb1x";
  99. linux,code = <BTN_1>;
  100. interrupt-parent = <&gsc>;
  101. interrupts = <0>;
  102. };
  103. key-erased {
  104. label = "key-erased";
  105. linux,code = <BTN_2>;
  106. interrupt-parent = <&gsc>;
  107. interrupts = <1>;
  108. };
  109. eeprom-wp {
  110. label = "eeprom_wp";
  111. linux,code = <BTN_3>;
  112. interrupt-parent = <&gsc>;
  113. interrupts = <2>;
  114. };
  115. tamper {
  116. label = "tamper";
  117. linux,code = <BTN_4>;
  118. interrupt-parent = <&gsc>;
  119. interrupts = <5>;
  120. };
  121. switch-hold {
  122. label = "switch_hold";
  123. linux,code = <BTN_5>;
  124. interrupt-parent = <&gsc>;
  125. interrupts = <7>;
  126. };
  127. };
  128. leds {
  129. compatible = "gpio-leds";
  130. pinctrl-names = "default";
  131. pinctrl-0 = <&pinctrl_gpio_leds>;
  132. led0: user1 {
  133. label = "user1";
  134. gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  135. default-state = "on";
  136. linux,default-trigger = "heartbeat";
  137. };
  138. led1: user2 {
  139. label = "user2";
  140. gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  141. default-state = "off";
  142. };
  143. led2: user3 {
  144. label = "user3";
  145. gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  146. default-state = "off";
  147. };
  148. };
  149. memory@10000000 {
  150. device_type = "memory";
  151. reg = <0x10000000 0x40000000>;
  152. };
  153. pps {
  154. compatible = "pps-gpio";
  155. pinctrl-names = "default";
  156. pinctrl-0 = <&pinctrl_pps>;
  157. gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  158. };
  159. reg_2p5v: regulator-2p5v {
  160. compatible = "regulator-fixed";
  161. regulator-name = "2P5V";
  162. regulator-min-microvolt = <2500000>;
  163. regulator-max-microvolt = <2500000>;
  164. regulator-always-on;
  165. };
  166. reg_3p3v: regulator-3p3v {
  167. compatible = "regulator-fixed";
  168. regulator-name = "3P3V";
  169. regulator-min-microvolt = <3300000>;
  170. regulator-max-microvolt = <3300000>;
  171. regulator-always-on;
  172. };
  173. reg_5p0v: regulator-5p0v {
  174. compatible = "regulator-fixed";
  175. regulator-name = "5P0V";
  176. regulator-min-microvolt = <5000000>;
  177. regulator-max-microvolt = <5000000>;
  178. regulator-always-on;
  179. };
  180. reg_12p0v: regulator-12p0v {
  181. compatible = "regulator-fixed";
  182. regulator-name = "12P0V";
  183. regulator-min-microvolt = <12000000>;
  184. regulator-max-microvolt = <12000000>;
  185. gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
  186. enable-active-high;
  187. };
  188. reg_1p4v: regulator-vddsoc {
  189. compatible = "regulator-fixed";
  190. regulator-name = "vdd_soc";
  191. regulator-min-microvolt = <1400000>;
  192. regulator-max-microvolt = <1400000>;
  193. regulator-always-on;
  194. };
  195. reg_usb_h1_vbus: regulator-usb-h1-vbus {
  196. compatible = "regulator-fixed";
  197. regulator-name = "usb_h1_vbus";
  198. regulator-min-microvolt = <5000000>;
  199. regulator-max-microvolt = <5000000>;
  200. regulator-always-on;
  201. };
  202. reg_usb_otg_vbus: regulator-usb-otg-vbus {
  203. compatible = "regulator-fixed";
  204. regulator-name = "usb_otg_vbus";
  205. regulator-min-microvolt = <5000000>;
  206. regulator-max-microvolt = <5000000>;
  207. gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  208. enable-active-high;
  209. };
  210. sound {
  211. compatible = "fsl,imx6q-ventana-sgtl5000",
  212. "fsl,imx-audio-sgtl5000";
  213. model = "sgtl5000-audio";
  214. ssi-controller = <&ssi1>;
  215. audio-codec = <&sgtl5000>;
  216. audio-routing =
  217. "MIC_IN", "Mic Jack",
  218. "Mic Jack", "Mic Bias",
  219. "Headphone Jack", "HP_OUT";
  220. mux-int-port = <1>;
  221. mux-ext-port = <4>;
  222. };
  223. };
  224. &audmux {
  225. pinctrl-names = "default";
  226. pinctrl-0 = <&pinctrl_audmux>;
  227. status = "okay";
  228. };
  229. &ecspi3 {
  230. cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
  231. pinctrl-names = "default";
  232. pinctrl-0 = <&pinctrl_ecspi3>;
  233. status = "okay";
  234. };
  235. &can1 {
  236. pinctrl-names = "default";
  237. pinctrl-0 = <&pinctrl_flexcan>;
  238. status = "okay";
  239. };
  240. &clks {
  241. assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
  242. <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
  243. assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
  244. <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
  245. };
  246. &fec {
  247. pinctrl-names = "default";
  248. pinctrl-0 = <&pinctrl_enet>;
  249. phy-mode = "rgmii-id";
  250. phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
  251. phy-reset-duration = <10>;
  252. phy-reset-post-delay = <100>;
  253. status = "okay";
  254. };
  255. &hdmi {
  256. ddc-i2c-bus = <&i2c3>;
  257. status = "okay";
  258. };
  259. &i2c1 {
  260. clock-frequency = <100000>;
  261. pinctrl-names = "default";
  262. pinctrl-0 = <&pinctrl_i2c1>;
  263. status = "okay";
  264. gsc: gsc@20 {
  265. compatible = "gw,gsc";
  266. reg = <0x20>;
  267. interrupt-parent = <&gpio1>;
  268. interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
  269. interrupt-controller;
  270. #interrupt-cells = <1>;
  271. #size-cells = <0>;
  272. adc {
  273. compatible = "gw,gsc-adc";
  274. #address-cells = <1>;
  275. #size-cells = <0>;
  276. channel@0 {
  277. gw,mode = <0>;
  278. reg = <0x00>;
  279. label = "temp";
  280. };
  281. channel@2 {
  282. gw,mode = <1>;
  283. reg = <0x02>;
  284. label = "vdd_vin";
  285. };
  286. channel@5 {
  287. gw,mode = <1>;
  288. reg = <0x05>;
  289. label = "vdd_3p3";
  290. };
  291. channel@8 {
  292. gw,mode = <1>;
  293. reg = <0x08>;
  294. label = "vdd_bat";
  295. };
  296. channel@b {
  297. gw,mode = <1>;
  298. reg = <0x0b>;
  299. label = "vdd_5p0";
  300. };
  301. channel@e {
  302. gw,mode = <1>;
  303. reg = <0xe>;
  304. label = "vdd_arm";
  305. };
  306. channel@11 {
  307. gw,mode = <1>;
  308. reg = <0x11>;
  309. label = "vdd_soc";
  310. };
  311. channel@14 {
  312. gw,mode = <1>;
  313. reg = <0x14>;
  314. label = "vdd_3p0";
  315. };
  316. channel@17 {
  317. gw,mode = <1>;
  318. reg = <0x17>;
  319. label = "vdd_1p5";
  320. };
  321. channel@1d {
  322. gw,mode = <1>;
  323. reg = <0x1d>;
  324. label = "vdd_1p8";
  325. };
  326. channel@20 {
  327. gw,mode = <1>;
  328. reg = <0x20>;
  329. label = "vdd_an1";
  330. };
  331. channel@23 {
  332. gw,mode = <1>;
  333. reg = <0x23>;
  334. label = "vdd_2p5";
  335. };
  336. channel@26 {
  337. gw,mode = <1>;
  338. reg = <0x26>;
  339. label = "vdd_gps";
  340. };
  341. channel@29 {
  342. gw,mode = <1>;
  343. reg = <0x29>;
  344. label = "vdd_an2";
  345. };
  346. };
  347. };
  348. gsc_gpio: gpio@23 {
  349. compatible = "nxp,pca9555";
  350. reg = <0x23>;
  351. gpio-controller;
  352. #gpio-cells = <2>;
  353. interrupt-parent = <&gsc>;
  354. interrupts = <4>;
  355. };
  356. eeprom1: eeprom@50 {
  357. compatible = "atmel,24c02";
  358. reg = <0x50>;
  359. pagesize = <16>;
  360. };
  361. eeprom2: eeprom@51 {
  362. compatible = "atmel,24c02";
  363. reg = <0x51>;
  364. pagesize = <16>;
  365. };
  366. eeprom3: eeprom@52 {
  367. compatible = "atmel,24c02";
  368. reg = <0x52>;
  369. pagesize = <16>;
  370. };
  371. eeprom4: eeprom@53 {
  372. compatible = "atmel,24c02";
  373. reg = <0x53>;
  374. pagesize = <16>;
  375. };
  376. ds1672: rtc@68 {
  377. compatible = "dallas,ds1672";
  378. reg = <0x68>;
  379. };
  380. };
  381. &i2c2 {
  382. clock-frequency = <100000>;
  383. pinctrl-names = "default";
  384. pinctrl-0 = <&pinctrl_i2c2>;
  385. status = "okay";
  386. sgtl5000: codec@a {
  387. compatible = "fsl,sgtl5000";
  388. reg = <0x0a>;
  389. #sound-dai-cells = <0>;
  390. clocks = <&clks IMX6QDL_CLK_CKO>;
  391. VDDA-supply = <&reg_1p8v>;
  392. VDDIO-supply = <&reg_3p3v>;
  393. };
  394. magn@1c {
  395. compatible = "st,lsm9ds1-magn";
  396. reg = <0x1c>;
  397. pinctrl-names = "default";
  398. pinctrl-0 = <&pinctrl_mag>;
  399. interrupt-parent = <&gpio5>;
  400. interrupts = <9 IRQ_TYPE_EDGE_RISING>;
  401. };
  402. tca8418: keypad@34 {
  403. compatible = "ti,tca8418";
  404. pinctrl-names = "default";
  405. pinctrl-0 = <&pinctrl_keypad>;
  406. reg = <0x34>;
  407. interrupt-parent = <&gpio5>;
  408. interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
  409. linux,keymap = < MATRIX_KEY(0x00, 0x01, BTN_0)
  410. MATRIX_KEY(0x00, 0x00, BTN_1)
  411. MATRIX_KEY(0x01, 0x01, BTN_2)
  412. MATRIX_KEY(0x01, 0x00, BTN_3)
  413. MATRIX_KEY(0x02, 0x00, BTN_4)
  414. MATRIX_KEY(0x00, 0x03, BTN_5)
  415. MATRIX_KEY(0x00, 0x02, BTN_6)
  416. MATRIX_KEY(0x01, 0x03, BTN_7)
  417. MATRIX_KEY(0x01, 0x02, BTN_8)
  418. MATRIX_KEY(0x02, 0x02, BTN_9)
  419. >;
  420. keypad,num-rows = <4>;
  421. keypad,num-columns = <4>;
  422. };
  423. ltc3676: pmic@3c {
  424. compatible = "lltc,ltc3676";
  425. pinctrl-names = "default";
  426. pinctrl-0 = <&pinctrl_pmic>;
  427. reg = <0x3c>;
  428. interrupt-parent = <&gpio1>;
  429. interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
  430. regulators {
  431. /* VDD_DDR (1+R1/R2 = 2.105) */
  432. reg_vdd_ddr: sw2 {
  433. regulator-name = "vddddr";
  434. regulator-min-microvolt = <868310>;
  435. regulator-max-microvolt = <1684000>;
  436. lltc,fb-voltage-divider = <221000 200000>;
  437. regulator-ramp-delay = <7000>;
  438. regulator-boot-on;
  439. regulator-always-on;
  440. };
  441. /* VDD_ARM (1+R1/R2 = 1.931) */
  442. reg_vdd_arm: sw3 {
  443. regulator-name = "vddarm";
  444. regulator-min-microvolt = <796551>;
  445. regulator-max-microvolt = <1544827>;
  446. lltc,fb-voltage-divider = <243000 261000>;
  447. regulator-ramp-delay = <7000>;
  448. regulator-boot-on;
  449. regulator-always-on;
  450. linux,phandle = <&reg_vdd_arm>;
  451. };
  452. /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
  453. reg_1p8v: sw4 {
  454. regulator-name = "vdd1p8";
  455. regulator-min-microvolt = <1033310>;
  456. regulator-max-microvolt = <2004000>;
  457. lltc,fb-voltage-divider = <301000 200000>;
  458. regulator-ramp-delay = <7000>;
  459. regulator-boot-on;
  460. regulator-always-on;
  461. };
  462. /* VDD_1P0 (1+R1/R2 = 1.39): PCIe/ENET-PHY */
  463. reg_1p0v: ldo2 {
  464. regulator-name = "vdd1p0";
  465. regulator-min-microvolt = <950000>;
  466. regulator-max-microvolt = <1050000>;
  467. lltc,fb-voltage-divider = <78700 200000>;
  468. regulator-boot-on;
  469. regulator-always-on;
  470. };
  471. /* VDD_AUD_1P8: Audio codec */
  472. reg_aud_1p8v: ldo3 {
  473. regulator-name = "vdd1p8a";
  474. regulator-min-microvolt = <1800000>;
  475. regulator-max-microvolt = <1800000>;
  476. regulator-boot-on;
  477. };
  478. /* VDD_HIGH (1+R1/R2 = 4.17) */
  479. reg_3p0v: ldo4 {
  480. regulator-name = "vdd3p0";
  481. regulator-min-microvolt = <3023250>;
  482. regulator-max-microvolt = <3023250>;
  483. lltc,fb-voltage-divider = <634000 200000>;
  484. regulator-boot-on;
  485. regulator-always-on;
  486. };
  487. };
  488. };
  489. imu@6a {
  490. compatible = "st,lsm9ds1-imu";
  491. reg = <0x6a>;
  492. st,drdy-int-pin = <1>;
  493. pinctrl-names = "default";
  494. pinctrl-0 = <&pinctrl_imu>;
  495. interrupt-parent = <&gpio5>;
  496. interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
  497. };
  498. };
  499. &i2c3 {
  500. clock-frequency = <100000>;
  501. pinctrl-names = "default";
  502. pinctrl-0 = <&pinctrl_i2c3>;
  503. status = "okay";
  504. egalax_ts: touchscreen@4 {
  505. compatible = "eeti,egalax_ts";
  506. reg = <0x04>;
  507. interrupt-parent = <&gpio5>;
  508. interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
  509. wakeup-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
  510. };
  511. };
  512. &ldb {
  513. fsl,dual-channel;
  514. status = "okay";
  515. lvds-channel@0 {
  516. fsl,data-mapping = "spwg";
  517. fsl,data-width = <18>;
  518. status = "okay";
  519. display-timings {
  520. native-mode = <&timing0>;
  521. timing0: hsd100pxn1 {
  522. clock-frequency = <65000000>;
  523. hactive = <1024>;
  524. vactive = <768>;
  525. hback-porch = <220>;
  526. hfront-porch = <40>;
  527. vback-porch = <21>;
  528. vfront-porch = <7>;
  529. hsync-len = <60>;
  530. vsync-len = <10>;
  531. };
  532. };
  533. };
  534. };
  535. &pcie {
  536. pinctrl-names = "default";
  537. pinctrl-0 = <&pinctrl_pcie>;
  538. reset-gpio = <&gpio4 31 GPIO_ACTIVE_LOW>;
  539. status = "okay";
  540. };
  541. &pwm2 {
  542. pinctrl-names = "default";
  543. pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  544. status = "disabled";
  545. };
  546. &pwm3 {
  547. pinctrl-names = "default";
  548. pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  549. status = "disabled";
  550. };
  551. &pwm4 {
  552. #pwm-cells = <2>;
  553. pinctrl-names = "default";
  554. pinctrl-0 = <&pinctrl_pwm4>;
  555. status = "okay";
  556. };
  557. &ssi1 {
  558. status = "okay";
  559. };
  560. &uart1 {
  561. pinctrl-names = "default";
  562. pinctrl-0 = <&pinctrl_uart1>;
  563. uart-has-rtscts;
  564. rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
  565. status = "okay";
  566. };
  567. &uart2 {
  568. pinctrl-names = "default";
  569. pinctrl-0 = <&pinctrl_uart2>;
  570. status = "okay";
  571. };
  572. &uart5 {
  573. pinctrl-names = "default";
  574. pinctrl-0 = <&pinctrl_uart5>;
  575. status = "okay";
  576. };
  577. &usbotg {
  578. vbus-supply = <&reg_usb_otg_vbus>;
  579. pinctrl-names = "default";
  580. pinctrl-0 = <&pinctrl_usbotg>;
  581. disable-over-current;
  582. dr_mode = "otg";
  583. status = "okay";
  584. };
  585. &usbh1 {
  586. vbus-supply = <&reg_usb_h1_vbus>;
  587. pinctrl-names = "default";
  588. pinctrl-0 = <&pinctrl_usbh1>;
  589. status = "okay";
  590. };
  591. &usdhc2 {
  592. pinctrl-names = "default";
  593. pinctrl-0 = <&pinctrl_usdhc2>;
  594. bus-width = <8>;
  595. vmmc-supply = <&reg_3p3v>;
  596. non-removable;
  597. status = "okay";
  598. };
  599. &usdhc3 {
  600. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  601. pinctrl-0 = <&pinctrl_usdhc3>;
  602. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  603. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  604. cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
  605. vmmc-supply = <&reg_3p3v>;
  606. status = "okay";
  607. };
  608. &wdog1 {
  609. pinctrl-names = "default";
  610. pinctrl-0 = <&pinctrl_wdog>;
  611. fsl,ext-reset-output;
  612. };
  613. &iomuxc {
  614. pinctrl_audmux: audmuxgrp {
  615. fsl,pins = <
  616. /* AUD4 */
  617. MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
  618. MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0
  619. MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
  620. MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
  621. MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
  622. /* AUD6 */
  623. MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0
  624. MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0
  625. MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0
  626. MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0
  627. >;
  628. };
  629. pinctrl_ecspi3: escpi3grp {
  630. fsl,pins = <
  631. MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
  632. MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
  633. MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
  634. MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
  635. >;
  636. };
  637. pinctrl_enet: enetgrp {
  638. fsl,pins = <
  639. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  640. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  641. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  642. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  643. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  644. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  645. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  646. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  647. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  648. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  649. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  650. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  651. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  652. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  653. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  654. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  655. MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */
  656. >;
  657. };
  658. pinctrl_flexcan: flexcangrp {
  659. fsl,pins = <
  660. MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
  661. MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
  662. MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
  663. >;
  664. };
  665. pinctrl_gpio_leds: gpioledsgrp {
  666. fsl,pins = <
  667. MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
  668. MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
  669. MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
  670. >;
  671. };
  672. pinctrl_i2c1: i2c1grp {
  673. fsl,pins = <
  674. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  675. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  676. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
  677. >;
  678. };
  679. pinctrl_i2c2: i2c2grp {
  680. fsl,pins = <
  681. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  682. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  683. >;
  684. };
  685. pinctrl_i2c3: i2c3grp {
  686. fsl,pins = <
  687. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  688. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  689. MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x4001b0b0 /* DIOI2C_DIS# */
  690. MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0001b0b0 /* LVDS_TOUCH_IRQ# */
  691. MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0001b0b0 /* LVDS_BACKEN */
  692. >;
  693. };
  694. pinctrl_imu: imugrp {
  695. fsl,pins = <
  696. MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b0
  697. >;
  698. };
  699. pinctrl_keypad: keypadgrp {
  700. fsl,pins = <
  701. MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0001b0b0 /* KEYPAD_IRQ# */
  702. MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x0001b0b0 /* KEYPAD_LED_EN */
  703. >;
  704. };
  705. pinctrl_mag: maggrp {
  706. fsl,pins = <
  707. MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0
  708. >;
  709. };
  710. pinctrl_pcie: pciegrp {
  711. fsl,pins = <
  712. MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 /* PCI_RST# */
  713. MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */
  714. >;
  715. };
  716. pinctrl_pmic: pmicgrp {
  717. fsl,pins = <
  718. MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
  719. >;
  720. };
  721. pinctrl_pps: ppsgrp {
  722. fsl,pins = <
  723. MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
  724. >;
  725. };
  726. pinctrl_pwm2: pwm2grp {
  727. fsl,pins = <
  728. MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  729. >;
  730. };
  731. pinctrl_pwm3: pwm3grp {
  732. fsl,pins = <
  733. MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
  734. >;
  735. };
  736. pinctrl_pwm4: pwm4grp {
  737. fsl,pins = <
  738. MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
  739. >;
  740. };
  741. pinctrl_uart1: uart1grp {
  742. fsl,pins = <
  743. MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
  744. MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
  745. MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
  746. >;
  747. };
  748. pinctrl_uart2: uart2grp {
  749. fsl,pins = <
  750. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  751. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  752. >;
  753. };
  754. pinctrl_uart5: uart5grp {
  755. fsl,pins = <
  756. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  757. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  758. >;
  759. };
  760. pinctrl_usbh1: usbh1grp {
  761. fsl,pins = <
  762. MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* USBHUB_RST# */
  763. >;
  764. };
  765. pinctrl_usbotg: usbotggrp {
  766. fsl,pins = <
  767. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
  768. MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
  769. MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
  770. >;
  771. };
  772. pinctrl_usdhc2: usdhc2grp {
  773. fsl,pins = <
  774. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
  775. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
  776. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
  777. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
  778. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
  779. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
  780. MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x170f9
  781. MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x170f9
  782. MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x170f9
  783. MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x170f9
  784. >;
  785. };
  786. pinctrl_usdhc3: usdhc3grp {
  787. fsl,pins = <
  788. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  789. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  790. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  791. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  792. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  793. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  794. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
  795. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
  796. >;
  797. };
  798. pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
  799. fsl,pins = <
  800. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
  801. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
  802. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
  803. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
  804. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
  805. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
  806. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
  807. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
  808. >;
  809. };
  810. pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
  811. fsl,pins = <
  812. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
  813. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
  814. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
  815. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
  816. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
  817. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
  818. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
  819. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
  820. >;
  821. };
  822. pinctrl_wdog: wdoggrp {
  823. fsl,pins = <
  824. MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
  825. >;
  826. };
  827. };