imx6qdl-gw52xx.dtsi 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2013 Gateworks Corporation
  4. */
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include <dt-bindings/input/linux-event-codes.h>
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. / {
  9. /* these are used by bootloader for disabling nodes */
  10. aliases {
  11. led0 = &led0;
  12. led1 = &led1;
  13. led2 = &led2;
  14. mmc0 = &usdhc3;
  15. nand = &gpmi;
  16. ssi0 = &ssi1;
  17. usb0 = &usbh1;
  18. usb1 = &usbotg;
  19. };
  20. chosen {
  21. bootargs = "console=ttymxc1,115200";
  22. };
  23. backlight {
  24. compatible = "pwm-backlight";
  25. pwms = <&pwm4 0 5000000>;
  26. brightness-levels = <0 4 8 16 32 64 128 255>;
  27. default-brightness-level = <7>;
  28. };
  29. gpio-keys {
  30. compatible = "gpio-keys";
  31. #address-cells = <1>;
  32. #size-cells = <0>;
  33. user-pb {
  34. label = "user_pb";
  35. gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  36. linux,code = <BTN_0>;
  37. };
  38. user-pb1x {
  39. label = "user_pb1x";
  40. linux,code = <BTN_1>;
  41. interrupt-parent = <&gsc>;
  42. interrupts = <0>;
  43. };
  44. key-erased {
  45. label = "key-erased";
  46. linux,code = <BTN_2>;
  47. interrupt-parent = <&gsc>;
  48. interrupts = <1>;
  49. };
  50. eeprom-wp {
  51. label = "eeprom_wp";
  52. linux,code = <BTN_3>;
  53. interrupt-parent = <&gsc>;
  54. interrupts = <2>;
  55. };
  56. tamper {
  57. label = "tamper";
  58. linux,code = <BTN_4>;
  59. interrupt-parent = <&gsc>;
  60. interrupts = <5>;
  61. };
  62. switch-hold {
  63. label = "switch_hold";
  64. linux,code = <BTN_5>;
  65. interrupt-parent = <&gsc>;
  66. interrupts = <7>;
  67. };
  68. };
  69. leds {
  70. compatible = "gpio-leds";
  71. pinctrl-names = "default";
  72. pinctrl-0 = <&pinctrl_gpio_leds>;
  73. led0: user1 {
  74. label = "user1";
  75. gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  76. default-state = "on";
  77. linux,default-trigger = "heartbeat";
  78. };
  79. led1: user2 {
  80. label = "user2";
  81. gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  82. default-state = "off";
  83. };
  84. led2: user3 {
  85. label = "user3";
  86. gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  87. default-state = "off";
  88. };
  89. };
  90. memory@10000000 {
  91. device_type = "memory";
  92. reg = <0x10000000 0x20000000>;
  93. };
  94. pps {
  95. compatible = "pps-gpio";
  96. pinctrl-names = "default";
  97. pinctrl-0 = <&pinctrl_pps>;
  98. gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  99. status = "okay";
  100. };
  101. reg_1p0v: regulator-1p0v {
  102. compatible = "regulator-fixed";
  103. regulator-name = "1P0V";
  104. regulator-min-microvolt = <1000000>;
  105. regulator-max-microvolt = <1000000>;
  106. regulator-always-on;
  107. };
  108. reg_3p3v: regulator-3p3v {
  109. compatible = "regulator-fixed";
  110. regulator-name = "3P3V";
  111. regulator-min-microvolt = <3300000>;
  112. regulator-max-microvolt = <3300000>;
  113. regulator-always-on;
  114. };
  115. reg_5p0v: regulator-5p0v {
  116. compatible = "regulator-fixed";
  117. regulator-name = "5P0V";
  118. regulator-min-microvolt = <5000000>;
  119. regulator-max-microvolt = <5000000>;
  120. regulator-always-on;
  121. };
  122. reg_usb_otg_vbus: regulator-usb-otg-vbus {
  123. compatible = "regulator-fixed";
  124. regulator-name = "usb_otg_vbus";
  125. regulator-min-microvolt = <5000000>;
  126. regulator-max-microvolt = <5000000>;
  127. gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  128. enable-active-high;
  129. };
  130. sound {
  131. compatible = "fsl,imx6q-ventana-sgtl5000",
  132. "fsl,imx-audio-sgtl5000";
  133. model = "sgtl5000-audio";
  134. ssi-controller = <&ssi1>;
  135. audio-codec = <&codec>;
  136. audio-routing =
  137. "MIC_IN", "Mic Jack",
  138. "Mic Jack", "Mic Bias",
  139. "Headphone Jack", "HP_OUT";
  140. mux-int-port = <1>;
  141. mux-ext-port = <4>;
  142. };
  143. };
  144. &audmux {
  145. pinctrl-names = "default";
  146. pinctrl-0 = <&pinctrl_audmux>;
  147. status = "okay";
  148. };
  149. &can1 {
  150. pinctrl-names = "default";
  151. pinctrl-0 = <&pinctrl_flexcan1>;
  152. status = "okay";
  153. };
  154. &clks {
  155. assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
  156. <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
  157. assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
  158. <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
  159. };
  160. &ecspi3 {
  161. cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
  162. pinctrl-names = "default";
  163. pinctrl-0 = <&pinctrl_ecspi3>;
  164. status = "okay";
  165. };
  166. &fec {
  167. pinctrl-names = "default";
  168. pinctrl-0 = <&pinctrl_enet>;
  169. phy-mode = "rgmii-id";
  170. phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
  171. phy-reset-duration = <10>;
  172. phy-reset-post-delay = <100>;
  173. status = "okay";
  174. };
  175. &gpmi {
  176. pinctrl-names = "default";
  177. pinctrl-0 = <&pinctrl_gpmi_nand>;
  178. status = "okay";
  179. };
  180. &hdmi {
  181. ddc-i2c-bus = <&i2c3>;
  182. status = "okay";
  183. };
  184. &i2c1 {
  185. clock-frequency = <100000>;
  186. pinctrl-names = "default";
  187. pinctrl-0 = <&pinctrl_i2c1>;
  188. status = "okay";
  189. gsc: gsc@20 {
  190. compatible = "gw,gsc";
  191. reg = <0x20>;
  192. interrupt-parent = <&gpio1>;
  193. interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
  194. interrupt-controller;
  195. #interrupt-cells = <1>;
  196. #size-cells = <0>;
  197. adc {
  198. compatible = "gw,gsc-adc";
  199. #address-cells = <1>;
  200. #size-cells = <0>;
  201. channel@0 {
  202. gw,mode = <0>;
  203. reg = <0x00>;
  204. label = "temp";
  205. };
  206. channel@2 {
  207. gw,mode = <1>;
  208. reg = <0x02>;
  209. label = "vdd_vin";
  210. };
  211. channel@5 {
  212. gw,mode = <1>;
  213. reg = <0x05>;
  214. label = "vdd_3p3";
  215. };
  216. channel@8 {
  217. gw,mode = <1>;
  218. reg = <0x08>;
  219. label = "vdd_bat";
  220. };
  221. channel@b {
  222. gw,mode = <1>;
  223. reg = <0x0b>;
  224. label = "vdd_5p0";
  225. };
  226. channel@e {
  227. gw,mode = <1>;
  228. reg = <0xe>;
  229. label = "vdd_arm";
  230. };
  231. channel@11 {
  232. gw,mode = <1>;
  233. reg = <0x11>;
  234. label = "vdd_soc";
  235. };
  236. channel@14 {
  237. gw,mode = <1>;
  238. reg = <0x14>;
  239. label = "vdd_3p0";
  240. };
  241. channel@17 {
  242. gw,mode = <1>;
  243. reg = <0x17>;
  244. label = "vdd_1p5";
  245. };
  246. channel@1d {
  247. gw,mode = <1>;
  248. reg = <0x1d>;
  249. label = "vdd_1p8";
  250. };
  251. channel@20 {
  252. gw,mode = <1>;
  253. reg = <0x20>;
  254. label = "vdd_1p0";
  255. };
  256. channel@23 {
  257. gw,mode = <1>;
  258. reg = <0x23>;
  259. label = "vdd_2p5";
  260. };
  261. channel@29 {
  262. gw,mode = <1>;
  263. reg = <0x29>;
  264. label = "vdd_an1";
  265. };
  266. };
  267. };
  268. gsc_gpio: gpio@23 {
  269. compatible = "nxp,pca9555";
  270. reg = <0x23>;
  271. gpio-controller;
  272. #gpio-cells = <2>;
  273. interrupt-parent = <&gsc>;
  274. interrupts = <4>;
  275. };
  276. eeprom1: eeprom@50 {
  277. compatible = "atmel,24c02";
  278. reg = <0x50>;
  279. pagesize = <16>;
  280. };
  281. eeprom2: eeprom@51 {
  282. compatible = "atmel,24c02";
  283. reg = <0x51>;
  284. pagesize = <16>;
  285. };
  286. eeprom3: eeprom@52 {
  287. compatible = "atmel,24c02";
  288. reg = <0x52>;
  289. pagesize = <16>;
  290. };
  291. eeprom4: eeprom@53 {
  292. compatible = "atmel,24c02";
  293. reg = <0x53>;
  294. pagesize = <16>;
  295. };
  296. rtc: ds1672@68 {
  297. compatible = "dallas,ds1672";
  298. reg = <0x68>;
  299. };
  300. };
  301. &i2c2 {
  302. clock-frequency = <100000>;
  303. pinctrl-names = "default";
  304. pinctrl-0 = <&pinctrl_i2c2>;
  305. status = "okay";
  306. ltc3676: pmic@3c {
  307. compatible = "lltc,ltc3676";
  308. reg = <0x3c>;
  309. pinctrl-names = "default";
  310. pinctrl-0 = <&pinctrl_pmic>;
  311. interrupt-parent = <&gpio1>;
  312. interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
  313. regulators {
  314. /* VDD_SOC (1+R1/R2 = 1.635) */
  315. reg_vdd_soc: sw1 {
  316. regulator-name = "vddsoc";
  317. regulator-min-microvolt = <674400>;
  318. regulator-max-microvolt = <1308000>;
  319. lltc,fb-voltage-divider = <127000 200000>;
  320. regulator-ramp-delay = <7000>;
  321. regulator-boot-on;
  322. regulator-always-on;
  323. };
  324. /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
  325. reg_1p8v: sw2 {
  326. regulator-name = "vdd1p8";
  327. regulator-min-microvolt = <1033310>;
  328. regulator-max-microvolt = <2004000>;
  329. lltc,fb-voltage-divider = <301000 200000>;
  330. regulator-ramp-delay = <7000>;
  331. regulator-boot-on;
  332. regulator-always-on;
  333. };
  334. /* VDD_ARM (1+R1/R2 = 1.635) */
  335. reg_vdd_arm: sw3 {
  336. regulator-name = "vddarm";
  337. regulator-min-microvolt = <674400>;
  338. regulator-max-microvolt = <1308000>;
  339. lltc,fb-voltage-divider = <127000 200000>;
  340. regulator-ramp-delay = <7000>;
  341. regulator-boot-on;
  342. regulator-always-on;
  343. };
  344. /* VDD_DDR (1+R1/R2 = 2.105) */
  345. reg_vdd_ddr: sw4 {
  346. regulator-name = "vddddr";
  347. regulator-min-microvolt = <868310>;
  348. regulator-max-microvolt = <1684000>;
  349. lltc,fb-voltage-divider = <221000 200000>;
  350. regulator-ramp-delay = <7000>;
  351. regulator-boot-on;
  352. regulator-always-on;
  353. };
  354. /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
  355. reg_2p5v: ldo2 {
  356. regulator-name = "vdd2p5";
  357. regulator-min-microvolt = <2490375>;
  358. regulator-max-microvolt = <2490375>;
  359. lltc,fb-voltage-divider = <487000 200000>;
  360. regulator-boot-on;
  361. regulator-always-on;
  362. };
  363. /* VDD_AUD_1P8: Audio codec */
  364. reg_aud_1p8v: ldo3 {
  365. regulator-name = "vdd1p8a";
  366. regulator-min-microvolt = <1800000>;
  367. regulator-max-microvolt = <1800000>;
  368. regulator-boot-on;
  369. };
  370. /* VDD_HIGH (1+R1/R2 = 4.17) */
  371. reg_3p0v: ldo4 {
  372. regulator-name = "vdd3p0";
  373. regulator-min-microvolt = <3023250>;
  374. regulator-max-microvolt = <3023250>;
  375. lltc,fb-voltage-divider = <634000 200000>;
  376. regulator-boot-on;
  377. regulator-always-on;
  378. };
  379. };
  380. };
  381. };
  382. &i2c3 {
  383. clock-frequency = <100000>;
  384. pinctrl-names = "default";
  385. pinctrl-0 = <&pinctrl_i2c3>;
  386. status = "okay";
  387. codec: sgtl5000@a {
  388. compatible = "fsl,sgtl5000";
  389. reg = <0x0a>;
  390. clocks = <&clks IMX6QDL_CLK_CKO>;
  391. VDDA-supply = <&reg_1p8v>;
  392. VDDIO-supply = <&reg_3p3v>;
  393. };
  394. touchscreen: egalax_ts@4 {
  395. compatible = "eeti,egalax_ts";
  396. reg = <0x04>;
  397. interrupt-parent = <&gpio7>;
  398. interrupts = <12 2>;
  399. wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
  400. };
  401. accel@1e {
  402. compatible = "nxp,fxos8700";
  403. reg = <0x1e>;
  404. };
  405. };
  406. &ldb {
  407. status = "okay";
  408. lvds-channel@0 {
  409. fsl,data-mapping = "spwg";
  410. fsl,data-width = <18>;
  411. status = "okay";
  412. display-timings {
  413. native-mode = <&timing0>;
  414. timing0: hsd100pxn1 {
  415. clock-frequency = <65000000>;
  416. hactive = <1024>;
  417. vactive = <768>;
  418. hback-porch = <220>;
  419. hfront-porch = <40>;
  420. vback-porch = <21>;
  421. vfront-porch = <7>;
  422. hsync-len = <60>;
  423. vsync-len = <10>;
  424. };
  425. };
  426. };
  427. };
  428. &pcie {
  429. pinctrl-names = "default";
  430. pinctrl-0 = <&pinctrl_pcie>;
  431. reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
  432. status = "okay";
  433. };
  434. &pwm2 {
  435. pinctrl-names = "default";
  436. pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  437. status = "disabled";
  438. };
  439. &pwm3 {
  440. pinctrl-names = "default";
  441. pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  442. status = "disabled";
  443. };
  444. &pwm4 {
  445. #pwm-cells = <2>;
  446. pinctrl-names = "default";
  447. pinctrl-0 = <&pinctrl_pwm4>;
  448. status = "okay";
  449. };
  450. &ssi1 {
  451. status = "okay";
  452. };
  453. &uart1 {
  454. pinctrl-names = "default";
  455. pinctrl-0 = <&pinctrl_uart1>;
  456. rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
  457. status = "okay";
  458. };
  459. &uart2 {
  460. pinctrl-names = "default";
  461. pinctrl-0 = <&pinctrl_uart2>;
  462. status = "okay";
  463. };
  464. &uart5 {
  465. pinctrl-names = "default";
  466. pinctrl-0 = <&pinctrl_uart5>;
  467. status = "okay";
  468. };
  469. &usbotg {
  470. vbus-supply = <&reg_usb_otg_vbus>;
  471. pinctrl-names = "default";
  472. pinctrl-0 = <&pinctrl_usbotg>;
  473. disable-over-current;
  474. dr_mode = "otg";
  475. status = "okay";
  476. };
  477. &usbh1 {
  478. status = "okay";
  479. };
  480. &usdhc3 {
  481. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  482. pinctrl-0 = <&pinctrl_usdhc3>;
  483. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  484. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  485. cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
  486. vmmc-supply = <&reg_3p3v>;
  487. no-1-8-v; /* firmware will remove if board revision supports */
  488. status = "okay";
  489. };
  490. &wdog1 {
  491. pinctrl-names = "default";
  492. pinctrl-0 = <&pinctrl_wdog>;
  493. fsl,ext-reset-output;
  494. };
  495. &iomuxc {
  496. pinctrl_audmux: audmuxgrp {
  497. fsl,pins = <
  498. MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
  499. MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
  500. MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
  501. MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
  502. MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
  503. >;
  504. };
  505. pinctrl_ecspi3: escpi3grp {
  506. fsl,pins = <
  507. MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
  508. MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
  509. MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
  510. MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
  511. >;
  512. };
  513. pinctrl_enet: enetgrp {
  514. fsl,pins = <
  515. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  516. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  517. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  518. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  519. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  520. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  521. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  522. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  523. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  524. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  525. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  526. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  527. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  528. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  529. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  530. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  531. MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
  532. >;
  533. };
  534. pinctrl_flexcan1: flexcan1grp {
  535. fsl,pins = <
  536. MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
  537. MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
  538. MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */
  539. >;
  540. };
  541. pinctrl_gpio_leds: gpioledsgrp {
  542. fsl,pins = <
  543. MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
  544. MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
  545. MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
  546. >;
  547. };
  548. pinctrl_gpmi_nand: gpminandgrp {
  549. fsl,pins = <
  550. MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
  551. MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
  552. MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
  553. MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  554. MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
  555. MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
  556. MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
  557. MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
  558. MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
  559. MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
  560. MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
  561. MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
  562. MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
  563. MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
  564. MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
  565. >;
  566. };
  567. pinctrl_i2c1: i2c1grp {
  568. fsl,pins = <
  569. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  570. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  571. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
  572. >;
  573. };
  574. pinctrl_i2c2: i2c2grp {
  575. fsl,pins = <
  576. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  577. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  578. >;
  579. };
  580. pinctrl_i2c3: i2c3grp {
  581. fsl,pins = <
  582. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  583. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  584. >;
  585. };
  586. pinctrl_pcie: pciegrp {
  587. fsl,pins = <
  588. MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */
  589. >;
  590. };
  591. pinctrl_pmic: pmicgrp {
  592. fsl,pins = <
  593. MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
  594. >;
  595. };
  596. pinctrl_pps: ppsgrp {
  597. fsl,pins = <
  598. MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
  599. >;
  600. };
  601. pinctrl_pwm2: pwm2grp {
  602. fsl,pins = <
  603. MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  604. >;
  605. };
  606. pinctrl_pwm3: pwm3grp {
  607. fsl,pins = <
  608. MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
  609. >;
  610. };
  611. pinctrl_pwm4: pwm4grp {
  612. fsl,pins = <
  613. MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
  614. >;
  615. };
  616. pinctrl_uart1: uart1grp {
  617. fsl,pins = <
  618. MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
  619. MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
  620. MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
  621. >;
  622. };
  623. pinctrl_uart2: uart2grp {
  624. fsl,pins = <
  625. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  626. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  627. >;
  628. };
  629. pinctrl_uart5: uart5grp {
  630. fsl,pins = <
  631. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  632. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  633. >;
  634. };
  635. pinctrl_usbotg: usbotggrp {
  636. fsl,pins = <
  637. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
  638. MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
  639. >;
  640. };
  641. pinctrl_usdhc3: usdhc3grp {
  642. fsl,pins = <
  643. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  644. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  645. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  646. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  647. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  648. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  649. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
  650. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
  651. >;
  652. };
  653. pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
  654. fsl,pins = <
  655. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
  656. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
  657. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
  658. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
  659. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
  660. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
  661. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
  662. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
  663. >;
  664. };
  665. pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
  666. fsl,pins = <
  667. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
  668. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
  669. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
  670. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
  671. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
  672. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
  673. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
  674. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
  675. >;
  676. };
  677. pinctrl_wdog: wdoggrp {
  678. fsl,pins = <
  679. MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
  680. >;
  681. };
  682. };