fsl-lx2162a-qds.dts 2.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * NXP LX2162AQDS device tree source
  4. *
  5. * Copyright 2020-2021 NXP
  6. *
  7. */
  8. /dts-v1/;
  9. #include "fsl-lx2160a-qds.dtsi"
  10. / {
  11. model = "NXP Layerscape LX2162AQDS Board";
  12. compatible = "fsl,lx2162aqds", "fsl,lx2160a";
  13. aliases {
  14. spi1 = &dspi0;
  15. spi2 = &dspi1;
  16. spi3 = &dspi2;
  17. };
  18. };
  19. &usb1 {
  20. status = "disabled";
  21. };
  22. &pcie2 {
  23. status = "disabled";
  24. };
  25. &pcie5 {
  26. status = "disabled";
  27. };
  28. &pcie6 {
  29. status = "disabled";
  30. };
  31. &dspi0 {
  32. bus-num = <0>;
  33. status = "okay";
  34. dflash0: n25q128a {
  35. #address-cells = <1>;
  36. #size-cells = <1>;
  37. compatible = "spi-flash";
  38. spi-max-frequency = <3000000>;
  39. spi-cpol;
  40. spi-cpha;
  41. reg = <0>;
  42. };
  43. dflash1: sst25wf040b {
  44. #address-cells = <1>;
  45. #size-cells = <1>;
  46. compatible = "spi-flash";
  47. spi-max-frequency = <3000000>;
  48. spi-cpol;
  49. spi-cpha;
  50. reg = <1>;
  51. };
  52. dflash2: en25s64 {
  53. #address-cells = <1>;
  54. #size-cells = <1>;
  55. compatible = "spi-flash";
  56. spi-max-frequency = <3000000>;
  57. spi-cpol;
  58. spi-cpha;
  59. reg = <2>;
  60. };
  61. };
  62. &dspi1 {
  63. bus-num = <0>;
  64. status = "okay";
  65. dflash3: n25q128a {
  66. #address-cells = <1>;
  67. #size-cells = <1>;
  68. compatible = "spi-flash";
  69. spi-max-frequency = <3000000>;
  70. spi-cpol;
  71. spi-cpha;
  72. reg = <0>;
  73. };
  74. dflash4: sst25wf040b {
  75. #address-cells = <1>;
  76. #size-cells = <1>;
  77. compatible = "spi-flash";
  78. spi-max-frequency = <3000000>;
  79. spi-cpol;
  80. spi-cpha;
  81. reg = <1>;
  82. };
  83. dflash5: en25s64 {
  84. #address-cells = <1>;
  85. #size-cells = <1>;
  86. compatible = "spi-flash";
  87. spi-max-frequency = <3000000>;
  88. spi-cpol;
  89. spi-cpha;
  90. reg = <2>;
  91. };
  92. };
  93. &dspi2 {
  94. bus-num = <0>;
  95. status = "okay";
  96. dflash6: n25q128a {
  97. #address-cells = <1>;
  98. #size-cells = <1>;
  99. compatible = "spi-flash";
  100. spi-max-frequency = <3000000>;
  101. spi-cpol;
  102. spi-cpha;
  103. reg = <0>;
  104. };
  105. dflash7: sst25wf040b {
  106. #address-cells = <1>;
  107. #size-cells = <1>;
  108. compatible = "spi-flash";
  109. spi-max-frequency = <3000000>;
  110. spi-cpol;
  111. spi-cpha;
  112. reg = <1>;
  113. };
  114. dflash8: en25s64 {
  115. #address-cells = <1>;
  116. #size-cells = <1>;
  117. compatible = "spi-flash";
  118. spi-max-frequency = <3000000>;
  119. spi-cpol;
  120. spi-cpha;
  121. reg = <2>;
  122. };
  123. };
  124. &esdhc1 {
  125. mmc-hs200-1_8v;
  126. mmc-hs400-1_8v;
  127. bus-width = <8>;
  128. };