fsl-lx2162a-qds-sd1-20.dtsi 589 B

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * NXP LX2162AQDS device tree source for the SERDES block #1 - protocol 20
  4. *
  5. * Some assumptions are made:
  6. * * Mezzanine card M8 is connected to IO SLOT1
  7. * (xlaui4 for DPMAC 1)
  8. *
  9. * Copyright 2020-2021 NXP
  10. *
  11. */
  12. #include "fsl-lx2160a-qds.dtsi"
  13. &dpmac1 {
  14. status = "okay";
  15. phy-handle = <&cortina_phy1_0>;
  16. phy-connection-type = "xlaui4";
  17. };
  18. &emdio1_slot1 {
  19. cortina_phy1_0: ethernet-phy@0 {
  20. compatible = "ethernet-phy-ieee802.3-c45";
  21. reg = <0x0>;
  22. };
  23. };
  24. &esdhc1 {
  25. mmc-hs200-1_8v;
  26. mmc-hs400-1_8v;
  27. bus-width = <8>;
  28. };