Kconfig 17 KB

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  1. config ARCH_LS1012A
  2. bool
  3. select ARMV8_SET_SMPEN
  4. select ARM_ERRATA_855873 if !TFABOOT
  5. select FSL_LAYERSCAPE
  6. select FSL_LSCH2
  7. select SYS_FSL_SRDS_1
  8. select SYS_HAS_SERDES
  9. select SYS_FSL_DDR_BE
  10. select SYS_FSL_MMDC
  11. select SYS_FSL_ERRATUM_A010315
  12. select SYS_FSL_ERRATUM_A009798
  13. select SYS_FSL_ERRATUM_A008997
  14. select SYS_FSL_ERRATUM_A009007
  15. select SYS_FSL_ERRATUM_A009008
  16. select ARCH_EARLY_INIT_R
  17. select BOARD_EARLY_INIT_F
  18. select SYS_I2C_MXC
  19. select SYS_I2C_MXC_I2C1 if !DM_I2C
  20. select SYS_I2C_MXC_I2C2 if !DM_I2C
  21. imply PANIC_HANG
  22. config ARCH_LS1028A
  23. bool
  24. select ARMV8_SET_SMPEN
  25. select FSL_LAYERSCAPE
  26. select FSL_LSCH3
  27. select NXP_LSCH3_2
  28. select SYS_FSL_HAS_CCI400
  29. select SYS_FSL_SRDS_1
  30. select SYS_HAS_SERDES
  31. select SYS_FSL_DDR
  32. select SYS_FSL_DDR_LE
  33. select SYS_FSL_DDR_VER_50
  34. select SYS_FSL_HAS_DDR3
  35. select SYS_FSL_HAS_DDR4
  36. select SYS_FSL_HAS_SEC
  37. select SYS_FSL_SEC_COMPAT_5
  38. select SYS_FSL_SEC_LE
  39. select FSL_TZASC_1
  40. select ARCH_EARLY_INIT_R
  41. select BOARD_EARLY_INIT_F
  42. select SYS_I2C_MXC
  43. select SYS_FSL_ERRATUM_A008997
  44. select SYS_FSL_ERRATUM_A009007
  45. select SYS_FSL_ERRATUM_A008514 if !TFABOOT
  46. select SYS_FSL_ERRATUM_A009663 if !TFABOOT
  47. select SYS_FSL_ERRATUM_A009942 if !TFABOOT
  48. select SYS_FSL_ERRATUM_A050382
  49. select SYS_FSL_ERRATUM_A011334
  50. select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
  51. select RESV_RAM if GIC_V3_ITS
  52. imply PANIC_HANG
  53. config ARCH_LS1043A
  54. bool
  55. select ARMV8_SET_SMPEN
  56. select ARM_ERRATA_855873 if !TFABOOT
  57. select FSL_LAYERSCAPE
  58. select FSL_LSCH2
  59. select SYS_FSL_SRDS_1
  60. select SYS_HAS_SERDES
  61. select SYS_FSL_DDR
  62. select SYS_FSL_DDR_BE
  63. select SYS_FSL_DDR_VER_50
  64. select SYS_FSL_ERRATUM_A008850 if !TFABOOT
  65. select SYS_FSL_ERRATUM_A008997
  66. select SYS_FSL_ERRATUM_A009007
  67. select SYS_FSL_ERRATUM_A009008
  68. select SYS_FSL_ERRATUM_A009660 if !TFABOOT
  69. select SYS_FSL_ERRATUM_A009663 if !TFABOOT
  70. select SYS_FSL_ERRATUM_A009798
  71. select SYS_FSL_ERRATUM_A009942 if !TFABOOT
  72. select SYS_FSL_ERRATUM_A010315
  73. select SYS_FSL_ERRATUM_A010539
  74. select SYS_FSL_HAS_DDR3
  75. select SYS_FSL_HAS_DDR4
  76. select ARCH_EARLY_INIT_R
  77. select BOARD_EARLY_INIT_F
  78. select SYS_I2C_MXC
  79. select SYS_I2C_MXC_I2C1 if !DM_I2C
  80. select SYS_I2C_MXC_I2C2 if !DM_I2C
  81. select SYS_I2C_MXC_I2C3 if !DM_I2C
  82. select SYS_I2C_MXC_I2C4 if !DM_I2C
  83. imply CMD_PCI
  84. config ARCH_LS1046A
  85. bool
  86. select ARMV8_SET_SMPEN
  87. select FSL_LAYERSCAPE
  88. select FSL_LSCH2
  89. select SYS_FSL_SRDS_1
  90. select SYS_HAS_SERDES
  91. select SYS_FSL_DDR
  92. select SYS_FSL_DDR_BE
  93. select SYS_FSL_DDR_VER_50
  94. select SYS_FSL_ERRATUM_A008336 if !TFABOOT
  95. select SYS_FSL_ERRATUM_A008511 if !TFABOOT
  96. select SYS_FSL_ERRATUM_A008850 if !TFABOOT
  97. select SYS_FSL_ERRATUM_A008997
  98. select SYS_FSL_ERRATUM_A009007
  99. select SYS_FSL_ERRATUM_A009008
  100. select SYS_FSL_ERRATUM_A009798
  101. select SYS_FSL_ERRATUM_A009801
  102. select SYS_FSL_ERRATUM_A009803 if !TFABOOT
  103. select SYS_FSL_ERRATUM_A009942 if !TFABOOT
  104. select SYS_FSL_ERRATUM_A010165 if !TFABOOT
  105. select SYS_FSL_ERRATUM_A010539
  106. select SYS_FSL_HAS_DDR4
  107. select SYS_FSL_SRDS_2
  108. select ARCH_EARLY_INIT_R
  109. select BOARD_EARLY_INIT_F
  110. select SYS_I2C_MXC
  111. select SYS_I2C_MXC_I2C1 if !DM_I2C
  112. select SYS_I2C_MXC_I2C2 if !DM_I2C
  113. select SYS_I2C_MXC_I2C3 if !DM_I2C
  114. select SYS_I2C_MXC_I2C4 if !DM_I2C
  115. imply SCSI
  116. imply SCSI_AHCI
  117. config ARCH_LS1088A
  118. bool
  119. select ARMV8_SET_SMPEN
  120. select ARM_ERRATA_855873 if !TFABOOT
  121. select FSL_LAYERSCAPE
  122. select FSL_LSCH3
  123. select SYS_FSL_SRDS_1
  124. select SYS_HAS_SERDES
  125. select SYS_FSL_DDR
  126. select SYS_FSL_DDR_LE
  127. select SYS_FSL_DDR_VER_50
  128. select SYS_FSL_EC1
  129. select SYS_FSL_EC2
  130. select SYS_FSL_ERRATUM_A009803 if !TFABOOT
  131. select SYS_FSL_ERRATUM_A009942 if !TFABOOT
  132. select SYS_FSL_ERRATUM_A010165 if !TFABOOT
  133. select SYS_FSL_ERRATUM_A008511 if !TFABOOT
  134. select SYS_FSL_ERRATUM_A008850 if !TFABOOT
  135. select SYS_FSL_ERRATUM_A009007
  136. select SYS_FSL_HAS_CCI400
  137. select SYS_FSL_HAS_DDR4
  138. select SYS_FSL_HAS_RGMII
  139. select SYS_FSL_HAS_SEC
  140. select SYS_FSL_SEC_COMPAT_5
  141. select SYS_FSL_SEC_LE
  142. select SYS_FSL_SRDS_1
  143. select SYS_FSL_SRDS_2
  144. select FSL_TZASC_1
  145. select FSL_TZASC_400
  146. select FSL_TZPC_BP147
  147. select ARCH_EARLY_INIT_R
  148. select BOARD_EARLY_INIT_F
  149. select SYS_I2C_MXC
  150. select SYS_I2C_MXC_I2C1 if !TFABOOT
  151. select SYS_I2C_MXC_I2C2 if !TFABOOT
  152. select SYS_I2C_MXC_I2C3 if !TFABOOT
  153. select SYS_I2C_MXC_I2C4 if !TFABOOT
  154. select RESV_RAM if GIC_V3_ITS
  155. imply SCSI
  156. imply PANIC_HANG
  157. config ARCH_LS2080A
  158. bool
  159. select ARMV8_SET_SMPEN
  160. select ARM_ERRATA_826974
  161. select ARM_ERRATA_828024
  162. select ARM_ERRATA_829520
  163. select ARM_ERRATA_833471
  164. select FSL_LAYERSCAPE
  165. select FSL_LSCH3
  166. select SYS_FSL_SRDS_1
  167. select SYS_HAS_SERDES
  168. select SYS_FSL_DDR
  169. select SYS_FSL_DDR_LE
  170. select SYS_FSL_DDR_VER_50
  171. select SYS_FSL_HAS_CCN504
  172. select SYS_FSL_HAS_DP_DDR
  173. select SYS_FSL_HAS_SEC
  174. select SYS_FSL_HAS_DDR4
  175. select SYS_FSL_SEC_COMPAT_5
  176. select SYS_FSL_SEC_LE
  177. select SYS_FSL_SRDS_2
  178. select FSL_TZASC_1
  179. select FSL_TZASC_2
  180. select FSL_TZASC_400
  181. select FSL_TZPC_BP147
  182. select SYS_FSL_ERRATUM_A008336 if !TFABOOT
  183. select SYS_FSL_ERRATUM_A008511 if !TFABOOT
  184. select SYS_FSL_ERRATUM_A008514 if !TFABOOT
  185. select SYS_FSL_ERRATUM_A008585
  186. select SYS_FSL_ERRATUM_A008997
  187. select SYS_FSL_ERRATUM_A009007
  188. select SYS_FSL_ERRATUM_A009008
  189. select SYS_FSL_ERRATUM_A009635
  190. select SYS_FSL_ERRATUM_A009663 if !TFABOOT
  191. select SYS_FSL_ERRATUM_A009798
  192. select SYS_FSL_ERRATUM_A009801
  193. select SYS_FSL_ERRATUM_A009803 if !TFABOOT
  194. select SYS_FSL_ERRATUM_A009942 if !TFABOOT
  195. select SYS_FSL_ERRATUM_A010165 if !TFABOOT
  196. select SYS_FSL_ERRATUM_A009203
  197. select ARCH_EARLY_INIT_R
  198. select BOARD_EARLY_INIT_F
  199. select SYS_I2C_MXC
  200. select SYS_I2C_MXC_I2C1 if !TFABOOT
  201. select SYS_I2C_MXC_I2C2 if !TFABOOT
  202. select SYS_I2C_MXC_I2C3 if !TFABOOT
  203. select SYS_I2C_MXC_I2C4 if !TFABOOT
  204. select RESV_RAM if GIC_V3_ITS
  205. imply DISTRO_DEFAULTS
  206. imply PANIC_HANG
  207. config ARCH_LX2162A
  208. bool
  209. select ARMV8_SET_SMPEN
  210. select FSL_LSCH3
  211. select NXP_LSCH3_2
  212. select SYS_HAS_SERDES
  213. select SYS_FSL_SRDS_1
  214. select SYS_FSL_SRDS_2
  215. select SYS_FSL_DDR
  216. select SYS_FSL_DDR_LE
  217. select SYS_FSL_DDR_VER_50
  218. select SYS_FSL_EC1
  219. select SYS_FSL_EC2
  220. select SYS_FSL_ERRATUM_A050204
  221. select SYS_FSL_ERRATUM_A011334
  222. select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
  223. select SYS_FSL_HAS_RGMII
  224. select SYS_FSL_HAS_SEC
  225. select SYS_FSL_HAS_CCN508
  226. select SYS_FSL_HAS_DDR4
  227. select SYS_FSL_SEC_COMPAT_5
  228. select SYS_FSL_SEC_LE
  229. select ARCH_EARLY_INIT_R
  230. select BOARD_EARLY_INIT_F
  231. select SYS_I2C_MXC
  232. select RESV_RAM if GIC_V3_ITS
  233. imply DISTRO_DEFAULTS
  234. imply PANIC_HANG
  235. imply SCSI
  236. imply SCSI_AHCI
  237. config ARCH_LX2160A
  238. bool
  239. select ARMV8_SET_SMPEN
  240. select FSL_LSCH3
  241. select NXP_LSCH3_2
  242. select SYS_HAS_SERDES
  243. select SYS_FSL_SRDS_1
  244. select SYS_FSL_SRDS_2
  245. select SYS_NXP_SRDS_3
  246. select SYS_FSL_DDR
  247. select SYS_FSL_DDR_LE
  248. select SYS_FSL_DDR_VER_50
  249. select SYS_FSL_EC1
  250. select SYS_FSL_EC2
  251. select SYS_FSL_ERRATUM_A050204
  252. select SYS_FSL_ERRATUM_A011334
  253. select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
  254. select SYS_FSL_HAS_RGMII
  255. select SYS_FSL_HAS_SEC
  256. select SYS_FSL_HAS_CCN508
  257. select SYS_FSL_HAS_DDR4
  258. select SYS_FSL_SEC_COMPAT_5
  259. select SYS_FSL_SEC_LE
  260. select ARCH_EARLY_INIT_R
  261. select BOARD_EARLY_INIT_F
  262. select SYS_I2C_MXC
  263. select RESV_RAM if GIC_V3_ITS
  264. imply DISTRO_DEFAULTS
  265. imply PANIC_HANG
  266. imply SCSI
  267. imply SCSI_AHCI
  268. config FSL_LSCH2
  269. bool
  270. select SYS_FSL_HAS_CCI400
  271. select SYS_FSL_HAS_SEC
  272. select SYS_FSL_SEC_COMPAT_5
  273. select SYS_FSL_SEC_BE
  274. config FSL_LSCH3
  275. select ARCH_MISC_INIT
  276. bool
  277. config NXP_LSCH3_2
  278. bool
  279. menu "Layerscape architecture"
  280. depends on FSL_LSCH2 || FSL_LSCH3
  281. config FSL_LAYERSCAPE
  282. bool
  283. config HAS_FEATURE_GIC64K_ALIGN
  284. bool
  285. default y if ARCH_LS1043A
  286. config HAS_FEATURE_ENHANCED_MSI
  287. bool
  288. default y if ARCH_LS1043A
  289. menu "Layerscape PPA"
  290. config FSL_LS_PPA
  291. bool "FSL Layerscape PPA firmware support"
  292. depends on !ARMV8_PSCI
  293. select ARMV8_SEC_FIRMWARE_SUPPORT
  294. select SEC_FIRMWARE_ARMV8_PSCI
  295. select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
  296. help
  297. The FSL Primary Protected Application (PPA) is a software component
  298. which is loaded during boot stage, and then remains resident in RAM
  299. and runs in the TrustZone after boot.
  300. Say y to enable it.
  301. config SPL_FSL_LS_PPA
  302. bool "FSL Layerscape PPA firmware support for SPL build"
  303. depends on !ARMV8_PSCI
  304. select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
  305. select SEC_FIRMWARE_ARMV8_PSCI
  306. select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
  307. help
  308. The FSL Primary Protected Application (PPA) is a software component
  309. which is loaded during boot stage, and then remains resident in RAM
  310. and runs in the TrustZone after boot. This is to load PPA during SPL
  311. stage instead of the RAM version of U-Boot. Once PPA is initialized,
  312. the rest of U-Boot (including RAM version) runs at EL2.
  313. choice
  314. prompt "FSL Layerscape PPA firmware loading-media select"
  315. depends on FSL_LS_PPA
  316. default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
  317. default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
  318. default SYS_LS_PPA_FW_IN_XIP
  319. config SYS_LS_PPA_FW_IN_XIP
  320. bool "XIP"
  321. help
  322. Say Y here if the PPA firmware locate at XIP flash, such
  323. as NOR or QSPI flash.
  324. config SYS_LS_PPA_FW_IN_MMC
  325. bool "eMMC or SD Card"
  326. help
  327. Say Y here if the PPA firmware locate at eMMC/SD card.
  328. config SYS_LS_PPA_FW_IN_NAND
  329. bool "NAND"
  330. help
  331. Say Y here if the PPA firmware locate at NAND flash.
  332. endchoice
  333. config LS_PPA_ESBC_HDR_SIZE
  334. hex "Length of PPA ESBC header"
  335. depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
  336. default 0x2000
  337. help
  338. Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
  339. NAND to memory to validate PPA image.
  340. endmenu
  341. config SYS_FSL_ERRATUM_A008997
  342. bool "Workaround for USB PHY erratum A008997"
  343. config SYS_FSL_ERRATUM_A009007
  344. bool
  345. help
  346. Workaround for USB PHY erratum A009007
  347. config SYS_FSL_ERRATUM_A009008
  348. bool "Workaround for USB PHY erratum A009008"
  349. config SYS_FSL_ERRATUM_A009798
  350. bool "Workaround for USB PHY erratum A009798"
  351. config SYS_FSL_ERRATUM_A050204
  352. bool "Workaround for USB PHY erratum A050204"
  353. help
  354. USB3.0 Receiver needs to enable fixed equalization
  355. for each of PHY instances in an SOC. This is similar
  356. to erratum A-009007, but this one is for LX2160A and LX2162A,
  357. and the register value is different.
  358. config SYS_FSL_ERRATUM_A010315
  359. bool "Workaround for PCIe erratum A010315"
  360. config SYS_FSL_ERRATUM_A010539
  361. bool "Workaround for PIN MUX erratum A010539"
  362. config MAX_CPUS
  363. int "Maximum number of CPUs permitted for Layerscape"
  364. default 2 if ARCH_LS1028A
  365. default 4 if ARCH_LS1043A
  366. default 4 if ARCH_LS1046A
  367. default 16 if ARCH_LS2080A
  368. default 8 if ARCH_LS1088A
  369. default 16 if ARCH_LX2160A
  370. default 16 if ARCH_LX2162A
  371. default 1
  372. help
  373. Set this number to the maximum number of possible CPUs in the SoC.
  374. SoCs may have multiple clusters with each cluster may have multiple
  375. ports. If some ports are reserved but higher ports are used for
  376. cores, count the reserved ports. This will allocate enough memory
  377. in spin table to properly handle all cores.
  378. config EMC2305
  379. bool "Fan controller"
  380. help
  381. Enable the EMC2305 fan controller for configuration of fan
  382. speed.
  383. config NXP_ESBC
  384. bool "NXP_ESBC"
  385. help
  386. Enable Freescale Secure Boot feature
  387. config QSPI_AHB_INIT
  388. bool "Init the QSPI AHB bus"
  389. help
  390. The default setting for QSPI AHB bus just support 3bytes addressing.
  391. But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
  392. bus for those flashes to support the full QSPI flash size.
  393. config FSPI_AHB_EN_4BYTE
  394. bool "Enable 4-byte Fast Read command for AHB mode"
  395. default n
  396. help
  397. The default setting for FlexSPI AHB bus just supports 3-byte addressing.
  398. But some FlexSPI flash sizes are up to 64MBytes.
  399. This flag enables fast read command for AHB mode and modifies required
  400. LUT to support full FlexSPI flash.
  401. config SYS_CCI400_OFFSET
  402. hex "Offset for CCI400 base"
  403. depends on SYS_FSL_HAS_CCI400
  404. default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
  405. default 0x180000 if FSL_LSCH2
  406. help
  407. Offset for CCI400 base
  408. CCI400 base addr = CCSRBAR + CCI400_OFFSET
  409. config SYS_FSL_IFC_BANK_COUNT
  410. int "Maximum banks of Integrated flash controller"
  411. depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
  412. default 4 if ARCH_LS1043A
  413. default 4 if ARCH_LS1046A
  414. default 8 if ARCH_LS2080A || ARCH_LS1088A
  415. config SYS_FSL_HAS_CCI400
  416. bool
  417. config SYS_FSL_HAS_CCN504
  418. bool
  419. config SYS_FSL_HAS_CCN508
  420. bool
  421. config SYS_FSL_HAS_DP_DDR
  422. bool
  423. config SYS_FSL_SRDS_1
  424. bool
  425. config SYS_FSL_SRDS_2
  426. bool
  427. config SYS_NXP_SRDS_3
  428. bool
  429. config SYS_HAS_SERDES
  430. bool
  431. config FSL_TZASC_1
  432. bool
  433. config FSL_TZASC_2
  434. bool
  435. config FSL_TZASC_400
  436. bool
  437. config FSL_TZPC_BP147
  438. bool
  439. endmenu
  440. menu "Layerscape clock tree configuration"
  441. depends on FSL_LSCH2 || FSL_LSCH3
  442. config SYS_FSL_CLK
  443. bool "Enable clock tree initialization"
  444. default y
  445. config CLUSTER_CLK_FREQ
  446. int "Reference clock of core cluster"
  447. depends on ARCH_LS1012A
  448. default 100000000
  449. help
  450. This number is the reference clock frequency of core PLL.
  451. For most platforms, the core PLL and Platform PLL have the same
  452. reference clock, but for some platforms, LS1012A for instance,
  453. they are provided sepatately.
  454. config SYS_FSL_PCLK_DIV
  455. int "Platform clock divider"
  456. default 1 if ARCH_LS1028A
  457. default 1 if ARCH_LS1043A
  458. default 1 if ARCH_LS1046A
  459. default 1 if ARCH_LS1088A
  460. default 2
  461. help
  462. This is the divider that is used to derive Platform clock from
  463. Platform PLL, in another word:
  464. Platform_clk = Platform_PLL_freq / this_divider
  465. config SYS_FSL_DSPI_CLK_DIV
  466. int "DSPI clock divider"
  467. default 1 if ARCH_LS1043A
  468. default 2
  469. help
  470. This is the divider that is used to derive DSPI clock from Platform
  471. clock, in another word DSPI_clk = Platform_clk / this_divider.
  472. config SYS_FSL_DUART_CLK_DIV
  473. int "DUART clock divider"
  474. default 1 if ARCH_LS1043A
  475. default 4 if ARCH_LX2160A
  476. default 4 if ARCH_LX2162A
  477. default 2
  478. help
  479. This is the divider that is used to derive DUART clock from Platform
  480. clock, in another word DUART_clk = Platform_clk / this_divider.
  481. config SYS_FSL_I2C_CLK_DIV
  482. int "I2C clock divider"
  483. default 1 if ARCH_LS1043A
  484. default 4 if ARCH_LS1012A
  485. default 4 if ARCH_LS1028A
  486. default 8 if ARCH_LX2160A
  487. default 8 if ARCH_LX2162A
  488. default 8 if ARCH_LS1088A
  489. default 2
  490. help
  491. This is the divider that is used to derive I2C clock from Platform
  492. clock, in another word I2C_clk = Platform_clk / this_divider.
  493. config SYS_FSL_IFC_CLK_DIV
  494. int "IFC clock divider"
  495. default 1 if ARCH_LS1043A
  496. default 4 if ARCH_LS1012A
  497. default 4 if ARCH_LS1028A
  498. default 8 if ARCH_LX2160A
  499. default 8 if ARCH_LX2162A
  500. default 8 if ARCH_LS1088A
  501. default 2
  502. help
  503. This is the divider that is used to derive IFC clock from Platform
  504. clock, in another word IFC_clk = Platform_clk / this_divider.
  505. config SYS_FSL_LPUART_CLK_DIV
  506. int "LPUART clock divider"
  507. default 1 if ARCH_LS1043A
  508. default 2
  509. help
  510. This is the divider that is used to derive LPUART clock from Platform
  511. clock, in another word LPUART_clk = Platform_clk / this_divider.
  512. config SYS_FSL_SDHC_CLK_DIV
  513. int "SDHC clock divider"
  514. default 1 if ARCH_LS1043A
  515. default 1 if ARCH_LS1012A
  516. default 2
  517. help
  518. This is the divider that is used to derive SDHC clock from Platform
  519. clock, in another word SDHC_clk = Platform_clk / this_divider.
  520. config SYS_FSL_QMAN_CLK_DIV
  521. int "QMAN clock divider"
  522. default 1 if ARCH_LS1043A
  523. default 2
  524. help
  525. This is the divider that is used to derive QMAN clock from Platform
  526. clock, in another word QMAN_clk = Platform_clk / this_divider.
  527. endmenu
  528. config RESV_RAM
  529. bool
  530. help
  531. Reserve memory from the top, tracked by gd->arch.resv_ram. This
  532. reserved RAM can be used by special driver that resides in memory
  533. after U-Boot exits. It's up to implementation to allocate and allow
  534. access to this reserved memory. For example, the reserved RAM can
  535. be at the high end of physical memory. The reserve RAM may be
  536. excluded from memory bank(s) passed to OS, or marked as reserved.
  537. config SYS_FSL_EC1
  538. bool
  539. help
  540. Ethernet controller 1, this is connected to
  541. MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs
  542. Provides DPAA2 capabilities
  543. config SYS_FSL_EC2
  544. bool
  545. help
  546. Ethernet controller 2, this is connected to
  547. MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs
  548. Provides DPAA2 capabilities
  549. config SYS_FSL_ERRATUM_A008336
  550. bool
  551. config SYS_FSL_ERRATUM_A008514
  552. bool
  553. config SYS_FSL_ERRATUM_A008585
  554. bool
  555. config SYS_FSL_ERRATUM_A008850
  556. bool
  557. config SYS_FSL_ERRATUM_A009203
  558. bool
  559. config SYS_FSL_ERRATUM_A009635
  560. bool
  561. config SYS_FSL_ERRATUM_A009660
  562. bool
  563. config SYS_FSL_ERRATUM_A050382
  564. bool
  565. config SYS_FSL_HAS_RGMII
  566. bool
  567. depends on SYS_FSL_EC1 || SYS_FSL_EC2
  568. config SPL_LDSCRIPT
  569. default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
  570. config HAS_FSL_XHCI_USB
  571. bool
  572. default y if ARCH_LS1043A || ARCH_LS1046A
  573. help
  574. For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
  575. pins, select it when the pins are assigned to USB.
  576. config SYS_FSL_BOOTROM_BASE
  577. hex
  578. depends on FSL_LSCH2
  579. default 0
  580. config SYS_FSL_BOOTROM_SIZE
  581. hex
  582. depends on FSL_LSCH2
  583. default 0x1000000