imx-regs.h 9.4 KB

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  1. /*
  2. * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  3. *
  4. * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. */
  24. #ifndef __ASM_ARCH_MX35_H
  25. #define __ASM_ARCH_MX35_H
  26. #define ARCH_MXC
  27. /*
  28. * IRAM
  29. */
  30. #define IRAM_BASE_ADDR 0x10000000 /* internal ram */
  31. #define IRAM_SIZE 0x00020000 /* 128 KB */
  32. #define LOW_LEVEL_SRAM_STACK 0x1001E000
  33. /*
  34. * AIPS 1
  35. */
  36. #define AIPS1_BASE_ADDR 0x43F00000
  37. #define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
  38. #define MAX_BASE_ADDR 0x43F04000
  39. #define EVTMON_BASE_ADDR 0x43F08000
  40. #define CLKCTL_BASE_ADDR 0x43F0C000
  41. #define I2C1_BASE_ADDR 0x43F80000
  42. #define I2C3_BASE_ADDR 0x43F84000
  43. #define ATA_BASE_ADDR 0x43F8C000
  44. #define UART1_BASE 0x43F90000
  45. #define UART2_BASE 0x43F94000
  46. #define I2C2_BASE_ADDR 0x43F98000
  47. #define CSPI1_BASE_ADDR 0x43FA4000
  48. #define IOMUXC_BASE_ADDR 0x43FAC000
  49. /*
  50. * SPBA
  51. */
  52. #define SPBA_BASE_ADDR 0x50000000
  53. #define UART3_BASE 0x5000C000
  54. #define CSPI2_BASE_ADDR 0x50010000
  55. #define ATA_DMA_BASE_ADDR 0x50020000
  56. #define FEC_BASE_ADDR 0x50038000
  57. #define SPBA_CTRL_BASE_ADDR 0x5003C000
  58. /*
  59. * AIPS 2
  60. */
  61. #define AIPS2_BASE_ADDR 0x53F00000
  62. #define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
  63. #define CCM_BASE_ADDR 0x53F80000
  64. #define GPT1_BASE_ADDR 0x53F90000
  65. #define EPIT1_BASE_ADDR 0x53F94000
  66. #define EPIT2_BASE_ADDR 0x53F98000
  67. #define GPIO3_BASE_ADDR 0x53FA4000
  68. #define MMC_SDHC1_BASE_ADDR 0x53FB4000
  69. #define MMC_SDHC2_BASE_ADDR 0x53FB8000
  70. #define MMC_SDHC3_BASE_ADDR 0x53FBC000
  71. #define IPU_CTRL_BASE_ADDR 0x53FC0000
  72. #define GPIO1_BASE_ADDR 0x53FCC000
  73. #define GPIO2_BASE_ADDR 0x53FD0000
  74. #define SDMA_BASE_ADDR 0x53FD4000
  75. #define RTC_BASE_ADDR 0x53FD8000
  76. #define WDOG1_BASE_ADDR 0x53FDC000
  77. #define PWM_BASE_ADDR 0x53FE0000
  78. #define RTIC_BASE_ADDR 0x53FEC000
  79. #define IIM_BASE_ADDR 0x53FF0000
  80. #define IMX_USB_BASE 0x53FF4000
  81. #define IMX_USB_PORT_OFFSET 0x400
  82. #define IMX_CCM_BASE CCM_BASE_ADDR
  83. /*
  84. * ROMPATCH and AVIC
  85. */
  86. #define ROMPATCH_BASE_ADDR 0x60000000
  87. #define AVIC_BASE_ADDR 0x68000000
  88. /*
  89. * NAND, SDRAM, WEIM, M3IF, EMI controllers
  90. */
  91. #define EXT_MEM_CTRL_BASE 0xB8000000
  92. #define ESDCTL_BASE_ADDR 0xB8001000
  93. #define WEIM_BASE_ADDR 0xB8002000
  94. #define WEIM_CTRL_CS0 WEIM_BASE_ADDR
  95. #define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10)
  96. #define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20)
  97. #define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30)
  98. #define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40)
  99. #define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50)
  100. #define M3IF_BASE_ADDR 0xB8003000
  101. #define EMI_BASE_ADDR 0xB8004000
  102. #define NFC_BASE_ADDR 0xBB000000
  103. /*
  104. * Memory regions and CS
  105. */
  106. #define IPU_MEM_BASE_ADDR 0x70000000
  107. #define CSD0_BASE_ADDR 0x80000000
  108. #define CSD1_BASE_ADDR 0x90000000
  109. #define CS0_BASE_ADDR 0xA0000000
  110. #define CS1_BASE_ADDR 0xA8000000
  111. #define CS2_BASE_ADDR 0xB0000000
  112. #define CS3_BASE_ADDR 0xB2000000
  113. #define CS4_BASE_ADDR 0xB4000000
  114. #define CS5_BASE_ADDR 0xB6000000
  115. /*
  116. * IRQ Controller Register Definitions.
  117. */
  118. #define AVIC_NIMASK 0x04
  119. #define AVIC_INTTYPEH 0x18
  120. #define AVIC_INTTYPEL 0x1C
  121. /* L210 */
  122. #define L2CC_BASE_ADDR 0x30000000
  123. #define L2_CACHE_LINE_SIZE 32
  124. #define L2_CACHE_CTL_REG 0x100
  125. #define L2_CACHE_AUX_CTL_REG 0x104
  126. #define L2_CACHE_SYNC_REG 0x730
  127. #define L2_CACHE_INV_LINE_REG 0x770
  128. #define L2_CACHE_INV_WAY_REG 0x77C
  129. #define L2_CACHE_CLEAN_LINE_REG 0x7B0
  130. #define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0
  131. #define L2_CACHE_DBG_CTL_REG 0xF40
  132. #define CLKMODE_AUTO 0
  133. #define CLKMODE_CONSUMER 1
  134. #define PLL_PD(x) (((x) & 0xf) << 26)
  135. #define PLL_MFD(x) (((x) & 0x3ff) << 16)
  136. #define PLL_MFI(x) (((x) & 0xf) << 10)
  137. #define PLL_MFN(x) (((x) & 0x3ff) << 0)
  138. #define _PLL_BRM(x) ((x) << 31)
  139. #define _PLL_PD(x) (((x) - 1) << 26)
  140. #define _PLL_MFD(x) (((x) - 1) << 16)
  141. #define _PLL_MFI(x) ((x) << 10)
  142. #define _PLL_MFN(x) (x)
  143. #define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \
  144. (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\
  145. _PLL_MFN(mfn))
  146. #define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1)
  147. #define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
  148. #define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
  149. #define CSCR_U(x) (WEIM_CTRL_CS#x + 0)
  150. #define CSCR_L(x) (WEIM_CTRL_CS#x + 4)
  151. #define CSCR_A(x) (WEIM_CTRL_CS#x + 8)
  152. #define IIM_SREV 0x24
  153. #define ROMPATCH_REV 0x40
  154. #define IPU_CONF IPU_CTRL_BASE_ADDR
  155. #define IPU_CONF_PXL_ENDIAN (1<<8)
  156. #define IPU_CONF_DU_EN (1<<7)
  157. #define IPU_CONF_DI_EN (1<<6)
  158. #define IPU_CONF_ADC_EN (1<<5)
  159. #define IPU_CONF_SDC_EN (1<<4)
  160. #define IPU_CONF_PF_EN (1<<3)
  161. #define IPU_CONF_ROT_EN (1<<2)
  162. #define IPU_CONF_IC_EN (1<<1)
  163. #define IPU_CONF_CSI_EN (1<<0)
  164. /*
  165. * CSPI register definitions
  166. */
  167. #define MXC_CSPI
  168. #define MXC_CSPICTRL_EN (1 << 0)
  169. #define MXC_CSPICTRL_MODE (1 << 1)
  170. #define MXC_CSPICTRL_XCH (1 << 2)
  171. #define MXC_CSPICTRL_SMC (1 << 3)
  172. #define MXC_CSPICTRL_POL (1 << 4)
  173. #define MXC_CSPICTRL_PHA (1 << 5)
  174. #define MXC_CSPICTRL_SSCTL (1 << 6)
  175. #define MXC_CSPICTRL_SSPOL (1 << 7)
  176. #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
  177. #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
  178. #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
  179. #define MXC_CSPICTRL_TC (1 << 7)
  180. #define MXC_CSPICTRL_RXOVF (1 << 6)
  181. #define MXC_CSPICTRL_MAXBITS 0xfff
  182. #define MXC_CSPIPERIOD_32KHZ (1 << 15)
  183. #define MAX_SPI_BYTES 4
  184. #define MXC_SPI_BASE_ADDRESSES \
  185. 0x43fa4000, \
  186. 0x50010000,
  187. #define GPIO_PORT_NUM 3
  188. #define GPIO_NUM_PIN 32
  189. #define CHIP_REV_1_0 0x10
  190. #define CHIP_REV_2_0 0x20
  191. #define BOARD_REV_1_0 0x0
  192. #define BOARD_REV_2_0 0x1
  193. #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  194. #include <asm/types.h>
  195. /* Clock Control Module (CCM) registers */
  196. struct ccm_regs {
  197. u32 ccmr; /* Control */
  198. u32 pdr0; /* Post divider 0 */
  199. u32 pdr1; /* Post divider 1 */
  200. u32 pdr2; /* Post divider 2 */
  201. u32 pdr3; /* Post divider 3 */
  202. u32 pdr4; /* Post divider 4 */
  203. u32 rcsr; /* CCM Status */
  204. u32 mpctl; /* Core PLL Control */
  205. u32 ppctl; /* Peripheral PLL Control */
  206. u32 acmr; /* Audio clock mux */
  207. u32 cosr; /* Clock out source */
  208. u32 cgr0; /* Clock Gating Control 0 */
  209. u32 cgr1; /* Clock Gating Control 1 */
  210. u32 cgr2; /* Clock Gating Control 2 */
  211. u32 cgr3; /* Clock Gating Control 3 */
  212. u32 reserved;
  213. u32 dcvr0; /* DPTC Comparator 0 */
  214. u32 dcvr1; /* DPTC Comparator 0 */
  215. u32 dcvr2; /* DPTC Comparator 0 */
  216. u32 dcvr3; /* DPTC Comparator 0 */
  217. u32 ltr0; /* Load Tracking 0 */
  218. u32 ltr1; /* Load Tracking 1 */
  219. u32 ltr2; /* Load Tracking 2 */
  220. u32 ltr3; /* Load Tracking 3 */
  221. u32 ltbr0; /* Load Tracking Buffer 0 */
  222. };
  223. /* IIM control registers */
  224. struct iim_regs {
  225. u32 iim_stat;
  226. u32 iim_statm;
  227. u32 iim_err;
  228. u32 iim_emask;
  229. u32 iim_fctl;
  230. u32 iim_ua;
  231. u32 iim_la;
  232. u32 iim_sdat;
  233. u32 iim_prev;
  234. u32 iim_srev;
  235. u32 iim_prg_p;
  236. u32 iim_scs0;
  237. u32 iim_scs1;
  238. u32 iim_scs2;
  239. u32 iim_scs3;
  240. u32 res1[0x1f1];
  241. struct fuse_bank {
  242. u32 fuse_regs[0x20];
  243. u32 fuse_rsvd[0xe0];
  244. } bank[3];
  245. };
  246. struct fuse_bank0_regs {
  247. u32 fuse0_7[8];
  248. u32 uid[8];
  249. u32 fuse16_31[0x10];
  250. };
  251. struct fuse_bank1_regs {
  252. u32 fuse0_21[0x16];
  253. u32 usr;
  254. u32 fuse23_31[9];
  255. };
  256. /* General Purpose Timer (GPT) registers */
  257. struct gpt_regs {
  258. u32 ctrl; /* control */
  259. u32 pre; /* prescaler */
  260. u32 stat; /* status */
  261. u32 intr; /* interrupt */
  262. u32 cmp[3]; /* output compare 1-3 */
  263. u32 capt[2]; /* input capture 1-2 */
  264. u32 counter; /* counter */
  265. };
  266. /* CSPI registers */
  267. struct cspi_regs {
  268. u32 rxdata;
  269. u32 txdata;
  270. u32 ctrl;
  271. u32 intr;
  272. u32 dma;
  273. u32 stat;
  274. u32 period;
  275. u32 test;
  276. };
  277. struct esdc_regs {
  278. u32 esdctl0;
  279. u32 esdcfg0;
  280. u32 esdctl1;
  281. u32 esdcfg1;
  282. u32 esdmisc;
  283. u32 reserved[4];
  284. u32 esdcdly[5];
  285. u32 esdcdlyl;
  286. };
  287. #define ESDC_MISC_RST (1 << 1)
  288. #define ESDC_MISC_MDDR_EN (1 << 2)
  289. #define ESDC_MISC_MDDR_DL_RST (1 << 3)
  290. #define ESDC_MISC_DDR_EN (1 << 8)
  291. #define ESDC_MISC_DDR2_EN (1 << 9)
  292. /* Multi-Layer AHB Crossbar Switch (MAX) registers */
  293. struct max_regs {
  294. u32 mpr0;
  295. u32 pad00[3];
  296. u32 sgpcr0;
  297. u32 pad01[59];
  298. u32 mpr1;
  299. u32 pad02[3];
  300. u32 sgpcr1;
  301. u32 pad03[59];
  302. u32 mpr2;
  303. u32 pad04[3];
  304. u32 sgpcr2;
  305. u32 pad05[59];
  306. u32 mpr3;
  307. u32 pad06[3];
  308. u32 sgpcr3;
  309. u32 pad07[59];
  310. u32 mpr4;
  311. u32 pad08[3];
  312. u32 sgpcr4;
  313. u32 pad09[251];
  314. u32 mgpcr0;
  315. u32 pad10[63];
  316. u32 mgpcr1;
  317. u32 pad11[63];
  318. u32 mgpcr2;
  319. u32 pad12[63];
  320. u32 mgpcr3;
  321. u32 pad13[63];
  322. u32 mgpcr4;
  323. u32 pad14[63];
  324. u32 mgpcr5;
  325. };
  326. /* AHB <-> IP-Bus Interface (AIPS) */
  327. struct aips_regs {
  328. u32 mpr_0_7;
  329. u32 mpr_8_15;
  330. u32 pad0[6];
  331. u32 pacr_0_7;
  332. u32 pacr_8_15;
  333. u32 pacr_16_23;
  334. u32 pacr_24_31;
  335. u32 pad1[4];
  336. u32 opacr_0_7;
  337. u32 opacr_8_15;
  338. u32 opacr_16_23;
  339. u32 opacr_24_31;
  340. u32 opacr_32_39;
  341. };
  342. /*
  343. * NFMS bit in RCSR register for pagesize of nandflash
  344. */
  345. #define NFMS_BIT 8
  346. #define NFMS_NF_DWIDTH 14
  347. #define NFMS_NF_PG_SZ 8
  348. #define CCM_RCSR_NF_16BIT_SEL (1 << 14)
  349. #endif
  350. #endif /* __ASM_ARCH_MX35_H */