phycore_imx8mp.h 3.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later
  2. *
  3. * Copyright (C) 2020 PHYTEC Messtechnik GmbH
  4. * Author: Teresa Remmet <t.remmet@phytec.de>
  5. */
  6. #ifndef __PHYCORE_IMX8MP_H
  7. #define __PHYCORE_IMX8MP_H
  8. #include <linux/sizes.h>
  9. #include <asm/arch/imx-regs.h>
  10. #define CONFIG_SYS_BOOTM_LEN SZ_64M
  11. #define CONFIG_SPL_MAX_SIZE (152 * SZ_1K)
  12. #define CONFIG_SYS_MONITOR_LEN SZ_512K
  13. #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
  14. #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
  15. #define CONFIG_SYS_UBOOT_BASE \
  16. (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
  17. #ifdef CONFIG_SPL_BUILD
  18. #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
  19. #define CONFIG_SPL_STACK 0x960000
  20. #define CONFIG_SPL_BSS_START_ADDR 0x98FC00
  21. #define CONFIG_SPL_BSS_MAX_SIZE SZ_1K
  22. #define CONFIG_SYS_SPL_MALLOC_START 0x42200000
  23. #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
  24. #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
  25. #define CONFIG_POWER
  26. #define CONFIG_POWER_I2C
  27. #define CONFIG_POWER_PCA9450
  28. #define CONFIG_SYS_I2C_LEGACY
  29. #endif
  30. #define CONFIG_EXTRA_ENV_SETTINGS \
  31. "image=Image\0" \
  32. "console=ttymxc0,115200\0" \
  33. "fdt_addr=0x48000000\0" \
  34. "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
  35. "ip_dyn=yes\0" \
  36. "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
  37. "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
  38. "mmcroot=2\0" \
  39. "mmcautodetect=yes\0" \
  40. "mmcargs=setenv bootargs console=${console} " \
  41. "root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \
  42. "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
  43. "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
  44. "mmcboot=echo Booting from mmc ...; " \
  45. "run mmcargs; " \
  46. "if run loadfdt; then " \
  47. "booti ${loadaddr} - ${fdt_addr}; " \
  48. "else " \
  49. "echo WARN: Cannot load the DT; " \
  50. "fi;\0 " \
  51. "nfsroot=/nfs\0" \
  52. "netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \
  53. "nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
  54. "netboot=echo Booting from net ...; " \
  55. "run netargs; " \
  56. "if test ${ip_dyn} = yes; then " \
  57. "setenv get_cmd dhcp; " \
  58. "else " \
  59. "setenv get_cmd tftp; " \
  60. "fi; " \
  61. "${get_cmd} ${loadaddr} ${image}; " \
  62. "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
  63. "booti ${loadaddr} - ${fdt_addr}; " \
  64. "else " \
  65. "echo WARN: Cannot load the DT; " \
  66. "fi;\0" \
  67. #define CONFIG_BOOTCOMMAND \
  68. "mmc dev ${mmcdev}; if mmc rescan; then " \
  69. "if run loadimage; then " \
  70. "run mmcboot; " \
  71. "else run netboot; " \
  72. "fi; " \
  73. "fi;"
  74. /* Link Definitions */
  75. #define CONFIG_LOADADDR 0x40480000
  76. #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  77. #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
  78. #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
  79. #define CONFIG_SYS_INIT_SP_OFFSET \
  80. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  81. #define CONFIG_SYS_INIT_SP_ADDR \
  82. (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  83. #define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */
  84. /* Size of malloc() pool */
  85. #define CONFIG_SYS_MALLOC_LEN SZ_32M
  86. #define CONFIG_SYS_SDRAM_BASE 0x40000000
  87. #define PHYS_SDRAM 0x40000000
  88. #define PHYS_SDRAM_SIZE 0x80000000
  89. /* UART */
  90. #define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
  91. /* Monitor Command Prompt */
  92. #define CONFIG_SYS_CBSIZE SZ_2K
  93. #define CONFIG_SYS_MAXARGS 64
  94. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  95. /* USDHC */
  96. #define CONFIG_FSL_USDHC
  97. #define CONFIG_SYS_FSL_USDHC_NUM 2
  98. #define CONFIG_SYS_FSL_ESDHC_ADDR 0
  99. #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
  100. /* I2C */
  101. #define CONFIG_SYS_I2C_SPEED 100000
  102. #endif /* __PHYCORE_IMX8MP_H */