ls1043a_common.h 10 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2015 Freescale Semiconductor
  4. * Copyright 2019-2021 NXP
  5. */
  6. #ifndef __LS1043A_COMMON_H
  7. #define __LS1043A_COMMON_H
  8. /* SPL build */
  9. #ifdef CONFIG_SPL_BUILD
  10. #define SPL_NO_FMAN
  11. #define SPL_NO_DSPI
  12. #define SPL_NO_PCIE
  13. #define SPL_NO_ENV
  14. #define SPL_NO_MISC
  15. #define SPL_NO_USB
  16. #define SPL_NO_SATA
  17. #define SPL_NO_QE
  18. #define SPL_NO_EEPROM
  19. #endif
  20. #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
  21. #define SPL_NO_MMC
  22. #endif
  23. #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
  24. #define SPL_NO_IFC
  25. #endif
  26. #define CONFIG_REMAKE_ELF
  27. #define CONFIG_GICV2
  28. #include <asm/arch/stream_id_lsch2.h>
  29. #include <asm/arch/config.h>
  30. /* Link Definitions */
  31. #ifdef CONFIG_TFABOOT
  32. #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
  33. #else
  34. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  35. #endif
  36. #define CONFIG_SKIP_LOWLEVEL_INIT
  37. #define CONFIG_VERY_BIG_RAM
  38. #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
  39. #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
  40. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  41. #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
  42. #define CPU_RELEASE_ADDR secondary_boot_addr
  43. /* Generic Timer Definitions */
  44. #define COUNTER_FREQUENCY 25000000 /* 25MHz */
  45. /* Size of malloc() pool */
  46. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
  47. /* Serial Port */
  48. #define CONFIG_SYS_NS16550_SERIAL
  49. #define CONFIG_SYS_NS16550_REG_SIZE 1
  50. #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
  51. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  52. /* SD boot SPL */
  53. #ifdef CONFIG_SD_BOOT
  54. #define CONFIG_SPL_MAX_SIZE 0x17000
  55. #define CONFIG_SPL_STACK 0x1001e000
  56. #define CONFIG_SPL_PAD_TO 0x1d000
  57. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
  58. CONFIG_SPL_BSS_MAX_SIZE)
  59. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  60. #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
  61. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  62. #ifdef CONFIG_NXP_ESBC
  63. #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
  64. /*
  65. * HDR would be appended at end of image and copied to DDR along
  66. * with U-Boot image. Here u-boot max. size is 512K. So if binary
  67. * size increases then increase this size in case of secure boot as
  68. * it uses raw u-boot image instead of fit image.
  69. */
  70. #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  71. #else
  72. #define CONFIG_SYS_MONITOR_LEN 0x100000
  73. #endif /* ifdef CONFIG_NXP_ESBC */
  74. #endif
  75. /* NAND SPL */
  76. #ifdef CONFIG_NAND_BOOT
  77. #define CONFIG_SPL_PBL_PAD
  78. #define CONFIG_SPL_MAX_SIZE 0x1a000
  79. #define CONFIG_SPL_STACK 0x1001d000
  80. #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
  81. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  82. #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
  83. #define CONFIG_SPL_BSS_START_ADDR 0x80100000
  84. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  85. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  86. #ifdef CONFIG_NXP_ESBC
  87. #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
  88. #endif /* ifdef CONFIG_NXP_ESBC */
  89. #ifdef CONFIG_U_BOOT_HDR_SIZE
  90. /*
  91. * HDR would be appended at end of image and copied to DDR along
  92. * with U-Boot image. Here u-boot max. size is 512K. So if binary
  93. * size increases then increase this size in case of secure boot as
  94. * it uses raw u-boot image instead of fit image.
  95. */
  96. #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  97. #else
  98. #define CONFIG_SYS_MONITOR_LEN 0x100000
  99. #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
  100. #endif
  101. /* GPIO */
  102. #ifdef CONFIG_DM_GPIO
  103. #ifndef CONFIG_MPC8XXX_GPIO
  104. #define CONFIG_MPC8XXX_GPIO
  105. #endif
  106. #endif
  107. /* IFC */
  108. #ifndef SPL_NO_IFC
  109. #if defined(CONFIG_TFABOOT) || \
  110. (!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI))
  111. #define CONFIG_FSL_IFC
  112. /*
  113. * CONFIG_SYS_FLASH_BASE has the final address (core view)
  114. * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  115. * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  116. * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
  117. */
  118. #define CONFIG_SYS_FLASH_BASE 0x60000000
  119. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  120. #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
  121. #ifdef CONFIG_MTD_NOR_FLASH
  122. #define CONFIG_SYS_FLASH_QUIET_TEST
  123. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  124. #endif
  125. #endif
  126. #endif
  127. /* I2C */
  128. #if !CONFIG_IS_ENABLED(DM_I2C)
  129. #define CONFIG_SYS_I2C_LEGACY
  130. #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
  131. #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
  132. #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
  133. #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
  134. #else
  135. #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
  136. #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
  137. #endif
  138. /* PCIe */
  139. #ifndef SPL_NO_PCIE
  140. #define CONFIG_PCIE1 /* PCIE controller 1 */
  141. #define CONFIG_PCIE2 /* PCIE controller 2 */
  142. #define CONFIG_PCIE3 /* PCIE controller 3 */
  143. #ifdef CONFIG_PCI
  144. #define CONFIG_PCI_SCAN_SHOW
  145. #endif
  146. #endif
  147. /* DSPI */
  148. #ifndef SPL_NO_DSPI
  149. #ifdef CONFIG_FSL_DSPI
  150. #define CONFIG_SPI_FLASH_STMICRO /* cs0 */
  151. #define CONFIG_SPI_FLASH_SST /* cs1 */
  152. #define CONFIG_SPI_FLASH_EON /* cs2 */
  153. #endif
  154. #endif
  155. /* FMan ucode */
  156. #ifndef SPL_NO_FMAN
  157. #define CONFIG_SYS_DPAA_FMAN
  158. #ifdef CONFIG_SYS_DPAA_FMAN
  159. #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
  160. #ifdef CONFIG_TFABOOT
  161. #define CONFIG_SYS_FMAN_FW_ADDR 0x900000
  162. #define CONFIG_SYS_QE_FW_ADDR 0x940000
  163. #else
  164. #ifdef CONFIG_NAND_BOOT
  165. /* Store Fman ucode at offeset 0x900000(72 blocks). */
  166. #define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE)
  167. #elif defined(CONFIG_SD_BOOT)
  168. /*
  169. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  170. * about 1MB (2040 blocks), Env is stored after the image, and the env size is
  171. * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800).
  172. */
  173. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
  174. #define CONFIG_SYS_QE_FW_ADDR (512 * 0x4A00)
  175. #elif defined(CONFIG_QSPI_BOOT)
  176. #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
  177. #else
  178. /* FMan fireware Pre-load address */
  179. #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
  180. #define CONFIG_SYS_QE_FW_ADDR 0x60940000
  181. #endif
  182. #endif
  183. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  184. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  185. #endif
  186. #endif
  187. /* Miscellaneous configurable options */
  188. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
  189. #define CONFIG_HWCONFIG
  190. #define HWCONFIG_BUFFER_SIZE 128
  191. #ifndef SPL_NO_MISC
  192. #ifndef CONFIG_SPL_BUILD
  193. #define BOOT_TARGET_DEVICES(func) \
  194. func(MMC, mmc, 0) \
  195. func(USB, usb, 0) \
  196. func(DHCP, dhcp, na)
  197. #include <config_distro_bootcmd.h>
  198. #endif
  199. /* Initial environment variables */
  200. #define CONFIG_EXTRA_ENV_SETTINGS \
  201. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  202. "fdt_high=0xffffffffffffffff\0" \
  203. "initrd_high=0xffffffffffffffff\0" \
  204. "fdt_addr=0x64f00000\0" \
  205. "kernel_addr=0x61000000\0" \
  206. "scriptaddr=0x80000000\0" \
  207. "scripthdraddr=0x80080000\0" \
  208. "fdtheader_addr_r=0x80100000\0" \
  209. "kernelheader_addr_r=0x80200000\0" \
  210. "kernel_addr_r=0x81000000\0" \
  211. "kernel_start=0x1000000\0" \
  212. "kernelheader_start=0x800000\0" \
  213. "fdt_addr_r=0x90000000\0" \
  214. "load_addr=0xa0000000\0" \
  215. "kernelheader_addr=0x60600000\0" \
  216. "kernel_size=0x2800000\0" \
  217. "kernelheader_size=0x40000\0" \
  218. "kernel_addr_sd=0x8000\0" \
  219. "kernel_size_sd=0x14000\0" \
  220. "kernelhdr_addr_sd=0x3000\0" \
  221. "kernelhdr_size_sd=0x10\0" \
  222. "console=ttyS0,115200\0" \
  223. "boot_os=y\0" \
  224. "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
  225. BOOTENV \
  226. "boot_scripts=ls1043ardb_boot.scr\0" \
  227. "boot_script_hdr=hdr_ls1043ardb_bs.out\0" \
  228. "scan_dev_for_boot_part=" \
  229. "part list ${devtype} ${devnum} devplist; " \
  230. "env exists devplist || setenv devplist 1; " \
  231. "for distro_bootpart in ${devplist}; do " \
  232. "if fstype ${devtype} " \
  233. "${devnum}:${distro_bootpart} " \
  234. "bootfstype; then " \
  235. "run scan_dev_for_boot; " \
  236. "fi; " \
  237. "done\0" \
  238. "boot_a_script=" \
  239. "load ${devtype} ${devnum}:${distro_bootpart} " \
  240. "${scriptaddr} ${prefix}${script}; " \
  241. "env exists secureboot && load ${devtype} " \
  242. "${devnum}:${distro_bootpart} " \
  243. "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
  244. "env exists secureboot " \
  245. "&& esbc_validate ${scripthdraddr};" \
  246. "source ${scriptaddr}\0" \
  247. "qspi_bootcmd=echo Trying load from qspi..;" \
  248. "sf probe && sf read $load_addr " \
  249. "$kernel_start $kernel_size; env exists secureboot " \
  250. "&& sf read $kernelheader_addr_r $kernelheader_start " \
  251. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
  252. "bootm $load_addr#$board\0" \
  253. "nor_bootcmd=echo Trying load from nor..;" \
  254. "cp.b $kernel_addr $load_addr " \
  255. "$kernel_size; env exists secureboot " \
  256. "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
  257. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
  258. "bootm $load_addr#$board\0" \
  259. "nand_bootcmd=echo Trying load from NAND..;" \
  260. "nand info; nand read $load_addr " \
  261. "$kernel_start $kernel_size; env exists secureboot " \
  262. "&& nand read $kernelheader_addr_r $kernelheader_start " \
  263. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
  264. "bootm $load_addr#$board\0" \
  265. "sd_bootcmd=echo Trying load from SD ..;" \
  266. "mmcinfo; mmc read $load_addr " \
  267. "$kernel_addr_sd $kernel_size_sd && " \
  268. "env exists secureboot && mmc read $kernelheader_addr_r " \
  269. "$kernelhdr_addr_sd $kernelhdr_size_sd " \
  270. " && esbc_validate ${kernelheader_addr_r};" \
  271. "bootm $load_addr#$board\0"
  272. #undef CONFIG_BOOTCOMMAND
  273. #ifdef CONFIG_TFABOOT
  274. #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
  275. "env exists secureboot && esbc_halt;"
  276. #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
  277. "env exists secureboot && esbc_halt;"
  278. #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
  279. "env exists secureboot && esbc_halt;"
  280. #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
  281. "env exists secureboot && esbc_halt;"
  282. #else
  283. #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  284. #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
  285. "env exists secureboot && esbc_halt;"
  286. #elif defined(CONFIG_SD_BOOT)
  287. #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
  288. "env exists secureboot && esbc_halt;"
  289. #else
  290. #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
  291. "env exists secureboot && esbc_halt;"
  292. #endif
  293. #endif
  294. #endif
  295. /* Monitor Command Prompt */
  296. #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  297. #define CONFIG_SYS_MAXARGS 64 /* max command args */
  298. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  299. #include <asm/arch/soc.h>
  300. #endif /* __LS1043A_COMMON_H */