imx8mp_evk.h 3.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2019 NXP
  4. */
  5. #ifndef __IMX8MP_EVK_H
  6. #define __IMX8MP_EVK_H
  7. #include <linux/sizes.h>
  8. #include <linux/stringify.h>
  9. #include <asm/arch/imx-regs.h>
  10. #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
  11. #define CONFIG_SPL_MAX_SIZE (152 * 1024)
  12. #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
  13. #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
  14. #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
  15. #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
  16. #ifdef CONFIG_SPL_BUILD
  17. /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
  18. #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
  19. #define CONFIG_SPL_STACK 0x960000
  20. #define CONFIG_SPL_BSS_START_ADDR 0x0098FC00
  21. #define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KB */
  22. #define CONFIG_SYS_SPL_MALLOC_START 0x42200000
  23. #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
  24. #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
  25. #undef CONFIG_DM_MMC
  26. #undef CONFIG_DM_PMIC
  27. #undef CONFIG_DM_PMIC_PFUZE100
  28. #define CONFIG_POWER
  29. #define CONFIG_POWER_I2C
  30. #define CONFIG_POWER_PCA9450
  31. #define CONFIG_SYS_I2C_LEGACY
  32. #endif
  33. #if defined(CONFIG_CMD_NET)
  34. #define CONFIG_ETHPRIME "eth1" /* Set eqos to primary since we use its MDIO */
  35. #define CONFIG_FEC_XCV_TYPE RGMII
  36. #define CONFIG_FEC_MXC_PHYADDR 1
  37. #define FEC_QUIRK_ENET_MAC
  38. #define DWC_NET_PHYADDR 1
  39. #ifdef CONFIG_DWC_ETH_QOS
  40. #define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */
  41. #endif
  42. #define PHY_ANEG_TIMEOUT 20000
  43. #endif
  44. #ifndef CONFIG_SPL_BUILD
  45. #define BOOT_TARGET_DEVICES(func) \
  46. func(MMC, mmc, 1) \
  47. func(MMC, mmc, 2)
  48. #include <config_distro_bootcmd.h>
  49. #endif
  50. /* Initial environment variables */
  51. #define CONFIG_EXTRA_ENV_SETTINGS \
  52. BOOTENV \
  53. "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
  54. "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
  55. "image=Image\0" \
  56. "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
  57. "fdt_addr_r=0x43000000\0" \
  58. "boot_fdt=try\0" \
  59. "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
  60. "initrd_addr=0x43800000\0" \
  61. "bootm_size=0x10000000\0" \
  62. "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
  63. "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
  64. /* Link Definitions */
  65. #define CONFIG_LOADADDR 0x40480000
  66. #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  67. #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
  68. #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
  69. #define CONFIG_SYS_INIT_SP_OFFSET \
  70. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  71. #define CONFIG_SYS_INIT_SP_ADDR \
  72. (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  73. #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
  74. /* Size of malloc() pool */
  75. #define CONFIG_SYS_MALLOC_LEN SZ_32M
  76. /* Totally 6GB DDR */
  77. #define CONFIG_SYS_SDRAM_BASE 0x40000000
  78. #define PHYS_SDRAM 0x40000000
  79. #define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */
  80. #define PHYS_SDRAM_2 0x100000000
  81. #define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */
  82. #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
  83. /* Monitor Command Prompt */
  84. #define CONFIG_SYS_CBSIZE 2048
  85. #define CONFIG_SYS_MAXARGS 64
  86. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  87. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  88. sizeof(CONFIG_SYS_PROMPT) + 16)
  89. #define CONFIG_FSL_USDHC
  90. #define CONFIG_SYS_FSL_USDHC_NUM 2
  91. #define CONFIG_SYS_FSL_ESDHC_ADDR 0
  92. #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
  93. #define CONFIG_SYS_I2C_SPEED 100000
  94. #endif